Memory test method, device, apparatus and storage medium

Abstract

The present disclosure provides a memory test method, device, equipment and storage medium, and relates to the technical field of memory test. The method comprises: obtaining a plurality of non-intersecting memory test units; testing each memory test unit by using a plurality of cores to obtain the test time of each core on each memory test unit; and matching a memory test unit group for each core according to the test time of each core on each memory test unit, so as to test the memory based on the matching relationship between the core and the memory test unit group, wherein the difference between the test time of the memory test unit groups corresponding to any two cores is within a preset time range, and any two memory test unit groups are non-intersecting. The memory test method, device, equipment and storage medium provided by the present disclosure bind the memory to the core without an operating system, thereby improving the test efficiency.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a memory testing method, a memory testing apparatus, a testing device and a computer readable storage medium. BACKGROUND

[0002] DRAM (Dynamic Random Access Memory), also known as memory, is the most common system memory. DRAM memory is one of the important components in a computer, which is a bridge for communication with the CPU. All programs in the computer are run in the memory, so the performance of the memory has a great influence on the computer. How to test the memory to ensure the normal operation of the memory is very important.

[0003] However, most of the current memory tests are performed in an operating system, and a multi-core computer runs a multi-process test program for testing, which requires a process scheduler to schedule between different processes. The operating system will occupy most of the content, and accordingly, the testable memory will be reduced, and the test efficiency will be reduced.

[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0005] The present disclosure provides a memory testing method, apparatus, device and storage medium, which at least partly overcomes the problem of low efficiency of existing memory testing provided in the related art.

[0006] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description, or will be learned by practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a memory testing method is provided, comprising: obtaining a plurality of disjoint memory testing units; testing each memory testing unit by using a plurality of cores to obtain a test time of each memory testing unit by each core; and matching a memory testing unit group for each core according to the test time of each memory testing unit by each core, to test the memory based on the matching relationship between the core and the memory testing unit group, wherein the difference between the test times of the memory testing unit groups corresponding to any two cores is within a preset time range, and any two memory testing unit groups are disjoint.

[0008] In one embodiment of the present disclosure, the testing the memory based on the matching relationship between the core and the memory test unit group comprises: determining a target thread corresponding to the core according to a preset core thread binding relationship; binding the target thread to the core and binding the target thread to a memory test unit group corresponding to the core until the core and the memory test unit group are bound, and starting the testing.

[0009] In one embodiment of the present disclosure, the binding the target thread to the memory test unit group corresponding to the core comprises: obtaining a test parameter of the memory test unit group corresponding to the core; and inputting the test parameter to the target thread to bind the memory test unit group to the target thread.

[0010] In one embodiment of the present disclosure, before the determining the target thread corresponding to the core according to the preset core thread binding relationship, the method further comprises: constructing a core thread binding relationship between the core and the thread according to a preset binding rule.

[0011] In one embodiment of the present disclosure, the binding the target thread to the core comprises: binding the target thread to the core based on a unified extensible firmware interface.

[0012] In one embodiment of the present disclosure, the obtaining a plurality of disjoint memory test units comprises: determining the number of the memory test units according to the number of memory particles and the number of cores of a CPU; and dividing the memory into a plurality of disjoint memory test units according to the number of the memory test units, wherein the capacity of each memory test unit is the same.

[0013] In one embodiment of the present disclosure, the testing each memory test unit by using a plurality of cores to obtain the testing time of each core on each memory test unit comprises: storing the testing time of each core on each memory test unit in a testing time matrix table.

[0014] In one embodiment of the present disclosure, the matching the memory test unit group to each core according to the testing time of each core on each memory test unit comprises: dividing a plurality of memory test units into a plurality of memory test unit groups based on the number of cores; calculating the testing time of the plurality of memory test unit groups according to the testing time of each core on each memory test unit; and matching the plurality of memory test unit groups to the plurality of cores if the difference between the testing time of any two memory test units is within a preset time range, wherein the memory test units in one memory test unit group belong to the same memory particle, and one memory test unit group corresponds to one core.

[0015] In one embodiment of the present disclosure, the method further comprises: if there is a difference between the test times of two memory test unit groups that is not within the preset time range, adjusting part of the memory test units in the two memory test unit groups until the difference between the test times of the two memory test unit groups is within the preset time range.

[0016] In one embodiment of the present disclosure, the matching of the memory test unit groups to the cores according to the test times of the memory test units by the cores comprises: dividing a plurality of memory test units into a plurality of memory test unit groups based on the number of cores; calculating the average test time of the memory test unit groups and the test times of the plurality of memory test unit groups according to the test times of the memory test units by the cores; and matching the plurality of memory test unit groups to the plurality of cores if the difference between the test time of each memory test unit group and the average test time of the memory test unit groups is within the preset time range, wherein the memory test units in one memory test unit group belong to the same memory grain, and one memory test unit group corresponds to one core.

[0017] In one embodiment of the present disclosure, the method further comprises: if the difference between the test time of one memory test unit group and the average test time of the memory test unit groups is not within the preset time range, sorting the plurality of memory test unit groups in a preset order, determining a first memory test unit group corresponding to the maximum test time and a second memory test unit group corresponding to the minimum test time, and exchanging at least one memory test unit in the first memory test unit group and the second memory test unit group until the difference between the test time of the exchanged memory test unit group and the average test time of the memory test unit is within the preset time range.

[0018] In one embodiment of the present disclosure, the test time of the memory test unit group is the sum of the test times of the memory test units in the memory test unit group, or the test time of the memory test unit group is the average of the test times of the memory test units in the memory test unit group.

[0019] According to another aspect of the present disclosure, a memory testing device is also provided, comprising: an obtaining module configured to obtain a plurality of disjoint memory testing units; a time-consuming module configured to test each memory testing unit by using a plurality of cores to obtain a testing time of each memory testing unit by each core; and a matching module configured to match a memory testing unit group for each core according to the testing time of each memory testing unit by each core, and test the memory based on the matching relationship between the core and the memory testing unit group, wherein the difference between the testing time of any two memory testing unit groups corresponding to two cores is within a preset time range, and any two memory testing unit groups are disjoint.

[0020] According to another aspect of the present disclosure, a testing device is also provided, comprising a processor and a memory configured to store executable instructions of the processor; wherein the processor is configured to execute the above memory testing method by executing the executable instructions.

[0021] According to another aspect of the present disclosure, a computer readable storage medium is also provided, which stores a computer program, and the computer program is executed by a processor to implement the above memory testing method.

[0022] According to another aspect of the present disclosure, a computer program product is also provided, which comprises a computer program or computer instructions, and the computer program or the computer instructions are loaded and executed by a processor to make a computer implement the above memory testing method.

[0023] The present disclosure provides a memory testing method, device, equipment and storage medium, by obtaining a plurality of disjoint memory testing units; testing each memory testing unit by using a plurality of cores to obtain a testing time of each memory testing unit by each core; matching a memory testing unit group for each core according to the testing time of each memory testing unit by each core, the difference between the testing time of any two memory testing unit groups corresponding to two cores is within a preset time range, and the running time of the plurality of cores can be close by binding a memory testing unit group for each core; the memory testing units in each memory testing unit group are disjoint, so as to prevent a core from testing a plurality of memory testing units multiple times, shorten the testing time, ensure that the physical addresses of the memory testing unit groups are independent of each other and do not affect each other, realize the binding of the memory to the core, and the testing device does not need an operating system and thread switching, thereby greatly improving the memory testing efficiency.

[0024] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0025] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, further serve to explain the principles of the present disclosure. It is apparent that the accompanying drawings, in the following description, are only some embodiments of the present disclosure, and other drawings can be obtained by those of ordinary skill in the art without creative effort based on these drawings.

[0026] Figure 1 A structure schematic diagram of a multi-CPU multi-core memory test provided in an embodiment of the present disclosure is shown.

[0027] Figure 2 A relationship diagram among programs, processes and threads in an operating system in an embodiment of the present disclosure is shown.

[0028] Figure 3 A single-thread and multi-thread running schematic diagram in a same process in an embodiment of the present disclosure is shown.

[0029] Figure 4 A multi-to-multi model schematic diagram between a core and a thread in an embodiment of the present disclosure is shown.

[0030] Figure 5 A one-to-one model schematic diagram between a core and a thread provided in an embodiment of the present disclosure is shown.

[0031] Figure 6 A model schematic diagram of a memory, a thread and a core provided in an embodiment of the present disclosure is shown.

[0032] Figure 7 A flowchart of a memory test method provided in an embodiment of the present disclosure is shown.

[0033] Figure 8 A flowchart of a memory test unit group and core matching method provided in an embodiment of the present disclosure is shown.

[0034] Figure 9 A flowchart of another memory test unit group and core matching method provided in an embodiment of the present disclosure is shown.

[0035] Figure 10 A flowchart of another memory test method provided in an embodiment of the present disclosure is shown.

[0036] Figure 11 A structure schematic diagram of a memory test device provided in an embodiment of the present disclosure is shown.

[0037] Figure 12 A framework diagram of a test device provided in an embodiment of the present disclosure is shown.

[0038] Figure 13 A schematic diagram of a computer program product provided in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0039] Preferred embodiments of the present disclosure will be described in more detail with reference to the drawings. Although the preferred embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0040] The terms "first", "second", etc. are used only for the purpose of description and should not be understood as indicating or implying relative importance or implying that the indicated technical features are limited to one or more of the indicated technical features. Therefore, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0041] In the description of the present application, it is to be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting" should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection or can communicate with each other; it can be directly connected, or indirectly connected through intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0042] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and arrangements of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeatedly refer to numbers and / or letters in different examples, and such repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or arrangements discussed.

[0043] When performing DRAM testing, the test equipment usually adopts a multi-CPU, multi-core structure, such as a multi-CPU multi-core computer. Figure 1 A structure diagram of a multi-CPU multi-core for memory testing provided in an embodiment of the present disclosure is shown. As shown in Figure 1 The test equipment includes four CPUs, each CPU includes two cores, and each core is connected to a corresponding DRAM to be tested, and the test data is stored in the cache memory Cache.

[0044] In the operating system of the test equipment, a program refers to a set of instructions instructing the test equipment (for example, a computer or other information processing device) to perform an action or make a judgment, usually written in a certain programming language and running on a certain target computer architecture, for example, a program can be written in C language, Java language, etc.

[0045] A process is a running activity of a software program on a certain data set in a computer, is a basic unit of resource allocation and scheduling of an operating system, memory, variables, etc., and is the basis of operating system structure.

[0046] A thread is an entity in a process and is a basic unit of independent scheduling and allocation by a system, and a thread itself does not own operating system resources, but the thread can share all resources owned by the process, such as memory and code segment, with other threads belonging to the process.

[0047] It should be noted that a process is an entity of a program, and a thread is an entity of a process, and a process is a container of a thread.

[0048] Figure 2 A relationship diagram between a program, a process and a thread in an operating system in the embodiment of the present disclosure is shown. As shown in Figure 2 Two sets of programs are developed in the operating system, which are program A and program B, wherein program A binds two processes, which are process 1 and process 2, process 1 binds one thread 1, and process 2 binds two threads 1; program B binds one process, which is program 3 in Figure 2 , and program 3 binds one thread 1.

[0049] Figure 3 A single-thread and multi-thread running schematic diagram in the same process in the embodiment of the present disclosure is shown. As shown in Figure 3 , in each single-thread or multi-thread, multiple time slices are divided. For a single thread, a set program can be executed in each time slice to realize DRAM testing. For multi-thread, multiple threads share all resources owned by the process, and only one thread in the multi-thread runs in a certain time slice, and the remaining threads in the multi-thread are in a ready state. Only when the thread in the running state is run, the remaining threads in the ready state can be scheduled by the scheduler.

[0050] As shown in Figure 4 , in the many-to-many model between the CPU kernel and the thread, there is resource sharing between multiple threads, and the use of the shared resources is coordinated with each other, so as to give up or obtain the use right of the CPU execution time slice.

[0051] In a scheduling period, when the CPU scheduling time slice arrives, the thread in the running state saves the context, suspends, and reassigns the CPU resource to the corresponding thread according to the preset algorithm, and executes the current time slice. After the current time slice is executed, the next scheduling period is entered, and this is repeated until all the time slices are completed. For example, in a scheduling period, when the CPU scheduling time slice arrives, threads 1-3 save the context and suspend, and the scheduler assigns the CPU resource (kernel K1) to thread 1 to execute the current time slice. After thread 1 executes the current time slice, the next scheduling period is entered. Threads 1-3 save the context and suspend, and the scheduler reassigns the CPU resource (kernel K1) to thread 2 to execute the time slice, and this is repeated until all the threads are executed.

[0052] In summary, it can be found that, when testing DRAM using a multi-process test program, in the presence of an operating system, the scheduler needs to schedule between processes, and the operating system occupies a large part of the memory, which accordingly reduces the testable memory. On the other hand, due to the switching between processes and the time difference in memory access by the kernel, in an extreme case, the memory test speed of one kernel is very slow, while the access efficiency of some memory to some kernels is very high, and the randomness of the scheduler cannot access these memories, thereby causing the technical problem of low test efficiency.

[0053] Therefore, how to improve the memory test efficiency has become one of the problems to be solved.

[0054] In order to facilitate the overall understanding of the technical solutions provided by the embodiments of the present disclosure, the binding model between the kernel and the thread provided by the embodiments of the present disclosure is described below.

[0055] Figure 5 A one-to-one model between the kernel and the thread provided by the embodiments of the present disclosure is shown. As shown in Figure 5 For the one-to-one model, one thread uniquely uses one kernel, and the thread and the kernel are one-to-one corresponding. Different threads are independently concurrently executed, the CPU call can be saved, there is no switching between threads, the memory test can be implemented without the operating system, each thread exclusively uses the CPU resource, thereby avoiding the occurrence of mutual exclusion or deadlock until the program ends.

[0056] For example, in Figure 5 , the test device includes four kernels K0-K3, and four threads are set, which are threads 1-4. Specifically, the kernel K0 is bound to the thread 4, and the kernels K1-K3 are bound to the threads 1-3, respectively, to construct a one-to-one model between the CPU kernel and the thread.

[0057] Figure 6A model schematic diagram between a memory to be tested, a thread and a core is shown. As shown in Figure 6 From the perspective of a thread, parallelism refers to that there is no data sharing or communication between multiple threads, multiple threads can be run by using the parallelism of a CPU, and the one-to-one model does not need to switch an operating system, and the memory test efficiency can be improved.

[0058] Based on this, the technical scheme provided by the embodiments of the present disclosure is that a plurality of memory test units without intersection are obtained; each memory test unit is tested by using a plurality of cores to obtain the test time of each memory test unit by each core; and a memory test unit group is matched for each core according to the test time of each memory test unit by each core, the difference in test time of the memory test unit groups corresponding to any two cores is within a preset time range, the running time of the plurality of cores can be made close by binding the memory test unit group for each core; the memory test units in each memory test unit group are without intersection, so that multiple memory test units are prevented from being tested by one core multiple times, the test time is shortened, the physical addresses of the memory test unit groups are ensured to be independent of each other and not to affect each other, the binding of the memory to the core is realized, the test device does not need an operating system and thread switching, and the memory test efficiency is greatly improved.

[0059] The example embodiments will be described in detail below with reference to the accompanying drawings and examples.

[0060] First, a memory test method is provided in the embodiments of the present disclosure, which can be executed by any electronic device with computing processing capability.

[0061] Figure 7 A flowchart of a memory test method provided by the embodiments of the present disclosure is shown. As shown in Figure 7 In one embodiment, a memory test method includes:

[0062] S702, a plurality of memory test units without intersection are obtained.

[0063] In one embodiment, the memory test unit can be represented by parameters such as memory ID, start address and end address. On the one hand, the address intervals formed by the start address and the end address of different memory test units are without intersection, so as to ensure that the memory test units are independent of each other. On the other hand, the start address and the end address of adjacent memory test units are continuous, so that the memory can be completely contained in the corresponding memory test unit.

[0064] There are various ways to divide the memory into a plurality of memory test units, for example, the memory can be divided according to the number of memory particles and the number of cores of the CPU, or the memory can be divided according to the multiple of the number of memory particles and the number of cores of the CPU, as long as the divided memory test units are without intersection, which is not limited in the present disclosure.

[0065] It is worth noting that for the number of memory test units, on the one hand, the memory needs to be divided into as many disjoint memory test units as possible, so that when the test times of different threads are greatly different, the test times of each thread can be adjusted to be close to each other, and the adjustment flexibility is improved, on the other hand, the number of memory test units is not the more the better, and too many memory test units can easily increase the calculation amount, and the memory test time is not significantly shortened.

[0066] S704, testing each memory test unit by using a plurality of cores to obtain the test time of each memory test unit by each core.

[0067] The purpose of testing the memory test unit by the core is to record the time of writing data and reading data once, so as to estimate the time of executing the test task by the memory test unit.

[0068] The above-mentioned testing each memory test unit by using a plurality of cores can write a certain data into a memory test unit by one core, read the data from the above-mentioned memory test unit, compare whether the written data and the read data are consistent, record the writing data time and the reading data time, and take the difference between the reading data time and the writing data time as the test time of the above-mentioned memory test unit; all memory test units are tested in turn by the above-mentioned core to obtain the test time of each memory test unit by the core; the remaining cores are sequentially tested on each memory test unit to obtain the test time of each memory test unit by the remaining cores.

[0069] In one embodiment, the above-mentioned S704 further comprises: storing the test time of each memory test unit by each core in a test time matrix table, and the test time matrix table is used to represent the corresponding relationship between each core and the test time of each memory test unit, so as to facilitate subsequent tracking and timely confirmation of abnormalities.

[0070] It should be noted that in addition to recording the test time of the core on the memory test unit by using the test time matrix table, a scatter plot or the like can also be used to represent, and the present disclosure is not limited specifically.

[0071] S706, according to the test time of each memory test unit by each core, matching the memory test unit group for each core, so as to test the memory based on the matching relationship between the core and the memory test unit group, wherein the difference between the test times of the memory test unit groups corresponding to any two cores is within a preset time range, and any two memory test unit groups are disjoint.

[0072] The memory test unit group can include at least one memory test unit, and when the memory test units in the memory test unit group are multiple, the multiple memory test units are disjointed, so that any two memory test unit groups are disjointed, independent of each other, and do not affect each other, and independent running of threads can be realized.

[0073] The test time of the memory test unit group is determined by the test time of the memory test units in the memory test unit group, and can be the sum of the test times of the memory test units in the memory test unit group or the average of the test times of the memory test units in the memory test unit group.

[0074] By limiting the difference between the test times of the memory test unit groups corresponding to any two cores within a preset time range, the test time of each memory test unit group is ensured to be substantially the same, that is, to start at the same time and end at the same time, so as to shorten the total test time of the memory.

[0075] The preset time range can be preset in the matching module of the test device, and the preset time range can be determined according to actual conditions, for example, the preset time range can be [0, 5ms], and the like, without specific limitation.

[0076] It should be noted that the above-mentioned preset time range is only an example provided for describing the embodiments of the present disclosure, and should not be regarded as a limitation on the protection scope of the present disclosure. The value of the preset time range can be determined according to specific conditions.

[0077] The memory test method provided by the embodiments of the present disclosure includes the following steps: obtaining multiple disjointed memory test units; testing each memory test unit by using multiple cores to obtain the test time of each memory test unit by each core; and matching a memory test unit group for each core according to the test time of each memory test unit by each core, so that the difference between the test times of the memory test unit groups corresponding to any two cores is within a preset time range, the running time of the multiple cores is close by binding the memory test unit group for each core, the memory test units in each memory test unit group are disjointed, so that multiple memory test units are prevented from being tested by one core multiple times, the test time is shortened, the physical addresses of the memory test unit groups are independent of each other and do not affect each other, the binding of the memory to the core is realized, the test device does not need an operating system and thread switching, and the memory test efficiency is greatly improved.

[0078] In one embodiment, the plurality of non-intersecting memory test units in S702 above are obtained by: determining the number of memory test units according to the number of memory particles and the number of CPU cores; dividing the memory into a plurality of non-intersecting memory test units according to the number of memory test units, each memory test unit having the same capacity, thereby ensuring that the test times of different memory test units are close or substantially the same, and at the same time, if there is a memory test unit with a very large capacity, it is possible that one core corresponds to only one memory test unit, resulting in that subsequent cores cannot be fully allocated to each memory test unit group.

[0079] Assuming that the number of memory particles is M, the number of CPU cores is K, and the number of memory test units is N = M x K, the memory test units divided by the number of memory particles and the number of cores are independent of each other, and each memory test unit is non-intersecting. The memory test unit can be identified by the memory ID, start address and end address used to distinguish the plurality of memories to be tested.

[0080] Obtain the total capacity V of the memory that the test system can test, then the capacity E of each memory test unit is V / N.

[0081] The memory test units are sequentially numbered as memory test unit 0, memory test unit 1, …, memory test unit N-1; and the cores are sequentially labeled as core 0, core 1, …, core K-1.

[0082] Each of the cores 1 to K-1 is used to test the test units 0 to K-1 to obtain the test times of the cores 1 to K-1 on the memory test units 0 to K-1.

[0083] For example, if the number of memory particles is 64 and the number of CPU cores is 4, the memory can be divided into 256 memory test units, which are labeled as memory test unit 0, memory test unit 1, …, memory test unit 255; and the cores are labeled as core 0, core 1, …, core 3.

[0084] The present disclosure divides non-intersecting memory test units according to the number of memory particles and the number of CPU cores, which on the one hand ensures that each memory test unit is non-intersecting and independent of each other, and the divided memory test units have sufficient number; on the other hand, the divided memory test units can cover all addresses of the memory, ensuring the integrity of the memory test.

[0085] Figure 8 A flow chart of a memory test unit group and core matching method provided by an embodiment of the present disclosure is shown. As shown in Figure 8 In one embodiment, S706 above matches the memory test unit group for each core according to the test time of each core on each memory test unit, comprising:

[0086] S802, divide the plurality of memory test units into a plurality of memory test unit groups according to the number of cores.

[0087] For memory test unit division, according to the number of memory particles and the number of cores, in order to facilitate operation, the plurality of memory test units are divided into a plurality of memory test unit groups according to the number of cores.

[0088] It should be noted that due to the difference in test time of different memory test units, each memory test unit group can contain the same number of memory test units, or different number of memory test units, which can be adjusted according to actual situation.

[0089] S804, according to the test time of each memory test unit of each core, calculate the test time of the plurality of memory test unit groups.

[0090] The test time of the memory test unit group can be the sum of the test time of the memory test unit in the memory test unit group, or the test time of the memory test unit group can be the average of the test time of the memory test unit in the memory test unit group. It should be noted that when the number of memory test units in the memory test unit group is different, only the sum of the test time of the memory test unit in the memory test unit group can be used as the test time of the memory test unit group.

[0091] In one embodiment, the test time of each memory test unit group, the memory test unit ID in each memory test unit group and other information can be recorded in the test time statistics table, so as to adjust the memory test unit according to the test time statistics table.

[0092] S806, if the difference between the test time of any two memory test units is within the preset time range, match the plurality of memory test unit groups with the plurality of cores, wherein the memory test units in one memory test unit group belong to the same memory particle, and one memory test unit group corresponds to one core.

[0093] The difference between the test time of any two memory test unit groups is calculated, and the relationship between the above difference and the preset time range is compared. When the difference between the test time of any two memory test unit groups is within the preset time range, it indicates that the test time of any two memory test unit groups is close, the memory test unit group can be matched with the core, and one memory test unit group corresponds to one core, so as to ensure the binding of memory to core, improve the memory test efficiency and shorten the memory test time.

[0094] For example, when the number of cores is 4 and the number of memory test units is 256, the memory test units can be divided into 4 memory test unit groups (memory test unit groups 0-3) based on the number of cores, and each memory test unit group initially contains 64 memory test units.

[0095] After calculating the test time of the 64 memory test units in each of the memory test unit groups 0-3, the test time of each memory test unit group is obtained. The difference between the test time of the memory test unit group 0 and the test time of the memory test unit groups 1-3, the difference between the test time of the memory test unit group 1 and the test time of the memory test unit groups 2-3, and the difference between the test time of the memory test unit group 2 and the test time of the memory test unit group 3 are calculated respectively. It is determined whether the above differences are within a preset time range. If the differences are within the preset time range, it indicates that the test time of the memory test unit groups 0-3 is close, and the memory test unit groups 0-3 can be matched with the cores 0-3.

[0096] The memory test units in one memory test unit group belong to the same memory particle, and the test time difference caused by the physical location difference of the particles can be improved.

[0097] Optionally, the memory test method provided by the embodiment of the disclosure further includes: if the difference between the test time of two memory test unit groups is not within a preset time range, adjusting part of the memory test units in the two memory test unit groups until the difference between the test time of the two memory test unit groups is within the preset time range.

[0098] In one embodiment, when the difference between the test time of two memory test unit groups is not within a preset time range, it indicates that the test time difference of the two memory test unit groups is large, and it cannot be guaranteed that each thread is started and ended at the same time, resulting in a long memory test time. Therefore, the memory test units in the memory test unit groups need to be adjusted so that the difference between the test time of the adjusted memory test unit groups is within the preset time range.

[0099] For the two memory test unit groups, the memory test units in the memory test unit group with larger test time can be exchanged with the memory test units in the memory test unit group with smaller test time. For example, both of the two memory test unit groups include 64 memory test units, the test time of one memory test unit group is 3s, the test time of the other memory test unit group is 4s, the difference between the two is 1s, the preset time range is [0, 0.8s], so the above difference is not within the preset time range, and the memory test units in the above two memory test unit groups need to be adjusted. In the adjustment, the memory test unit with a test time of 200ms in the other memory test unit group can be adjusted to the above one memory test unit group, and the memory test unit with a test time of 300ms in the other memory test unit group can be adjusted to the above one memory test unit group, and the memory test unit with a test time of 100ms in the above one memory test unit group can be adjusted to the above other memory test unit group.

[0100] It should be noted that there are many ways to adjust the memory test units in the memory test unit group so that the difference between the test times of the two memory test unit groups is within the preset time range. The above is only an example provided for the purpose of illustrating the embodiments of the present disclosure and should not be regarded as a limitation on the protection scope of the present disclosure. In actual implementation, the memory test units and their quantities that need to be adjusted in the memory test unit group can be selected according to specific circumstances, and the present disclosure does not make specific limitations.

[0101] The memory test method provided by the embodiments of the present disclosure divides a plurality of memory test units into a plurality of memory test unit groups based on the number of cores. When the difference between the test times of any two memory test unit groups is within the preset time range, it indicates that the test times of each memory test unit group are close, and the memory test unit group can be matched with the core. When the difference between the test times of two memory test unit groups is not within the preset time range, it indicates that the test times of the above two memory test unit groups differ greatly, and it is impossible to guarantee that the threads are started and ended at the same time. By adjusting part of the memory test units, the test times of the memory test unit groups are close, which is convenient for adjustment and shortens the memory test time.

[0102] Figure 9 Another flowchart of a method for matching a memory test unit group with a core is shown. As shown in FIG. 8, in one embodiment, S706 matches the memory test unit group with the core according to the test time of each memory test unit for each core, which includes: Figure 9

[0103] S902, divide a plurality of memory test units into a plurality of memory test unit groups based on the number of cores.

[0104] ​For the division of the memory test units, according to the number of memory particles and the number of cores, in order to facilitate operation, a plurality of memory test units are divided into a plurality of memory test unit groups according to the number of cores. When initially dividing the memory test unit groups, the number of memory test units in each memory test unit group is the same.

[0105] S904, according to the test time of each memory test unit by each core, the test time average of the memory test unit group and the test time of the plurality of memory test unit groups are calculated.

[0106] The test time of the memory test unit group can be the sum of the test times of the memory test units in the memory test unit group, or the test time of the memory test unit group is the average of the test times of the memory test units in the memory test unit group. It should be noted that when the number of memory test units in the memory test unit group is different, the test time of the memory test unit is used as the test time of the memory test unit group.

[0107] The test time average of the memory test unit group is obtained according to the test time of the memory test unit in the memory test unit group and the number of memory test units, and the test time average of the memory test unit group is used as the basis for adjustment.

[0108] S906, if the difference between the test time of each memory test unit group and the test time average of the memory test unit group is within the preset time range, the plurality of memory test unit groups are matched with the plurality of cores, wherein the memory test units in one memory test unit group belong to the same memory particle, and one memory test unit group corresponds to one core.

[0109] In one embodiment, the difference between the test time of each memory test unit group and the test time average of the memory test unit group is calculated, and then according to the relationship between the difference and the preset time range, it is confirmed whether the memory test units in the memory test unit group are adjusted.

[0110] The preset time range is pre-configured in the matching module of the test equipment, for example, the preset time range is [-0.5s, 0.5s], which can be determined according to the actual situation, and the present disclosure is not limited.

[0111] The memory test units in one memory test unit group belong to the same memory particle, which can improve the test time difference caused by the difference in physical location of the particles.

[0112] Optionally, the memory testing method provided by the embodiment of the present disclosure further comprises: if the difference between the test time of one memory testing unit group and the average test time of the memory testing unit group is not within the preset time range, sorting the plurality of memory testing unit groups according to a preset order, determining a first memory testing unit group corresponding to the maximum test time and a second memory testing unit group corresponding to the minimum test time; and exchanging at least one memory testing unit in the first memory testing unit group and the second memory testing unit group until the difference between the test time of the memory testing unit group after the exchange and the average test time of the memory testing unit is within the preset time range.

[0113] The preset order can sort the memory testing unit groups in descending order or ascending order, and the first memory testing unit group corresponding to the maximum test time and the second memory testing unit group corresponding to the minimum test time are filtered from the sorting result, and part of the memory testing units in the above two memory testing unit groups are exchanged until the difference between the test time of the above two memory testing unit groups after the exchange and the average test time is within the preset range.

[0114] It should be noted that when exchanging part of the memory testing units, the implementation of the above embodiment can be referred to, which will not be described here.

[0115] The memory testing method provided by the embodiment of the present disclosure divides the plurality of memory testing units into a plurality of memory testing unit groups based on the number of cores, takes the average test time of the memory testing unit group as the adjustment reference, when the difference between the test time of the memory testing unit group and the average test time is within the preset time range, the test time of each memory testing unit group is close, and the memory testing unit group is matched with the core, when the difference between the test time of the memory testing unit group and the average test time is not within the preset time range, it indicates that the test time of the above two memory testing unit groups is quite different, which cannot guarantee that the threads are started and ended at the same time, and the test time of the memory testing unit group is close by adjusting part of the memory testing units. This adjustment method is convenient and shortens the memory testing time.

[0116] Figure 10 Another flowchart of a memory testing method provided by the embodiment of the present disclosure is shown. In Figure 7 On the basis of the embodiment, steps S708-S710 are added to bind the core, thread and memory testing unit group, so as to test the memory based on the matching relationship between the core and the memory testing unit group. In one embodiment, as Figure 10 shown, the method comprises S702-S710, specifically comprising:

[0117] S708, according to the preset core thread binding relationship, determining a target thread corresponding to one core;

[0118] S710, binding the target thread to a core, binding the target thread to a memory test unit group corresponding to the core, until the core is bound to the memory test unit group, and starting the test.

[0119] In one embodiment, before S708, the method further comprises: constructing a core thread binding relationship between the core and the thread according to a preset core thread binding relationship.

[0120] The preset binding rule is used to determine the correspondence between the core and the thread, and the preset binding rule is by default a one-to-one correspondence of the core ID and the thread ID from small to large, which can also be adjusted according to the instructions of the tester, and is not limited.

[0121] The core thread binding relationship is used to indicate the correspondence between the core and the thread, and the core thread binding relationship can be stored in the binding module of the test device in the form of a core thread binding relationship table. The core thread binding relationship table contains the core ID and the thread ID, thereby determining the correspondence between the two, facilitating quick determination of the target thread.

[0122] The core and the thread are bound through a unified extensible firmware interface.

[0123] In one embodiment, S710 binds the target thread to a memory test unit group corresponding to a core, including: obtaining test parameters of the memory test unit group corresponding to the core; and inputting the test parameters to the target thread to bind the memory test unit group to the target thread.

[0124] The core and the memory test unit group corresponding to the core test the memory test unit group through the target thread, and the target thread can be determined according to actual conditions, for example, by determining the target thread corresponding to the core through a preset core thread binding relationship.

[0125] The test parameters of the memory test unit group include a memory ID, a start address and an end address of a memory test unit in the memory test unit group, and the like, and inputting the test parameters of the memory test unit group to the target thread can bind the memory test unit group to the target thread.

[0126] The present disclosure determines the target thread through a preset core thread binding relationship, binds the core, the target thread, and the memory, and starts the test, without a process scheduler, greatly reducing the engineering implementation difficulty, realizing parallel testing of the memory test process, improving the test efficiency, avoiding the problem of mutual exclusion resource lock, and short-term process lock affecting the test.

[0127] For the convenience of understanding the memory testing method provided by the present disclosure, the following will be described in combination with specific examples.

[0128] The overall flow of the memory testing method is as follows:

[0129] 1. The memory testing unit is divided, and the testing time of each core for each memory testing unit is calculated.

[0130] 2. The memory binding core list with the best testing time is obtained according to the testing time.

[0131] 3. A thread is bound to each core, and each thread executes the same testing algorithm.

[0132] 4. The testing memory of the core-bound thread is allocated according to the memory core binding core list.

[0133] 5. The core testing memory is started.

[0134] For dividing the memory testing unit and calculating the testing time of each core for each memory testing unit, the following process can be implemented:

[0135] a) According to the number of DRAM memory particles M and the number of cores K, the number of memory testing units N of memory division is M×K;

[0136] b) The total capacity V of the system testable memory is obtained, and the memory is divided into N memory testing units, and the capacity E of each memory testing unit is V / N;

[0137] c) The memory testing units are sequentially labeled as testing units 0, 1, 2, …, N-1;

[0138] d) The cores are sequentially labeled as cores 0, 1, 2, …, K-1;

[0139] e) The cores 0, 1, 2, …, K-1 are used to test the memory testing units 0, 1, 2, …, N-1, respectively, and a testing time matrix table of each core for each memory testing unit is obtained, as shown in Table 1.

[0140] Table 1 Testing time matrix table (unit: ms)

[0141]

[0142]

[0143] According to the testing time in Table 1, the best testing time memory binding core list can be obtained.

[0144] In the case of ensuring that each kernel runs the test time is substantially the same (i.e. the difference between the test time of any two memory test unit groups is within a preset time range), the memory test unit group and the kernel binding list is obtained according to the test time matrix table, as shown in Table 2.

[0145] Table 2 Memory test unit group and kernel binding list

[0146] Test Unit ID 0 1 2 3 … N-4 N-3 N-2 N-1 Core ID 0 1 K-2 1 … 0 K-1 2 K-3

[0147] According to the preset kernel thread correspondence, a thread is bound to each kernel, as shown in Table 3.

[0148] Table 3 Kernel thread binding relationship table

[0149] Thread ID 0 1 2 3 … K-4 K-3 K-2 K-1 Core ID 0 1 2 3 … K-4 K-3 K-2 K-1

[0150] The memory test unit and the thread are bound, and the memory is bound to the kernel, as shown in Table 4.

[0151] Table 4 Memory kernel binding list

[0152] Test Unit ID 0 1 2 3 … N-4 N-3 N-2 N-1 Thread ID 0 1 K-2 1 … 0 K-1 2 K-3 Core ID 0 1 K-2 1 … 0 K-1 2 K-3

[0153] After the memory, the thread, and the kernel are bound, the kernel is started, and the test can be started.

[0154] Based on the same inventive concept, the disclosure embodiments also provide a memory test device, as described in the following embodiments. Since the principles of solving problems of the device embodiments are similar to those of the above-mentioned method embodiments, the implementation of the device embodiments can be referred to the implementation of the above-mentioned method embodiments, and the repeated parts will not be described.

[0155] Figure 11 A structure schematic diagram of a memory test device provided by the embodiments of the disclosure is shown. As shown in Figure 11 In one embodiment, the memory test device provided by the embodiments of the disclosure includes an acquisition module 1101, a time consumption module 1102, and a matching module 1103.

[0156] The acquisition module 1101 is configured to acquire a plurality of non-intersecting memory test units.

[0157] The time consumption module 1102 is configured to test each memory test unit by using a plurality of kernels to obtain the test time of each memory test unit by each kernel.

[0158] The matching module 1103 is configured to match the memory test units to the cores according to the test time of each core on each memory test unit, so as to test the memory based on the matching relationship between the cores and the memory test unit groups, wherein the difference between the test time of the memory test unit groups corresponding to any two cores is within a preset time range, and any two memory test unit groups have no intersection.

[0159] In an embodiment, the device further comprises a binding module not shown in the drawings, and the binding module is configured to determine a target thread corresponding to a core according to a preset core thread binding relationship, bind the target thread to the core, and bind the memory test unit group corresponding to the target thread to the core until the core and the memory test unit group are bound, and then start the test.

[0160] In an embodiment, the binding module is specifically configured to obtain the test parameters of the memory test unit group corresponding to the core, and input the test parameters to the target thread, so as to bind the memory test unit group to the target thread.

[0161] In an embodiment, the device further comprises a construction module not shown in the drawings, and the construction module is configured to construct the core thread binding relationship between the cores and the threads according to a preset binding rule.

[0162] In an embodiment, the binding module binds the target thread to the core based on a unified extensible firmware interface.

[0163] In an embodiment, the obtaining module 1101 is specifically configured to determine the number of memory test units according to the number of memory particles and the number of cores of the CPU, divide the memory into a plurality of non-intersecting memory test units according to the number of memory test units, and the capacity of each memory test unit is the same.

[0164] In an embodiment, the time-consuming module 1102 is specifically configured to store the test time of each core on each memory test unit in a test time matrix table.

[0165] In an embodiment, the matching module 1103 is configured to divide the plurality of memory test units into a plurality of memory test unit groups based on the number of cores, calculate the test time of the plurality of memory test unit groups according to the test time of each core on each memory test unit, and match the plurality of memory test unit groups to the plurality of cores if the difference between the test time of any two memory test units is within a preset time range, wherein the memory test units in one memory test unit group belong to the same memory particle, and one memory test unit group corresponds to one core.

[0166] In one embodiment, the matching module 1103 is further configured to adjust part of the memory test units in the two memory test unit groups until the difference between the test time of the two memory test unit groups is within the preset time range, if the difference between the test time of the two memory test unit groups is not within the preset time range.

[0167] In another embodiment, the matching module 1103 is configured to divide the plurality of memory test units into a plurality of memory test unit groups based on the number of cores; calculate the test time average of the memory test unit groups and the test time of the plurality of memory test unit groups according to the test time of each memory test unit by each core; match the plurality of memory test unit groups with the plurality of cores if the difference between the test time of each memory test unit group and the test time average of the memory test unit groups is within the preset time range, wherein the memory test units in one memory test unit group belong to the same memory grain, and one memory test unit group corresponds to one core.

[0168] In one embodiment, the matching module 1103 is further configured to sort the plurality of memory test unit groups in a preset order, determine a first memory test unit group corresponding to the maximum test time and a second memory test unit group corresponding to the minimum test time, if the difference between the test time of one memory test unit group and the test time average of the memory test unit groups is not within the preset time range; and exchange at least one memory test unit in the first memory test unit group and the second memory test unit group until the difference between the test time of the exchanged memory test unit group and the test time average of the memory test unit is within the preset time range.

[0169] It should be noted that the test time of the memory test unit group is the sum of the test time of the memory test units in the memory test unit group, or the test time of the memory test unit group is the average of the test time of the memory test units in the memory test unit group.

[0170] Those skilled in the art can understand that each aspect of the present application can be implemented as a system, a method or a program product. Therefore, each aspect of the present application can be embodied as a complete hardware embodiment, a complete software embodiment (including firmware, microcode, etc.), or an embodiment combining hardware and software aspects, which can be collectively referred to as "circuitry", "module" or "system" herein.

[0171] The memory testing device provided by the embodiments of the present disclosure comprises the following steps: obtaining a plurality of memory testing units without intersection; testing each memory testing unit by using a plurality of cores to obtain the testing time of each memory testing unit by each core; and matching a memory testing unit group for each core according to the testing time of each memory testing unit by each core, so that the testing time difference of the memory testing unit groups corresponding to any two cores is within a preset time range, the running time of the plurality of cores can be made close by binding the memory testing unit group for each core, the memory testing units in each memory testing unit group are without intersection, so that the plurality of memory testing units are prevented from being tested by one core for multiple times, the testing time is shortened, the physical addresses of the memory testing unit groups are ensured to be independent of each other and not to affect each other, the binding of the memory to the core is realized, the testing device does not need an operating system and thread switching, and the memory testing efficiency is greatly improved.

[0172] The testing device 1200 according to this embodiment of the present disclosure will be described below with reference to Figure 12 Figure 12 The testing device 1200 shown is merely an example and should not impose any limitation on the functions and use range of the embodiments of the present disclosure.

[0173] As shown in Figure 12 , the testing device 1200 is in the form of a general computing device. The components of the testing device 1200 can include but are not limited to the above-mentioned at least one processing unit 1210, the above-mentioned at least one storage unit 1220, and a bus 1230 connecting different system components, including the storage unit 1220 and the processing unit 1210.

[0174] The storage unit stores program codes, which can be executed by the processing unit 1210, so that the processing unit 1210 performs the steps described in the above “Exemplary Method” section according to various exemplary embodiments of the present disclosure. For example, the processing unit 1210 can execute the following steps: obtaining a plurality of memory testing units without intersection; testing each memory testing unit by using a plurality of cores to obtain the testing time of each memory testing unit by each core; and matching a memory testing unit group for each core according to the testing time of each memory testing unit by each core, so that the testing time difference of the memory testing unit groups corresponding to any two cores is within a preset time range, and any two memory testing unit groups are without intersection. Figure 7

[0175] ​​The storage unit 1220 can include a readable medium in the form of volatile storage such as random access memory (RAM) 12201 and / or cache memory 12202, and also can include a non-volatile storage such as read only memory (ROM) 12203.

[0176] The storage unit 1220 also can include a program / utility 12204 having a set (at least one) of program modules 12205, including an operating system, one or more application programs, other program modules, and program data, each of which can give the system its functionality, or some combination thereof. The program modules 12205 can include a network environment implementation, either alone or in some combination.

[0177] The bus 1230 can represent one or more of several types of bus structures, including a storage bus or bus for storage controller, a peripheral bus, a graphics acceleration port, a processor or local bus using any of a variety of bus architectures.

[0178] The testing device 1200 also can communicate with one or more external devices 1240 such as a keyboard, a pointing device, a Bluetooth device, etc.; and can communicate with one or more devices that enable a user to interact with the system 1200, and / or with any devices (e.g., a router, a modem, etc.) that enable the testing device 1200 to communicate with one or more other computing devices. Such communication can occur via an input / output (I / O) interface 1250. Still yet, the system can communicate with one or more networks such as a local area network (LAN), a general wide area network (WAN), and / or a public network (e.g., the Internet) via a network adapter 1260. As Figure 12 illustrated, the network adapter 1260 can communicate with the other components of the testing device 1200 via the bus 1230. It should be understood that, although not shown explicitly, other hardware and / or software components could be used in conjunction with the testing device 1200. These include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc.

[0179] Those skilled in the art will readily recognize that the example embodiments described herein can be implemented by software and / or firmware in combination with the requisite hardware. Thus, the technical solutions according to the embodiments of the present disclosure can be embodied in a software product including a number of instructions stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, or the like) or a network, and the software product can be executed by one or more computing devices (which can be a personal computer, a server, a terminal device, or a network device, etc.) to implement the methods according to the embodiments of the present disclosure.

[0180] In the exemplary embodiments of the present disclosure, a computer readable storage medium is also provided, which can be a readable signal medium or a readable storage medium. Figure 13 A schematic diagram of a computer readable storage medium provided in an embodiment of the present disclosure is shown in FIG. 13. Figure 13 As shown in FIG. 13, the computer readable storage medium 1300 stores a program product capable of implementing the method of the present disclosure. In some possible implementations, various aspects of the present disclosure can also be implemented in the form of a program product, which includes program code for causing a user equipment to perform the steps described in the "Exemplary Methods" section above when the program product is run on the user equipment.

[0181] The program product for implementing the method according to the embodiments of the present disclosure can be in the form of a portable compact disc read-only memory (CD-ROM) and includes program code, and can be run on a user equipment, such as a personal computer. However, the program product of the present disclosure is not limited thereto, and in the present document, the readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus or device.

[0182] The program product can be in any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, or any suitable combination thereof. More specific examples (a non-exhaustive list) of the readable storage medium include an electrical connection having one or more wires, a portable disc, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0183] The computer readable signal medium can include a data signal propagated in baseband or propagated as a carrier wave in a propagated data signal, in which the readable program code is embodied. Such propagated data signal can take various forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination thereof. The readable signal medium can also be any readable medium that is not a readable storage medium and that can transmit, propagate or transport for use by or in connection with an instruction execution system, apparatus or device program code.

[0184] The program code contained in the readable medium can be transmitted by any suitable medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination thereof.

[0185] The program code may, through the use of program components, be implemented in any of one or more programming languages including an object oriented programming language such as Java, C++, or the like, and conventional procedural programming languages. The program code may execute entirely on the user's computing device, partly on the user's computing device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device or entirely on the remote computing device or server. In the latter scenario, the remote computing device can be connected to the user's computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computing device, such as through the Internet using an Internet Service Provider.

[0186] It should be noted that, although several modules or units of the device for action execution are mentioned in the foregoing detailed description, such a division is not mandatory. Indeed, according to embodiments of the disclosure, features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, features and functions of one module or unit described above can be further divided into a plurality of modules or units.

[0187] Furthermore, although the various steps of the methods of the disclosure are described in a particular order in the figures, this is not required or implied as to the order of execution of the steps, nor is it required that all of the steps be executed to achieve the desired result. Additionally or alternatively, certain steps can be omitted, multiple steps can be combined into one step, one step can be broken into multiple steps, etc.

[0188] From the above description of embodiments of the disclosure, those skilled in the art will readily perceive that the example embodiments described herein can be implemented by software and / or by hardware and / or by a combination of software and hardware. Accordingly, the technical solutions according to the embodiments of the disclosure can be embodied in the form of a software product. The software product can be stored in a non-volatile storage medium, such as a CD-ROM, a USB flash drive, a mobile hard disk, or the like, or on a network, and includes a number of instructions for causing a computing device (such as a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the methods according to the embodiments of the disclosure.

[0189] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A memory testing method, characterized by, The method comprises the following steps: acquiring a plurality of non-intersecting memory test units; testing each memory test unit by using a plurality of cores to obtain a test time of each core for each memory test unit; matching a memory test unit group for each core according to the test time of each core for each memory test unit, so as to test the memory based on the matching relationship between the core and the memory test unit group, wherein the difference between the test times of the memory test unit groups corresponding to any two cores is within a preset time range, and any two memory test unit groups are non-intersecting.

2. The method of claim 1, wherein, The testing of the memory based on the matching relationship between the core and the memory test unit group comprises the following steps: determining a target thread corresponding to one core according to a preset core-thread binding relationship; binding the target thread with the one core and binding the target thread with the memory test unit group corresponding to the one core until the binding of the core with the memory test unit group is completed, and then starting the test.

3. The method of claim 2, wherein, The binding of the target thread with the memory test unit group corresponding to the one core comprises the following steps: acquiring test parameters of the memory test unit group corresponding to the one core; inputting the test parameters into the target thread to bind the memory test unit group with the target thread.

4. The method of claim 2, wherein, Before the step of determining the target thread corresponding to the one core according to the preset core-thread binding relationship, the method further comprises the following step: constructing a core-thread binding relationship between the core and the thread according to a preset binding rule.

5. The method of claim 2, wherein, The binding of the target thread with the one core comprises the following step: binding the target thread with the one core based on a unified extensible firmware interface.

6. The method of claim 1, wherein, The acquisition of the plurality of non-intersecting memory test units comprises the following steps: determining the number of memory test units according to the number of memory particles and the number of cores of a CPU; dividing the memory into a plurality of non-intersecting memory test units according to the number of memory test units, and the capacity of each memory test unit is the same.

7. The method of claim 1, wherein, The testing of each memory test unit by using a plurality of cores to obtain a test time of each core for each memory test unit comprises the following step: storing the test time of each core for each memory test unit in a test time matrix table.

8. The method of claim 1, wherein, The matching of a memory test unit group for each core according to the test time of each core for each memory test unit comprises the following steps: dividing a plurality of memory test units into a plurality of memory test unit groups based on the number of cores; calculating the test time of the plurality of memory test unit groups according to the test time of each core for each memory test unit; if the difference between the test times of any two memory test units is within a preset time range, then matching the plurality of memory test unit groups with the plurality of cores, wherein the memory test units in one memory test unit group belong to the same memory particle, and one memory test unit group corresponds to one core.

9. The method of claim 8, wherein, The method further comprises the following steps: If the difference between the test times of the two memory test unit groups is not within the preset time range, adjust the partial memory test units in the two memory test unit groups until the difference between the test times of the two memory test unit groups is within the preset time range.

10. The method of claim 1, wherein, The matching memory test unit groups for the respective cores according to the test times of the respective memory test units by the respective cores comprises: The plurality of memory test units are divided into a plurality of memory test unit groups based on the number of cores; The test time average of the memory test unit groups and the test times of the plurality of memory test unit groups are calculated according to the test times of the respective memory test units by the respective cores; If the difference between the test time of each memory test unit group and the test time average of the memory test unit groups is within the preset time range, the plurality of memory test unit groups are matched with the plurality of cores, wherein the memory test units in one memory test unit group belong to the same memory particle, and one memory test unit group corresponds to one core.

11. The method of claim 10, wherein, The method further comprises: If the difference between the test time of one memory test unit group and the test time average of the memory test unit groups is not within the preset time range, a plurality of memory test unit groups are sorted in a preset order to determine a first memory test unit group corresponding to a maximum test time and a second memory test unit group corresponding to a minimum test time; At least one memory test unit in the first memory test unit group and the second memory test unit group is exchanged until the difference between the test time of the exchanged memory test unit group and the test time average of the memory test unit is within the preset time range.

12. The method of claim 1, wherein, The test time of the memory test unit group is the sum of the test times of the memory test units in the memory test unit group, or the test time of the memory test unit group is the average of the test times of the memory test units in the memory test unit group.

13. A memory testing apparatus, characterized by comprising: It comprises: An acquisition module is configured to acquire a plurality of non-intersecting memory test units; A time-consuming module is configured to test each memory test unit by using a plurality of cores to obtain the test time of each memory test unit by the respective cores; A matching module is configured to match a memory test unit group for each core according to the test time of each memory test unit by the respective cores, and test the memory based on the matching relationship between the cores and the memory test unit groups, wherein the difference between the test times of the memory test unit groups corresponding to any two cores is within a preset time range, and any two memory test unit groups are non-intersecting.

14. A test apparatus, characterized by The computer program is executed by the processor to implement the memory test method of any one of claims 1-12.

15. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the memory test method of any one of claims 1-12.

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