Page table generation method, apparatus, and electronic equipment for processor paging verification

Abstract

This application discloses a page table generation method, apparatus, and electronic device for processor paging verification, relating to the field of processor technology, and is invented to simplify the page table generation process and reduce the cost of verification design. The method includes: obtaining the base address of the first-level page table of the current user process; determining the page frame number in each page table entry of the last-level page table based on the base address and each virtual address in the virtual address range of the current user process; the page table having a mapping relationship between the virtual address range and the physical address verification space; and updating the page frame number in the first page table entry of the last-level page table to the second page table entry of the last-level page table to generate a new page table. This application is applicable to processor paging verification.

Description

Technical Field

[0001] This application relates to the field of processor technology, and in particular to a page table generation method, apparatus, electronic device, and readable storage medium for processor paging verification. Background Technology

[0002] In processor protected mode, a paging mechanism is activated to prevent processes from corrupting the system's physical memory, translating virtual addresses into physical addresses. Processes cannot directly access physical addresses; instead, they access virtual addresses. The mapping between virtual and physical addresses is recorded in the page table. The address translation process involves checks of access permissions and access types. If an error is detected, a corresponding page fault is triggered, achieving memory protection. Therefore, verifying the paging mechanism is crucial to the processor's functional stability.

[0003] To verify processor paging, the page table needs to be modified (a new page table needs to be generated) to change the virtual address to physical address mapping. This can cover as many verification attributes as possible. In the existing technology, modifying the page table requires modifying the operating system kernel code, which is quite complex, making the process of generating the page table quite complicated. Summary of the Invention

[0004] In view of this, embodiments of this application provide a page table generation method, apparatus, electronic device, and readable storage medium for processor paging verification, which simplifies the page table generation process and reduces the cost of verification design.

[0005] In a first aspect, embodiments of this application provide a page table generation method for processor paging verification, comprising: obtaining the base address of the first-level page table of the current user process; determining the page frame number in each page table entry of the last-level page table based on the base address and each virtual address in the virtual address range of the current user process; the page table having a mapping relationship between the virtual address range and the physical address verification space; and updating the page frame number in the first page table entry of the last-level page table to the second page table entry of the last-level page table to generate a new page table.

[0006] According to a specific implementation of an embodiment of this application, before obtaining the base address of the first-level page table of the current user process, the method further includes: the current user process loading a first driver into the operating system kernel; wherein, obtaining the base address of the first-level page table of the current user process, and determining the page frame number in each page table entry of the last-level page table based on the base address and each virtual address in the virtual address range of the current user process, includes: the first driver obtaining the base address of the first-level page table of the current user process, and determining the page frame number in each page table entry of the last-level page table based on the base address and each virtual address in the virtual address range of the current user process.

[0007] According to a specific implementation of this application, after the first driver determines the page frame number in each page table entry of the last-level page table, the method further includes: the first driver returning the page frame number in each page table entry of the last-level page table to the current user process; wherein, updating the page frame number in the first page table entry of the last-level page table to the second page table entry of the last-level page table includes: the current user process updating the page frame number in the first page table entry of the last-level page table to the second page table entry of the last-level page table.

[0008] According to a specific implementation of an embodiment of this application, the current user process updates the page frame number in the first page entry of the last-level page table to the second page entry of the last-level page table, which includes: the current user process randomly determines the first page entry of the last-level page table and updates the page frame number in the randomly determined first page entry of the last-level page table to the second page entry of the last-level page table.

[0009] According to a specific implementation of an embodiment of this application, after the current user process updates the page frame number in the first page entry of the last-level page table to the second page entry of the last-level page table, the method further includes: the current user process modifying the attributes of the first page entry and / or the attributes of the first page entry in the last-level page table.

[0010] According to a specific implementation of an embodiment of this application, before obtaining the base address of the first-level page table of the current user process, the method further includes: the current user process requesting page frame number storage space from the operating system; wherein, after determining the page frame number in each page table entry of the last-level page table, the method further includes: storing the page frame number in each page table entry of the last-level page table in the page frame number storage space.

[0011] Secondly, embodiments of this application provide a page table generation apparatus for processor paging verification, comprising: an acquisition module, configured to acquire the base address of the first-level page table of the current user process, and determine the page frame number in each page table entry of the last-level page table based on the base address and each virtual address in the virtual address range of the current user process; the page table has a mapping relationship between the virtual address range and the physical address verification space; and an update module, configured to update the page frame number in the first page table entry of the last-level page table to the second page table entry of the last-level page table to generate a new page table.

[0012] According to a specific implementation of an embodiment of this application, the apparatus further includes: a loading module, configured to load a first driver into the operating system kernel before the acquisition module acquires the base address of the first-level page table of the current user process; wherein, the acquisition module includes: a determining submodule, configured to, based on the base address of the first-level page table of the current user process acquired by the first driver, determine the page frame number in each page table entry of the last-level page table of the page table based on the base address and each virtual address in the virtual address range of the current user process.

[0013] According to a specific implementation of an embodiment of this application, the apparatus further includes: a return module, configured to, after the determining submodule determines the page frame number in each page table entry of the last-level page table through the first driver, return the page frame number in each page table entry of the last-level page table to the current user process; wherein, the update module includes: an update submodule, configured to, the current user process update the page frame number in the first page table entry of the last-level page table to the second page table entry of the last-level page table.

[0014] According to a specific implementation of an embodiment of this application, the update submodule is specifically used for: the current user process randomly determines the first page entry in the last-level page table, and updates the page frame number in the randomly determined first page entry in the last-level page table to the second page entry in the last-level page table.

[0015] According to a specific implementation of an embodiment of this application, the method further includes: a modification module, configured to modify the first page entry and / or the attributes of the first page entry in the last-level page table after the current user process of the update submodule updates the page frame number in the first page entry of the last-level page table to the second page entry of the last-level page table.

[0016] According to a specific implementation of an embodiment of this application, the apparatus further includes: an application module, configured to allow the current user process to apply for page frame number storage space from the operating system before the acquisition module obtains the base address of the first-level page table of the current user process; wherein, the apparatus further includes: a storage module, configured to store the page frame numbers in each page table entry of the last-level page table in the page frame number storage space after the acquisition module determines the page frame numbers in each page table entry of the last-level page table.

[0017] Thirdly, embodiments of this application provide an electronic device, which includes: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed inside the space enclosed by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the page table generation method for processor paging verification described in any of the foregoing implementations.

[0018] Fourthly, embodiments of this application provide a computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement the page table generation method for processor paging verification as described in any of the foregoing implementations.

[0019] This embodiment of the page table generation method, apparatus, electronic device, and readable storage medium for processor paging verification obtains the base address of the first-level page table of the current user process. Based on the base address and each virtual address in the virtual address range of the current user process, it determines the page frame number in each page table entry of the last-level page table. The page table has a mapping relationship between the virtual address range and the physical address verification space. The page frame number in the first page table entry of the last-level page table is updated to the second page table entry of the last-level page table to generate a new page table. In the process of generating a new page table, there is no need to modify the operating system kernel code, which simplifies the page table generation process and reduces the cost of verification design. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1A schematic flowchart illustrating a page table generation method for processor paging verification provided in an embodiment of this application;

[0022] Figure 2 A schematic diagram of the processor paging verification process provided in a specific embodiment of this application;

[0023] Figure 3 This is a comparison diagram of the last-level page table entries before and after modification in a specific embodiment of this application;

[0024] Figure 4 A schematic diagram of a page table generation apparatus for processor paging verification provided in an embodiment of this application;

[0025] Figure 5 A schematic diagram of a page table generation apparatus for processor paging verification provided in a specific embodiment of this application;

[0026] Figure 6 A flowchart illustrating processor paging verification is provided for a specific embodiment of this application;

[0027] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0028] The embodiments of this application will now be described in detail with reference to the accompanying drawings. It should be understood that the described embodiments are merely some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0029] To enable those skilled in the art to better understand the technical concept, implementation scheme and beneficial effects of the embodiments of this application, detailed descriptions are provided below through specific embodiments.

[0030] One embodiment of this application provides a page table generation method for processor paging verification, which simplifies the page table generation process and reduces the cost of verification design.

[0031] Figure 1 This is a flowchart illustrating a page table generation method for processor paging verification provided in an embodiment of this application, as shown below. Figure 1 As shown, the page table generation method for processor paging verification in this embodiment may include:

[0032] S101. Obtain the base address of the first-level page table of the current user process. Based on the base address and each virtual address in the virtual address range of the current user process, determine the page frame number in each page table entry of the last-level page table.

[0033] The current user process can be the process performing processor paging verification.

[0034] During the initialization of the verification program, a verification space is requested from the physical address of the operating system. This space is used for paging verification. Upon receiving the request, the operating system allocates the corresponding memory and creates a page table for the current user process. The page table contains the mapping relationship between the virtual address range and the physical address verification space, thus realizing the mapping from virtual address to physical address.

[0035] Page tables can be two-level or multi-level. A page table must include at least a first-level page table and a last-level page table. Each level of page table includes page table entries. The page table entries of the previous level page table store the base address of the next level page table, and the page table entries of the last level page table store the page frame number.

[0036] After obtaining the base address of the first-level page table of the current user process, the page frame number in each page table entry of the last-level page table can be determined based on the base address of the first-level page table and the virtual addresses in the virtual address range of the current user process.

[0037] S102. Update the page frame number in the first page table entry of the last-level page table to the second page table entry of the last-level page table to generate a new page table.

[0038] The first page table entry is a page table within the last-level page table, and the second page table entry is a page table entry within the last-level page table that is different from the first page table entry.

[0039] The first page table entry stores the page frame number, and the second page table entry also stores the page frame number. In this embodiment, the page frame number in the second page table entry is updated using the page frame number in the first page table entry, thereby generating a new page table.

[0040] In this embodiment, by obtaining the base address of the first-level page table of the current user process, and based on the base address and each virtual address in the virtual address range of the current user process, the page frame number in each page table entry of the last-level page table is determined. The page table has a mapping relationship between the virtual address range and the physical address verification space. The page frame number in the first page table entry of the last-level page table is updated to the second page table entry of the last-level page table to generate a new page table. In the process of generating a new page table, there is no need to modify the operating system kernel code, which simplifies the page table generation process and reduces the cost of verification design.

[0041] Understandably, in order to generate a page table, one can modify a single entry from the page table in the last-level page table, or multiple entries can be modified.

[0042] Another embodiment of this application is basically the same as the above embodiments, except that, in this embodiment, before obtaining the base address of the first-level page table of the current user process, this embodiment may further include:

[0043] S103. The current user process loads the first driver into the operating system kernel.

[0044] The first driver, once loaded into the operating system kernel, can obtain the base address of the first-level page table in the page table allocated by the operating system for the current process, as well as the page frame number in each page table entry of the last-level page table.

[0045] The process of obtaining the base address of the first-level page table of the current user process, and determining the page frame number in each page table entry of the last-level page table based on the base address and the virtual addresses within the virtual address range of the current user process (S101), may include:

[0046] S101 a. The first driver obtains the base address of the first-level page table of the current user process, and determines the page frame number in each page table entry of the last-level page table based on the base address and each virtual address in the virtual address range of the current user process.

[0047] In the operating system kernel, the first driver obtains the base address of the first-level page table of the current user process. Then, based on the base address and the virtual addresses in the virtual address range of the current user process, it queries the page tables at each level to determine the page frame number in each page table entry of the last-level page table.

[0048] In this embodiment, the paging mechanism of the operating system can be utilized, eliminating the need to rebuild the paging mechanism for page verification or modify the operating system kernel code, thereby reducing the design cost of verification.

[0049] In some examples, after the first driver determines the page frame number in each page table entry of the last-level page table, the method may further include:

[0050] S104. The first driver returns the page frame number from each page table entry in the last-level page table to the current user process.

[0051] The first driver determines the page frame number in each page table entry of the last-level page table in the operating system kernel. In order to facilitate the current user process to modify the page frame number in each page table entry of the last-level page table, the first driver can return the page frame number in each page table entry of the last-level page table from the operating system kernel to the current user process.

[0052] In this embodiment, updating the page frame number in the first page entry of the last-level page table to the second page entry of the last-level page table (S102) may include:

[0053] S102a. The current user process updates the page frame number in the first page table entry of the last-level page table to the second page table entry of the last-level page table.

[0054] In this embodiment, the user-mode process can update the page frame number in the first page table entry of the last-level page table to the second page table entry of the last-level page table. That is, the user-mode process uses the page frame number in the first page table entry to update the page frame number in the second page table entry. In this way, the user can conveniently and flexibly modify the page frame number in the last-level page table according to their own needs, thereby improving the verification efficiency and avoiding the problem of low verification efficiency caused by the inability of the user to modify the page table in the prior art.

[0055] In some other examples, the current user process updates the page frame number in the first page table entry of the last-level page table to the second page table entry of the last-level page table (S102a), which may include:

[0056] The current user process randomly determines the first page entry in the last-level page table, and updates the page frame number in the first page entry of the randomly determined last-level page table to the second page entry in the last-level page table.

[0057] In this embodiment, the first page entry in the last-level page table is randomly determined, and the page frame number in the randomly determined first page entry in the last-level page table is updated to the second page entry in the last-level page table. In this way, a verification environment with random page mapping can be generated, providing a verification environment with higher complexity and randomness for verification test cases, making the functional verification of the processor more accurate. Furthermore, in the environment of random page mapping, the page mapping relationship can be expanded, avoiding process access to the same page and reducing verification errors caused by latent factors. The random mapping verification environment of this embodiment can also be applied in security application scenarios.

[0058] In some examples, after the current user process updates the page frame number in the first page table entry of the last-level page table to the second page table entry of the last-level page table (S102a), the method may further include:

[0059] S105. The current user process modifies the first page entry and / or the attributes of the first page entry in the last-level page table.

[0060] Page table entries include different bits, including bits that identify the page frame number and bits that identify the page table entry attributes. Specifically, these may include a valid bit, an access bit, a modified bit, and a protection bit. The valid bit indicates whether the virtual page corresponding to the page table entry has been read into memory; the access bit indicates whether the page has been accessed; the modified bit indicates whether the page has been modified in memory; and the protection bit indicates the read and write permissions for the page. The attributes of page table entries can be modified by modifying the bits that identify the different page table entry attributes.

[0061] In practical applications, users can modify the attributes of the last-level page table items, i.e., the page attributes within the verification space, according to their verification requirements. This allows for the coverage of more verification attributes during verification.

[0062] In another embodiment of this application, which is basically the same as the above embodiment, the difference is that, in this embodiment, before obtaining the base address of the first-level page table of the current user process, the method may further include:

[0063] S106. The current user process requests page frame number storage space from the operating system.

[0064] The allocated page frame number storage space is used to store the page frame numbers of each page table entry in the last-level page table.

[0065] In this embodiment, after determining the page frame number in each page table entry of the last-level page table, the method may further include:

[0066] Store the page frame numbers from each page table entry in the last-level page table in the page frame number storage space.

[0067] In this embodiment, the page frame number in each page table entry of the last-level page table is stored in the page frame number storage space. In this way, after the verification is completed, the original address mapping relationship of the operating system is restored and the verification process is exited, so as not to destroy the original address mapping relationship of the system.

[0068] If it is necessary to modify the attributes of each page table entry in the last-level page table, storage space for the stored attributes can be requested for restoring the attributes after the verification experiment is completed.

[0069] The following detailed description of the solution in this application is based on a specific embodiment.

[0070] See Figure 2 The processor paging verification process in this embodiment includes the following steps:

[0071] S11, System initialization.

[0072] Request storage space for the verification pages and PTEs. The verification page space is used for paginated verification, and this space includes multiple pages; request storage space for PTEs to store the PTEs for each page of the verification page.

[0073] S12, Load driver module

[0074] Load the driver module into the operating system kernel. The driver module is used to obtain process CR3 and PTE.

[0075] S13, Obtain process CR3.

[0076] Get the CR3 allocated by the operating system to the current process. The value in CR3 represents the base address of the page table.

[0077] S14. Obtain the PTE for each page through CR3 and the application verification page.

[0078] The driver module obtains the PTE address of each page through the page table PTE acquisition module based on the current process CR3 and the address of the requested verification space.

[0079] S15. Save the PTE to the PTE storage space.

[0080] Save the PTE address of each page of the application page to the PTE's storage space.

[0081] S16. Change the address mapping relationship.

[0082] Modify the system's original address mapping relationship to obtain a randomly mapped verification environment. Within the verification space, modify the system's original address mapping relationship by changing the PTE of each page to obtain a randomly mapped verification environment (see 3).

[0083] S17. Restore the original page mapping relationship of the operating system and exit the process.

[0084] After verification is complete, restore the original page mapping relationship of the operating system and exit the process.

[0085] An embodiment of this application provides a page table generation apparatus for processor paging verification, which includes: simplifying the page table generation process and reducing the cost of verification design.

[0086] Figure 4 This is a schematic diagram of a page table generation apparatus for processor paging verification provided in an embodiment of this application, as shown below. Figure 4As shown, the page table generation device for processor paging verification in this embodiment may include: an acquisition module 11, configured to acquire the base address of the first-level page table of the current user process, and determine the page frame number in each page table entry of the last-level page table based on the base address and each virtual address in the virtual address range of the current user process; the page table has a mapping relationship between the virtual address range and the physical address verification space; and an update module 12, configured to update the page frame number in the first page table entry of the last-level page table to the second page table entry of the last-level page table to generate a new page table.

[0087] The apparatus of this embodiment can be used to perform Figure 1 The technical solutions of the method embodiments shown are similar in principle and in effect, and will not be described again here.

[0088] The apparatus of this embodiment obtains the base address of the first-level page table of the current user process, and determines the page frame number in each page table entry of the last-level page table based on the base address and each virtual address in the virtual address range of the current user process. The page table has a mapping relationship between the virtual address range and the physical address verification space. The page frame number in the first page table entry of the last-level page table is updated to the second page table entry of the last-level page table to generate a new page table. In the process of generating a new page table, there is no need to modify the operating system kernel code, which simplifies the page table generation process and reduces the cost of verification design.

[0089] As an optional implementation, the apparatus further includes: a loading module, configured to load a first driver into the operating system kernel before the acquisition module acquires the base address of the first-level page table of the current user process; wherein, the acquisition module includes: a determining submodule, configured to, based on the base address of the first-level page table of the current user process acquired by the first driver, determine the page frame number in each page table entry of the last-level page table of the page table based on the base address and each virtual address in the virtual address range of the current user process.

[0090] As an optional implementation, the apparatus further includes: a return module, configured to, after the determining submodule determines the page frame number in each page table entry of the last-level page table through the first driver, return the page frame number in each page table entry of the last-level page table to the current user process; wherein, the update module includes: an update submodule, configured to, for the current user process to update the page frame number in the first page table entry of the last-level page table to the second page table entry of the last-level page table.

[0091] As an optional implementation, the update submodule is specifically used for: the current user process randomly determining the first page entry in the last-level page table, and updating the page frame number in the randomly determined first page entry in the last-level page table to the second page entry in the last-level page table.

[0092] As an optional implementation, the method further includes: a modification module, configured to modify the first page entry and / or the attributes of the first page entry in the last-level page table after the current user process of the update submodule updates the page frame number in the first page entry of the last-level page table to the second page entry of the last-level page table.

[0093] As an optional implementation, the apparatus further includes: an application module, configured to allow the current user process to apply for page frame number storage space from the operating system before the acquisition module obtains the base address of the first-level page table of the current user process; wherein, the apparatus further includes: a storage module, configured to store the page frame numbers in each page table entry of the last-level page table in the page frame number storage space after the acquisition module determines the page frame numbers in each page table entry of the last-level page table.

[0094] The apparatus described in the above embodiments can be used to execute the technical solutions of the above method embodiments. The implementation principle and technical effects are similar, and will not be repeated here.

[0095] The solution of this application will be described in detail below with reference to specific embodiments.

[0096] See Figure 5 In specific embodiment one, the page table generation device for processor paging verification consists of three parts: a process CR3 acquisition module 21, a page table PTE acquisition module 22, and a random mapping module 23. The process base address acquisition module obtains the CR3 control register value of the current process; this value is the base address of the highest-level page table (first-level page table). Based on the CR3 control register value, the base addresses of each level of page table can be calculated.

[0097] The Page Table PTE Acquisition Module, also known as the Last-Level Page Table Entry Acquisition Module, is used to extract the PTEs (Physical Address Page Frames and Page Attributes) of pages in the verification space. It acquires the PTEs of all pages within the requested verification space. The Random Mapping Module then performs random mapping on all pages within the verification space based on the acquired PTEs, changing the original mapping relationship between virtual addresses and physical addresses to obtain a verification environment with randomly mapped pages.

[0098] See Figure 6 In specific embodiment two, the processor paging verification process includes:

[0099] S21, System initialization.

[0100] Allocate space for verification pages and storage of PTEs in the system. Assume the verification space is 8MB, with 2048 4KB pages; the PTE storage space is 16KB, and the space occupied by storing PTEs is 4 * 512 * 8 bytes.

[0101] S22, Load the driver module.

[0102] The driver module may include a process CR3 acquisition module and a PTE acquisition module. The driver module for acquiring process CR3 and the PTE acquisition module are loaded into the operating system kernel. User processes can obtain the CR3 of the current process and the PTE of each page through these two modules.

[0103] S23. The CR3 process obtains the base address of the first-level page table from the module.

[0104] S24, the PTE acquisition module traverses the page table level by level based on the CR3 of the current process and the verification page address.

[0105] S25. Obtain the PTE of each page of the verification page and return it to the user space.

[0106] After the user space process receives the PTE returned by the kernel space, it stores the PTE in the PTE storage space and keeps a backup for page mapping restoration after verification is completed.

[0107] S26. Modify the PTE to change the address mapping and obtain the random page mapping environment.

[0108] Each obtained page PTE is denoted as PTE[0], PTE[1], PTE[2]...PTE

[2047] . A PTE is randomly selected from these PTEs and assigned to another PTE, changing the original mapping relationship and obtaining a verification environment for random page mapping.

[0109] S26. Page mapping relationship restored, process exits.

[0110] After verification is complete, the system restores itself based on the saved original mapping relationship, and then exits the verification process without affecting the operating system.

[0111] After obtaining the PTE for each page, users can modify the content within the PTE, change page attributes and access permissions, and cover more verification attributes; the random mapping relationship can be modified multiple times according to verification requirements.

[0112] In this embodiment, the address mapping of each page can be modified, changing the mapping of all pages within the verification space. This increases the complexity and randomness of the verification environment. Furthermore, it achieves random page mapping within the verification space under the operating system environment, eliminating the need to rebuild the paging mechanism and reducing the design cost of verification. The original address mapping relationship of the operating system is saved and restored after verification without disrupting the system's address mapping relationship. In addition, users can maintain the page table state themselves within the verification space, modifying page attributes, access permissions, and mapping relationships.

[0113] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, as shown below. Figure 7 As shown, the device may include: a housing 61, a processor 62, a memory 63, a circuit board 64, and a power supply circuit 65. The circuit board 64 is disposed inside the space enclosed by the housing 61, and the processor 62 and the memory 63 are disposed on the circuit board 64. The power supply circuit 65 is used to supply power to the various circuits or devices of the above-mentioned electronic device. The memory 63 is used to store executable program code. The processor 62 runs the program corresponding to the executable program code by reading the executable program code stored in the memory 63, and is used to execute any of the page table generation methods for processor paging verification provided in the foregoing embodiments. Therefore, it can also achieve the corresponding beneficial technical effects, which have been described in detail above and will not be repeated here.

[0114] The aforementioned electronic devices exist in various forms, including but not limited to:

[0115] (1) Mobile communication devices: These devices are characterized by their mobile communication capabilities and primarily aim to provide voice and data communication. These terminals include: smartphones (e.g., iPhones), multimedia phones, feature phones, and low-end phones, etc.

[0116] (2) Ultra-mobile personal computer devices: These devices fall under the category of personal computers, possessing computing and processing capabilities, and generally also have mobile internet access features. These terminals include PDAs, MIDs, and UMPCs, such as the iPad.

[0117] (3) Portable entertainment devices: These devices can display and play multimedia content. This category includes: audio and video players (such as iPods), handheld game consoles, e-books, as well as smart toys and portable car navigation devices.

[0118] (4) Server: A device that provides computing services. The components of a server include a processor, hard disk, memory, system bus, etc. Servers are similar to general computer architectures, but because they need to provide highly reliable services, they have higher requirements in terms of processing power, stability, reliability, security, scalability, and manageability.

[0119] (5) Other electronic devices with data interaction functions.

[0120] Accordingly, embodiments of this application also provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement any of the page table generation methods for processor paging verification provided in the foregoing embodiments. Therefore, it can also achieve the corresponding technical effects, as has been described in detail above and will not be repeated here.

[0121] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0122] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0123] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0124] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this application, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0125] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0126] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for page table generation for processor paging verification, the method comprising: The method comprises the following steps: obtaining a base address of a first-level page table of a current user process, and determining a page frame number in each page table entry in a last-level page table of a page table based on the base address and each virtual address in a virtual address range of the current user process; the page table has a mapping relationship between the virtual address range and a physical address verification space; updating the page frame number in a first page table entry in the last-level page table into a second page table entry in the last-level page table to generate a new page table; wherein, before obtaining the base address of the first-level page table of the current user process, the method further comprises: the current user process loads a first driver into an operating system kernel; the obtaining of the base address of the first-level page table of the current user process and the determination of the page frame number in each page table entry in the last-level page table of the page table based on the base address and each virtual address in the virtual address range of the current user process comprise: the first driver obtains the base address of the first-level page table of the current user process, and determines the page frame number in each page table entry in the last-level page table of the page table based on the base address and each virtual address in the virtual address range of the current user process.

2. The method of claim 1, wherein, after the first driver determines the page frame number in each page table entry in the last-level page table of the page table, the method further comprises: the first driver returns the page frame number in each page table entry in the last-level page table to the current user process; wherein, the updating of the page frame number in the first page table entry in the last-level page table into the second page table entry in the last-level page table comprises: the current user process updates the page frame number in the first page table entry in the last-level page table into the second page table entry in the last-level page table.

3. The method of claim 2, wherein, the current user process updates the page frame number in the first page table entry in the last-level page table into the second page table entry in the last-level page table comprises: the current user process randomly determines the first page table entry in the last-level page table, and updates the page frame number in the randomly determined first page table entry in the last-level page table into the second page table entry in the last-level page table.

4. The method of claim 2, wherein, after the current user process updates the page frame number in the first page table entry in the last-level page table into the second page table entry in the last-level page table, the method further comprises: the current user process modifies the first page table entry in the last-level page table and / or the attribute of the first page table entry.

5. The method of claim 1, wherein, before obtaining the base address of the first-level page table of the current user process, the method further comprises: the current user process applies for a page frame number storage space from an operating system; wherein, after determining the page frame number in each page table entry in the last-level page table, the method further comprises: storing the page frame number in each page table entry in the last-level page table in the page frame number storage space.

6. A page table generation apparatus for processor paging verification, characterized by, The method comprises the following steps: an obtaining module is configured to obtain a base address of a first-level page table of a current user process, and determine a page frame number in each page table entry in a last-level page table of a page table based on the base address and each virtual address in a virtual address range of the current user process; the page table has a mapping relationship between the virtual address range and a physical address verification space; An updating module is configured to update a page frame number in a first page table entry in a last-level page table to a second page table entry in the last-level page table to generate a new page table. The apparatus further includes: A loading module is configured to load a first driver into an operating system kernel by a current user process before the obtaining module obtains a base address of a first-level page table of the current user process. The obtaining module includes: A determining submodule is configured to obtain the base address of the first-level page table of the current user process by the first driver, and determine the page frame number in each page table entry in a last-level page table of the page table based on the base address and each virtual address in a virtual address range of the current user process.

7. The apparatus of claim 6, wherein, The apparatus further includes: A returning module is configured to return the page frame number in each page table entry in the last-level page table to the current user process by the first driver after the determining submodule determines the page frame number in each page table entry in the last-level page table of the page table by the first driver. The updating module includes: An updating submodule is configured to update the page frame number in the first page table entry in the last-level page table to the second page table entry in the last-level page table by the current user process.

8. The apparatus of claim 7, wherein, The updating submodule is specifically configured to: The current user process randomly determines the first page table entry in the last-level page table, and updates the page frame number in the randomly determined first page table entry in the last-level page table to the second page table entry in the last-level page table.

9. The apparatus of claim 7, wherein, The apparatus further includes: A modifying module is configured to modify the first page table entry in the last-level page table and / or an attribute of the first page table entry by the current user process after the updating submodule updates the page frame number in the first page table entry in the last-level page table to the second page table entry in the last-level page table by the current user process.

10. The apparatus of claim 6, wherein, The apparatus further includes: An applying module is configured to apply for a page frame number storage space by the current user process to an operating system before the obtaining module obtains the base address of the first-level page table of the current user process. The apparatus further includes: A storage module is configured to store the page frame number in each page table entry in the last-level page table in the page frame number storage space after the obtaining module determines the page frame number in each page table entry in the last-level page table.

11. An electronic device, comprising: The electronic device includes a housing, a processor, a memory, a circuit board, and a power circuit, wherein the circuit board is arranged inside a space enclosed by the housing, and the processor and the memory are arranged on the circuit board; the power circuit is configured to supply power to each circuit or device of the electronic device; the memory is configured to store executable program codes; and the processor is configured to run a program corresponding to the executable program codes by reading the executable program codes stored in the memory, and execute the page table generation method for processor paging verification according to any one of the preceding claims 1-6.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the page table generation method for processor paging verification according to any one of the preceding claims 1-6.

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