CAM device structure unit, array, operation method and device based on NVM device

Abstract

The present disclosure provides a CAM device structure unit, array, operation method, and device based on an NVM device. The CAM device structure unit based on an NVM device includes a first NVM device unit and a second NVM device unit. The first NVM device unit stores a first conductance value mapped to a set storage logic value; the second NVM device unit stores a second conductance value mapped to a set storage logic value, is arranged adjacent to the first NVM device unit, and is connected to the same bit line; when a first input voltage mapped to a set input logic value is applied to the first NVM device unit, and a second input voltage mapped to a set input logic value is applied to the second NVM device unit, the bit line current of the bit line is read in response to a first read voltage applied to the first NVM device unit and a second read voltage applied to the second NVM device unit to determine the Euclidean distance. This achieves a CAM system design that is low in power consumption, high in density, and can meet the requirements of complex application scenarios.

Description

Technical Field

[0001] The present disclosure relates to the fields of semiconductor device technology and integrated circuit design technology, and in particular to a CAM device structure unit, array, operation method, and device based on an NVM device. Background Art

[0002] Content-addressable memory (CAM) devices can search and compare input content with stored data, calculating the distance between the input vector and the stored vector. Due to this property, CAM devices are widely used to accelerate various machine learning applications, such as memory-enhanced neural networks and high-dimensional computing. Traditional CAM devices are based on static random access memory (SRAM). A single CAM device unit consists of more than a dozen transistors, resulting in a large circuit area and standby power consumption. Furthermore, they implement a ternary content addressable memory (TCAM) device structure that stores three-state values ​​of '0', '1', and 'X', and can only calculate the relatively simple Hamming distance.

[0003] With the development of the Internet of Things (IoT) and big data, the amount of stored data that needs to be searched has exploded, posing significant challenges to power consumption and circuit area. Furthermore, using the Hamming distance in complex tasks can significantly reduce the accuracy of the entire system. In machine learning tasks, the Euclidean distance is widely used due to its greater power and accuracy. However, there is currently a lack of effective computational solutions for this Euclidean distance using CAM devices. Summary of the Invention

[0004] (1) Technical issues to be solved

[0005] In order to solve at least one of the above-mentioned technical problems existing in the prior art, the present disclosure provides a CAM device structure unit, array, operation method and equipment based on NVM (non-volatile memory), in order to at least partially solve the technical problems existing in the prior art of CAM devices, such as high power consumption, low density, and simple distance function that cannot adapt to complex task scenarios, and realize a multi-valued CAM device for Euclidean distance operation.

[0006] (2) Technical solution

[0007] One aspect of the present disclosure provides a CAM device structure unit based on an NVM device, comprising a first NVM device cell and a second NVM device cell. The first NVM device cell stores a first conductance value mapped to a set storage logic value; the second NVM device cell stores a second conductance value mapped to the set storage logic value, is disposed adjacent to the first NVM device cell, and is connected to the same bit line. When a first input voltage mapped to the set input logic value is applied to the first NVM device cell and a second input voltage mapped to the set input logic value is applied to the second NVM device cell, a bit line current of the bit line is sensed in response to a first read voltage applied to the first NVM device cell and a second read voltage applied to the second NVM device cell to determine a Euclidean distance.

[0008] According to an embodiment of the present disclosure, the drain of the first NVM device unit is connected to the bit line; and the drain of the second NVM device unit is connected to the bit line.

[0009] According to an embodiment of the present disclosure, the gate of the first NVM device unit is used to apply a first input voltage, and its source is used to apply a first read voltage; the gate of the second NVM device unit is used to apply a second input voltage, and its source is used to apply a second read voltage.

[0010] According to an embodiment of the present disclosure, the first conductance value is the product of the square of the set stored logic value and the set conductance step length; the second conductance value is the product of the square of the negated value of the set stored logic value and the set conductance step length; the first conductance value and the second conductance value are complementary.

[0011] According to an embodiment of the present disclosure, the set input logic value is close to the set minimum logic value, the first input voltage is the word line turn-on voltage corresponding to the set minimum logic value, and the second input voltage is zero; the set input logic value is close to the set maximum logic value, the second input voltage is the word line turn-on voltage corresponding to the set maximum logic value, and the first input voltage is zero; the set input logic value is close to the set middle large logic value, the first input voltage is zero, and the second input voltage is zero.

[0012] Another aspect of the present disclosure provides a method for operating the aforementioned NVM device-based CAM device structure unit, comprising: mapping a set storage logic value corresponding to a set storage vector to a first conductance value of a first NVM device cell and a second conductance value of a second NVM device cell of the CAM device structure unit based on a Euclidean distance encoding rule; mapping a set input logic value corresponding to a set search vector to a first input voltage of the first NVM device cell and a second input voltage of the second NVM device cell based on an input logic encoding rule; applying a first input voltage to the first NVM device cell and a second input voltage to the second NVM device cell, and sensing a bit line current of the bit line in response to a first read voltage applied to the first NVM device cell and a second read voltage applied to the second NVM device cell for determining the Euclidean distance.

[0013] Another aspect of the present disclosure provides a CAM device structure array based on an NVM device, which includes a plurality of CAM device modules, and the plurality of CAM device modules are arranged in a one-to-one correspondence with the plurality of bit lines along a first direction in which the plurality of bit lines are arranged; wherein each of the plurality of CAM device modules includes the aforementioned CAM device structure unit based on the NVM device, and the plurality of CAM device structure units are arranged along a second direction in which the plurality of word lines are arranged and connected to a corresponding one of the bit lines.

[0014] According to an embodiment of the present disclosure, the CAM device structure array based on NVM devices further includes a plurality of conversion modules, each of which corresponds one-to-one to a plurality of CAM device modules. Each of the plurality of conversion modules is connected in series to a bit line corresponding to a CAM device module to implement voltage conversion of the bit line current output by the corresponding CAM device module.

[0015] Another aspect of the present disclosure provides an electronic device including the above-mentioned CAM device structure array based on NVM devices.

[0016] (3) Beneficial effects

[0017] Compared with the prior art, the embodiments of the present disclosure provide the above-mentioned CAM device structure unit, array, operation method, and device based on NVM devices, which have at least the following beneficial effects:

[0018] (1) Since data is not lost after NVM power failure, the CAM device structure unit based on NVM does not need to be continuously powered to maintain data storage in the system standby state, and has lower device power consumption compared to traditional SRAM-based CAM devices;

[0019] (2) By utilizing the NVM device-based CAM device structure unit that requires only two NVM device units, a higher transistor density can be achieved compared to the dozen transistors required by conventional CAM devices, thereby greatly improving device performance;

[0020] (3) The CAM device structure unit based on the NVM device in the above-mentioned embodiment of the present disclosure can directly realize the parallel calculation of Euclidean distance. Compared with the Hamming distance calculation of traditional CAM devices, the device function is more powerful and the system calculation accuracy is higher.

[0021] Therefore, based on the above advantages, the technical content of the above-mentioned CAM device structural unit, array, operation method and equipment based on NVM devices in the embodiments of the present disclosure can achieve a CAM system design level with low power consumption, high density and the ability to meet the needs of complex application scenarios, which has extremely high scientific research value and commercial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematically shows the architecture composition diagram of a CAM device structural unit based on an NVM device according to an embodiment of the present disclosure;

[0023] Figure 2 Schematically shows the conductance values ​​G and G′ of two different transistors of a CAM device structure unit based on an NVM device according to an embodiment of the present disclosure, where the storage logic coding state of a 3-bit CAM corresponds to the conductance values ​​G and G′ of the two different transistors of the CAM device structure unit;

[0024] Figure 3 Schematically shows a search logic coding table of a 3-bit CAM corresponding to a CAM device structure unit based on an NVM device according to an embodiment of the present disclosure;

[0025] Figure 4 Schematically shows a truth table for calculating the Euclidean distance of a 3-bit CAM corresponding to a CAM device structure unit based on an NVM device according to an embodiment of the present disclosure;

[0026] Figure 5 A flowchart schematically illustrates an operation method of a CAM device structure unit based on an NVM device according to an embodiment of the present disclosure; and

[0027] Figure 6 The diagram schematically shows the architecture composition of a CAM device structure array based on NVM devices according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0029] It should be noted that any implementations not shown or described in the drawings or the main text of the specification are known to those skilled in the art and are not described in detail. Furthermore, the definitions of the various elements and methods described above are not limited to the specific structures, shapes, or methods described in the embodiments; those skilled in the art may easily modify or replace them.

[0030] It should also be noted that directional terms such as "upper," "lower," "front," "back," "left," and "right" mentioned in the embodiments are merely references to the directions in the accompanying drawings and are not intended to limit the scope of protection of this disclosure. Throughout the drawings, identical elements are represented by identical or similar reference numerals. Conventional structures or configurations will be omitted where they may cause confusion in understanding this disclosure.

[0031] Furthermore, the shapes and sizes of the components in the figures do not reflect the actual sizes and proportions, but are merely illustrative of the contents of the embodiments of the present disclosure. In addition, in the claims, any reference signs placed between brackets should not be construed as limiting the claims.

[0032] Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

[0033] The use of ordinal numbers such as "first," "second," "third," etc. in the specification and claims to modify corresponding elements does not in itself mean that the elements have any ordinal number, nor does it represent the order of one element relative to another or the order in the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish one element with a certain name from another element with the same name.

[0034] Those skilled in the art will appreciate that the modules in the devices of the embodiments may be adaptively changed and placed in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and further they may be divided into a plurality of submodules or subunits or subcomponents. All features disclosed in this specification (including the accompanying claims, abstract and drawings) and all processes or units of any method or device so disclosed may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose. Furthermore, in a unit claim enumerating a number of means, several of these means may be embodied by the same item of hardware.

[0035] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various disclosed aspects, in the above description of exemplary embodiments of the present disclosure, various features of the present disclosure are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed approach should not be interpreted as reflecting an intention that the claimed disclosure requires more features than are expressly recited in each claim. Rather, as reflected in the claims below, the disclosed aspects lie in less than all the features of the individual embodiments disclosed above. Accordingly, the claims that follow the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the present disclosure.

[0036] Traditional CAM devices are typically built on SRAM, where a single CAM cell consists of more than a dozen transistors, resulting in a large circuit area. Furthermore, since SRAM is volatile, data is lost upon power failure, leading to system standby power consumption. Furthermore, due to SRAM's binary storage characteristics, the CAM cell implemented can only store three states, '0', '1', and the wildcard 'X', known as ternary content addressable memory (TCAM). In this case, only the Hamming distance can be calculated. The Hamming distance represents the number of bits that differ between two binary strings of the same length. It is calculated by counting the number of '1' values ​​obtained by performing a bitwise exclusive-OR operation on the two strings, and its functionality is relatively simple.

[0037] With the development of the Internet of Things and big data, the amount of stored data requiring search has exploded, posing significant challenges to power consumption and circuit area. Furthermore, using the Hamming distance in complex tasks can significantly reduce overall system accuracy. In machine learning tasks, however, the Euclidean distance is widely used due to its greater power and accuracy. Therefore, there is an urgent need for a low-power, high-density memory device capable of calculating the Euclidean distance.

[0038] like Figure 1 As shown, one aspect of the present disclosure provides a CAM device structure unit based on an NVM device, which includes a first NVM device unit 110 and a second NVM device unit 120 .

[0039] The first NVM device unit 110 stores a first conductance value G mapped to a set storage logic value;

[0040] The second NVM device unit 120 stores a second conductance value G′ mapped to a set storage logic value, is disposed adjacent to the first NVM device unit 110, and is connected to the same bit line BL;

[0041] When a first input voltage V mapped to a set input logic value is applied to the first NVM device unit 110, and a second input voltage V′ mapped to a set input logic value is applied to the second NVM device unit 120, in response to a first read voltage V applied to the first NVM device unit 110, read1 and a second read voltage V applied to the second NVM device unit 120 read2 , the bit line current I of the bit line BL (Bit Line, BL for short) is read out to determine the Euclidean distance.

[0042] The bit line current value I represents the Euclidean distance between the set storage logic value and the set input logic value corresponding to the CAM device structure unit, and a larger bit line current I indicates a larger Euclidean distance. Finally, a readout module, such as an analog-to-digital conversion module, can convert the bit line current I into a voltage, thereby enabling the Euclidean distance to be read out.

[0043] In the embodiments of the present disclosure, an NVM device unit may refer to a type of semiconductor memory device in which stored data will not be lost after power failure. The semiconductor memory device includes non-volatile memory (NVM) devices such as flash memory, ferroelectric memory, resistive memory, phase change memory, and magnetoresistive memory. Among them, for flash memory or ferroelectric memory, its corresponding NVM device unit may be a transistor unit, and the transistor unit itself has a corresponding gate, source, and drain; and for resistive memory, phase change memory, or magnetoresistive memory, its corresponding NVM device unit may be a series structure of a transistor unit and a corresponding resistive unit, and the resistive unit may be connected in series with the source or drain of the transistor unit, and the transistor unit itself may also have a corresponding gate, source, and drain. Therefore, the NVM device units of the embodiments of the present disclosure generally can have corresponding gates, sources, and drains.

[0044] In the embodiments of the present disclosure, the NVM device unit may be a transistor unit of a flash memory device as described in detail below. That is, the first NVM device unit 110 may be a first transistor, and the second NVM device unit 120 may be a second transistor, which will not be described in detail below.

[0045] Among them, such as Figure 1As shown, in the NVM-based CAM device structure unit according to the embodiment of the present disclosure, the first NVM device unit and the second NVM device unit are connected side by side and adjacently on the same bit line BL, thereby providing a multi-valued CAM device implementation solution capable of calculating Euclidean distance. Compared to traditional SRAM-based devices, since data is not lost after NVM power failure, the NVM-based CAM device structure unit does not require continuous power supply to maintain data storage in system standby mode, and has lower device power consumption than traditional devices. In addition, with the help of the NVM-based CAM device structure unit requiring only two NVM device units, the transistor density can be higher than the dozen transistors required by traditional CAM devices, thereby greatly improving device operating performance. Furthermore, the NVM-based CAM device structure unit according to the embodiment of the present disclosure can directly implement parallel calculation of Euclidean distance. Compared with the Hamming distance calculation of traditional CAM devices, the device function is more powerful and the system calculation accuracy is higher.

[0046] It should be noted that the first read voltage V read1 and the second read voltage V of the second NVM device unit 120 read2 The word lines (WL) and source lines (SL) corresponding to the two NVM device units may be the same, and the word lines (WL) and source lines (SL) corresponding to the two NVM device units may be adjacent in space.

[0047] like Figure 1 As shown, according to an embodiment of the present disclosure, the drain of the first NVM device unit 110 is connected to the bit line BL; the drain of the second NVM device unit 120 is connected to the bit line BL. In this way, two NVM device units can be connected side by side and adjacent to each other on the same bit line BL.

[0048] like Figure 1 As shown, according to an embodiment of the present disclosure, the gate of the first NVM device unit 110 is used to apply a first input voltage V, and its source is used to apply a first read voltage V read1 The gate of the second NVM device unit 120 is used to apply a second input voltage V ', and its source is used to apply a second read voltage V read2 .

[0049] like Figure 1 The schematic diagram of the circuit structure of the CAM device structure unit based on the NVM device of the embodiment of the present disclosure is shown, wherein the preferred NVM device type is a flash memory device (other types of NVM devices such as ferroelectric memory, resistive random access memory, etc. are also applicable to the above-mentioned CAM device structure unit based on the NVM device). Figure 1As shown, a single CAM device structure unit is composed of two adjacent flash memory devices (ie, a first NVM device unit 110 and a second NVM device unit 120) connected on the same BL, and their corresponding word lines WL and source lines SL are adjacent to each other.

[0050] CAM definition Storage (x) Conductivity (G, G′) Input (y) Conductivity (V, V′) Distance (D) Current (I)

[0051] Table 1

[0052] As shown in Table 1 above, for Figure 1 For a single CAM device structure unit shown in FIG. 1 , its stored logic value (x) can be mapped to the conductance values ​​(i.e., the first conductance value G and the second conductance value G′) of the first NVM device unit 110 and the second NVM device unit 120 according to the square relationship in the Euclidean distance calculation formula, and the input logic value (y) to be searched is mapped to the input voltages (the first input voltage V and the second input voltage V′) applied to the two word lines WL, and then a fixed read voltage V is applied to the corresponding source lines (i.e., SL and SL′). read (The first reading voltage V read1 and the second read voltage V read2 ), the current (I) flowing through the bit line BL at this time represents the Euclidean distance (D) between the input logic value and the stored logic value, and its calculation formula (1) is as follows:

[0053]

[0054] Finally, the bitline BL current of a single CAM device structure unit can be converted into a voltage through an analog-to-digital conversion module to realize the readout of the result. The conductance value of each NVM device unit is defined as the ratio between the output current of the transistor device and the corresponding read voltage under the conditions of fixed wordline input voltage and source line read voltage.

[0055] In addition, since the above-mentioned CAM device structure unit can be applied to accelerate machine learning tasks (such as memory-enhanced neural networks), the main purpose can be to compare the relative sizes of distances between different storage vectors, and whether the square root operation is performed in the distance calculation will not affect the size order of different distances and the system accuracy. Therefore, the above-mentioned CAM device structure unit of the embodiment of the present disclosure can directly omit the square root operation of the Euclidean distance when outputting the result, thereby further accelerating the calculation speed of the Euclidean distance.

[0056] like Figure 1 and Figure 2As shown, according to an embodiment of the present disclosure, the first conductance value G is the product of the square of the set stored logic value and the set conductance step length; the second conductance value G′ is the product of the square of the negated value of the set stored logic value and the set conductance step length; the first conductance value G and the second conductance value G′ are complementary.

[0057] In the CAM device structure unit of the embodiment of the present disclosure, the multi-value storage logic can be proportionally mapped to the conductance values ​​of two NVM device units according to the square relationship in the Euclidean distance calculation formula (such as the above formula (1)). The specific operation is as follows:

[0058] The first conductance value G of the first NVM device unit is equal to the square of the storage logic value corresponding to the CAM device structure unit, and then multiplied by a fixed conductance step size. The conductance step size can be predetermined by the conductance range of the NVM device unit actually used;

[0059] The second conductance value G′ of the second NVM device unit is equal to the storage logic value corresponding to the CAM device structure unit, which is first negated, then squared, and then multiplied by the above-mentioned fixed conductance step size.

[0060] like Figure 2 The storage logic encoding scheme of the CAM device structure unit of the embodiment of the present disclosure is shown. Since the CAM device structure unit of the embodiment of the present disclosure can realize a multi-value CAM device, only 3-bit encoding is used as an example for description. Specifically, the storage logic encoding rule (i.e., the Euclidean distance encoding rule) of the CAM device structure unit is as follows: the first conductance value G of the first flash memory device as the first NVM device unit can be equal to the square of the storage logic value, and then multiplied by a fixed conductance step length V. step The second conductance value G′ of the second flash memory device as the second NVM device unit can be equal to the stored logic value first negated, then squared, and then multiplied by the above-mentioned conductance step length V step .

[0061] Accordingly, in 3-bit encoding, there are eight states of stored logic values: '0', '1', '2', '3', '4', '5', '6' and '7', and the conductance step size is determined by the conductance range of the device actually used. Here, it is assumed to be 1, then Figure 2 As shown in FIG. (a), the first conductance value G of the first flash memory device can be '0', '1', '4', '9', '16', '25', '36' and '49' in sequence. Figure 2As shown in Figure (b), the second conductance value G′ of the second flash memory device can be '49', '36', '25', '16', '9', '4', '1', and '0', respectively. This means that the first conductance value G of the first flash memory device increases squarely with increasing stored logic values, while the second conductance value G′ of the second flash memory device decreases squarely with increasing stored logic values, with the two values ​​complementing each other. Before starting the search, the storage vector must be encoded according to the aforementioned storage logic, and the write operation corresponding to the NVM device (programming or erasing the flash memory device) must be performed to set the device conductance to the corresponding value.

[0062] like Figure 1 and Figure 3 As shown, according to an embodiment of the present disclosure, the set input logic value is close to the set minimum logic value, the first input voltage V is the word line turn-on voltage corresponding to the set minimum logic value, and the second input voltage V′ is zero; the set input logic value is close to the set maximum logic value, the second input voltage V′ is the word line turn-on voltage corresponding to the set maximum logic value, and the first input voltage V is zero; the set input logic value is close to the set middle large logic value, the first input voltage V is zero, and the second input voltage V′ is zero.

[0063] The input logic of the CAM device structure unit that needs to be searched is encoded as a three-state and mapped to the input voltage of the two word lines WL. The specific operation is as follows:

[0064] If the input logic value corresponding to the CAM device structure unit is closer to the minimum logic value, the input logic value is encoded as the minimum logic value. At this time, the word line WL of the first NVM device unit is connected to the turn-on voltage as the first input voltage V, the word line WL of the second NVM device unit is grounded, and the second input voltage V′ is zero.

[0065] If the input logic value corresponding to the CAM device structure unit is closer to the maximum logic value, the input logic value is encoded as the maximum logic value. At this time, the word line WL of the first NVM device unit is grounded, the first input voltage V is zero, and the word line WL of the second NVM device unit is connected to the turn-on voltage of the second input voltage V′;

[0066] If the input logic value is closer to the intermediate logic value, the input logic value is encoded as a wildcard, i.e., the 'X' state, at which time the word lines WL of the first NVM device unit and the second NVM device unit are both grounded, i.e., the first input voltage V and the second input voltage V' are both zero.

[0067] A fixed read voltage is applied to the source line SL. The currents from the first and second NVM devices merge and flow out on the bit line BL. Based on the conductance-squared relationship set during encoding, the BL current value represents the Euclidean distance between the stored logic value and the input logic value, with larger currents representing larger distances. Finally, the bit line current is converted to a voltage by an analog-to-digital conversion module for readout.

[0068] like Figure 3 The search logic coding scheme of the CAM device structure unit of the embodiment of the present disclosure is also introduced using 3-bit coding as an example. Specifically, the input logic coding rules of the CAM device structure unit are as follows:

[0069] like Figure 3 As shown, if the input logic value corresponding to the CAM device structure unit is closer to the minimum logic value, that is, '0', '1' or '2', the input logic value is uniformly encoded to the minimum logic value '0'. At this time, the sub-line WL of the first flash memory device as the first NVM device unit is connected to the turn-on voltage V as the first input voltage V g , WL of the second flash memory device serving as the second NVM device unit is grounded, that is, the corresponding second input voltage V′ is zero;

[0070] like Figure 3 As shown, if the input logic value corresponding to the CAM device structure unit is closer to the maximum logic value, that is, '5', '6' or '7', the input logic value is uniformly encoded to the maximum logic value '7'. At this time, the sub-line WL of the first flash memory device is grounded, that is, the first input voltage V is zero, and the sub-line WL of the second flash memory device is connected to the turn-on voltage V as the second input voltage V'. g ;

[0071] like Figure 3 As shown in FIG, if the input logic value corresponding to the CAM device structure unit is closer to the intermediate logic value, that is, '5' or '6', it is encoded as the wildcard 'X' state. At this time, the WL of the first flash memory device and the second flash memory device are both grounded, that is, the first input voltage V and the second input voltage V' are both zero. Among them, the turn-on voltage V g The word line input voltage used to define the device conductance for the corresponding flash memory device.

[0072] Among them, whether the critical logical value (such as '2' or '5') is encoded as the minimum logical value or the maximum logical value ('0' or '7'), or encoded as a wildcard ('X'), its encoding preference can also be determined according to the specific application scenario and data distribution.

[0073] like Figure 4The truth table for calculating the Euclidean distance corresponding to the CAM device structure unit of the embodiment of the present disclosure is shown. Here, a 3-bit value is also used as an example for explanation. As mentioned above, the input logic value for searching the CAM device structure unit is mapped to the input voltage applied to the two word lines WL of the CAM device structure unit, and the corresponding read voltage V is applied to the corresponding source line SL. read At this time, the output currents of the first flash memory device as the first NVM device unit and the second flash memory device as the second NVM device unit merge and flow out on the bit line BL. This current value I represents the Euclidean distance between the input logic value and the stored logic value. The larger the current, the larger the Euclidean distance between the two. Figure 4 As shown, the grayscale value of a cell represents the magnitude of the output current on the BL. For an input of '0', the distance from the stored logical value increases squared, while for an input of '7', the distance from the stored logical value decreases squared. For an input wildcard of 'X', the distance from the stored logical value is always '0'. This demonstrates the calculation of the Euclidean distance between input and stored values ​​within the CAM device structure. In other words, the CAM device structure of the disclosed embodiments effectively implements Euclidean distance calculation.

[0074] like Figure 1 and Figure 5 As shown, another aspect of the present disclosure provides an operation method of the above-mentioned CAM device structure unit based on the NVM device, which includes steps S501-S503.

[0075] In step S501, a set storage logic value corresponding to a set storage vector is mapped to a first conductance value of a first NVM device unit and a second conductance value of a second NVM device unit of the CAM device structure unit based on a Euclidean distance encoding rule;

[0076] In step S502, mapping the set input logic value corresponding to the set search vector to the first input voltage of the first NVM device unit and the second input voltage of the second NVM device unit based on the input logic coding rule;

[0077] In step S503, a first input voltage is applied to the first NVM device cell, and a second input voltage is applied to the second NVM device cell. In response to the first read voltage applied to the first NVM device cell and the second read voltage applied to the second NVM device cell, a bit line current of the bit line is sensed for determining the Euclidean distance.

[0078] Regarding the above Figure 1 The CAM device structure unit of the embodiment of the present disclosure is operated accordingly to realize the calculation of the Euclidean distance, which can be realized by referring to the following steps:

[0079] First, the storage vector corresponding to the Euclidean distance calculation formula (refer to the above formula (1)) can be encoded according to the above Euclidean distance encoding rules (such as Figure 2 ) is mapped into the conductance value of the above-mentioned CAM device structure unit, that is, the first conductance value of the first NVM device unit and the second conductance value of the second NVM device unit;

[0080] Secondly, the search vector corresponding to the Euclidean distance calculation formula can be encoded according to the above input logic rules (such as Figure 3 ) is mapped to the WL input voltage of the above-mentioned CAM device structure unit, that is, the first input voltage of the first NVM device unit and the second input voltage of the second NVM device unit;

[0081] Finally, when the above mapping conductance and input voltage are satisfied, a fixed read voltage is applied to the corresponding source line SL of the above CAM device structure unit, and the current of the NVM array BL is detected by the analog-to-digital conversion module to realize parallel Euclidean distance calculation.

[0082] It should be noted that there is no specific restriction on the order of operations involved in the above steps S501-S503, etc., and the specific order is based on whether the corresponding current reading conditions are met. That is, when the input logic value and the stored logic value meet the conditions, when the corresponding operating voltage and read voltage are applied to the two NVM device units corresponding to the same CAM device structure unit, the bit line current of the CAM device structure unit can be read.

[0083] like Figure 1 and Figure 6 As shown, another aspect of the present disclosure provides a CAM device structure array based on NVM devices, wherein the array includes a plurality of CAM device modules, wherein the plurality of CAM device modules are arranged along a plurality of bit lines BL1, BL2, ... BL n The first direction d1 of the arrangement is connected to a plurality of bit lines BL1, BL2, ... BL n One-to-one corresponding arrangement settings;

[0084] Each of the plurality of CAM device modules includes the aforementioned CAM device structure unit based on the NVM device, and the plurality of CAM device structure units are arranged along a plurality of word lines WL1, WL1', ... WL k 、WL k The second direction d2 of the arrangement is arranged and connected to a corresponding bit line.

[0085] like Figure 6As shown, different CAM device structure units are connected in a cross-array relationship to form a CAM device structure array for storing vectors and performing parallel distance calculations. The connection correspondence of the CAM device structure array is as follows: CAM device structure units connected to the same bit line BL together form a CAM device module, which corresponds to a CAM storage vector. That is, the currents of these CAM device structure units in the CAM device module are all converged and read out on the bit line BL. The input search vector and the storage vector of the CAM device structure array have the same dimensions and are applied to the word lines WL of each CAM device structure unit. The Euclidean distance between the input search vector and the storage vector is equal to the sum of the Euclidean distances between each element (i.e., each CAM device structure unit). The CAM storage vectors stored on different bit lines BL are independent of each other and are detected and read out in parallel. That is, the input search vector and each CAM storage vector are simultaneously subjected to Euclidean distance calculations and read out simultaneously through the analog-to-digital conversion module.

[0086] like Figure 6 The diagram of the CAM device structure array based on a flash memory device and an NVM device according to an embodiment of the present disclosure shows that different CAM device structure units are connected along the second direction d2 on the same bit line to form a CAM device module. Multiple CAM device modules are arranged in parallel along the first direction d1 in a cross-array connection to form the CAM device structure array, which is used for vector storage and large-scale parallel distance calculation. The connection correspondence of the CAM device structure array is as follows: the CAM device structure units connected to the same bit line BL together form a CAM storage vector, that is, the currents of these CAM device structure units are all converged and read out on the bit line BL; the input search vector and the CAM storage vector have the same dimension, both k-dimensional, and are applied to the word lines WL of each CAM device structure unit; all source lines SL of the CAM device structure array are applied with the same read voltage V read The Euclidean distance between the input search vector and the storage vector is equal to the sum of the Euclidean distances between each element (i.e., each CAM device structural unit); the CAM storage vectors stored on different bit lines BL are independent of each other and are detected and read in parallel, i.e., the input search vector and Figure 6 The n CAM storage vectors shown in FIG. 1 are all subjected to Euclidean distance calculations simultaneously and are read out simultaneously through the analog-to-digital conversion module. Figure 1 Each CAM device structure unit in the CAM device structure array has two parallel NVM device units connected to the same bit line, such as CAM device structure unit T 11 As shown, the CAM device structure array has a total of k×n cross-connected CAM device structure units, totaling 2×k×n NVM device units.

[0087] like Figure 1 and Figure 6 As shown, according to an embodiment of the present disclosure, the CAM device structure array based on the NVM device further includes a plurality of conversion modules AD1, AD2, ... AD n , multiple conversion modules AD1, AD2, ...AD n There are multiple CAM device modules corresponding to each other, and the multiple conversion modules AD1, AD2, ... AD n Each conversion module in the CAM device module is connected in series with the bit line (ie BL1, BL2, ... BL n ), so as to realize voltage conversion of the bit line current output by the corresponding CAM device module.

[0088] like Figure 1 As shown, the bit line output current I of each CAM device structure unit can be A / D converted and output by a conversion module AD0 to output its corresponding current in the form of voltage. Figure 6 As shown, for the CAM device structure array, all CAM device structure units on the same bit line can use the conversion module corresponding to the bit line to uniformly convert and output the current of all elements, that is, the sum of the output currents of all CAM device structure units on the bit line BL1 can be converted and output together through the conversion module AD1.

[0089] It should be noted that those skilled in the art can easily learn the operation method for the above-mentioned CAM device structure array based on the above-mentioned operation method for the CAM device structure unit to achieve large-scale parallel Euclidean distance calculation, which is not described in detail here.

[0090] Another aspect of the present disclosure provides an electronic device comprising the aforementioned NVM-based CAM device array. The NVM-based CAM device array can be applied to electronic chips for large-scale neural network computing. The electronic device can be any type of smart device with corresponding functions, including but not limited to portable electronic devices such as mobile phones, computers, and PADs, as well as various smart devices with high-performance computing capabilities.

[0091] Compared with the prior art, the embodiments of the present disclosure provide the above-mentioned CAM device structure unit, array, operation method, and device based on NVM devices, which have at least the following beneficial effects:

[0092] (1) Since data is not lost after NVM power failure, the CAM device structure unit based on NVM does not need to be continuously powered to maintain data storage in the system standby state, and has lower device power consumption compared to traditional SRAM-based CAM devices;

[0093] (2) By utilizing the NVM device-based CAM device structure unit that requires only two NVM device units, a higher transistor density can be achieved compared to the dozen transistors required by conventional CAM devices, thereby greatly improving device performance;

[0094] (3) The CAM device structure unit based on the NVM device in the above-mentioned embodiment of the present disclosure can directly realize the parallel calculation of Euclidean distance. Compared with the Hamming distance calculation of traditional CAM devices, the device function is more powerful and the system calculation accuracy is higher.

[0095] Therefore, based on the above advantages, the technical content of the above-mentioned CAM device structure unit, array, operation method and equipment based on NVM devices in the embodiments of the present disclosure can have extremely high scientific research value and commercial utilization value for the future design of low-power, high-density CAM systems that can meet the needs of complex application scenarios.

[0096] So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings.

[0097] The above specific embodiments further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A CAM device structure unit based on an NVM device, wherein: include: a first NVM device unit storing a first conductance value mapped to a set storage logic value; a second NVM device unit storing a second conductance value mapped to a set storage logic value, disposed adjacent to the first NVM device unit and connected to the same bit line; When a first input voltage mapped to a set input logic value is applied to the first NVM device cell and a second input voltage mapped to the set input logic value is applied to the second NVM device cell, a bit line current of the bit line is sensed in response to a first read voltage applied to the first NVM device cell and a second read voltage applied to the second NVM device cell for determining the Euclidean distance.

2. The CAM device structure unit based on the NVM device according to claim 1, wherein: The drain of the first NVM device unit is connected to the bit line; A drain of the second NVM device cell is connected to the bit line.

3. The CAM device structure unit based on the NVM device according to claim 1, wherein: The gate of the first NVM device unit is used to apply a first input voltage, and the source thereof is used to apply a first read voltage; The gate of the second NVM device unit is used to apply a second input voltage, and the source thereof is used to apply a second read voltage.

4. The CAM device structure unit based on the NVM device according to claim 1, wherein: The first conductance value is the product of the square of the set storage logic value and the set conductance step length; The second conductance value is a product of the square of the negated value of the set stored logical value and the set conductance step length; The first conductance value is complementary to the second conductance value.

5. The CAM device structure unit based on the NVM device according to claim 1, wherein: The set input logic value is close to a set minimum logic value, the first input voltage is a word line turn-on voltage corresponding to the set minimum logic value, and the second input voltage is zero; The set input logic value is close to the set maximum logic value, the second input voltage is a word line turn-on voltage corresponding to the set maximum logic value, and the first input voltage is zero; The set input logic value is close to a set intermediate large logic value, the first input voltage is zero, and the second input voltage is zero.

6. An operating method of a CAM device structure unit based on an NVM device according to any one of claims 1 to 5, wherein: include: Mapping the set storage logic value corresponding to the set storage vector to a first conductance value of a first NVM device unit and a second conductance value of a second NVM device unit of the CAM device structure unit based on a Euclidean distance encoding rule; Mapping a set input logic value corresponding to a set search vector to a first input voltage of the first NVM device unit and a second input voltage of a second NVM device unit based on an input logic coding rule; A first input voltage is applied to the first NVM device cell, and a second input voltage is applied to the second NVM device cell, and a bit line current of the bit line is sensed in response to a first read voltage applied to the first NVM device cell and a second read voltage applied to the second NVM device cell for determining a Euclidean distance.

7. A CAM device structure array based on NVM devices, wherein: include: A plurality of CAM device modules are arranged in a one-to-one correspondence with the plurality of bit lines along a first direction in which the plurality of bit lines are arranged; Among them, each CAM device module in the multiple CAM device modules includes multiple CAM device structure units based on NVM devices as described in any one of claims 1-5, and the multiple CAM device structure units are arranged along the second direction of the multiple word lines and connected to a corresponding bit line.

8. The CAM device structure array based on NVM devices according to claim 7, wherein: Also includes: The plurality of conversion modules correspond one to one with the plurality of CAM device modules. Each of the plurality of conversion modules is connected in series to the bit line of a corresponding CAM device module to realize voltage conversion of the bit line current output by the corresponding CAM device module.

9. An electronic device comprising the CAM device structure array based on the NVM device according to claim 7 or 8.

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