A differential OTP memory cell circuit and related apparatus

Abstract

A differential OTP storage unit circuit and related equipment, the differential OTP storage unit circuit includes first selection tube, first storage tube, second storage tube and second selection tube, when programming data "0", the first storage tube is programmed, the second storage tube is not programmed;The current provided by the first selection tube is > 0uA, the current provided by the second selection tube is ~ 0uA;When programming data "1", the second storage tube is programmed, the first storage tube is not programmed;The current provided by the first selection tube is ~ 0uA, the current provided by the second selection tube is > 0uA.In the case of keeping the difference current of the 2 input ends of the comparator consistent with the traditional storage unit, both are Iref, the current Icell0 or the current Icell1 after programming only needs to be Iref, which greatly reduces the requirement for the current of the storage tube after programming, and improves the reliability of the output result of the differential OTP storage unit circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a differential OTP storage unit circuit and related equipment. BACKGROUND

[0002] Figure 1 A schematic diagram of a traditional OTP storage unit, which is composed of a selection tube M1 and a storage tube M2, U1 is a comparator, SIGin and SIGout are used to represent intermediate transmission signals, and the device where SIGin and SIGout are located can be understood as an intermediate device, for example, a selection device.

[0003] When the traditional OTP storage unit is used to store data, before programming operation, the storage unit current Icell is close to 0, representing storage data "0"; during programming, the gate oxide layer of the storage tube M2 is broken down, the Icell current increases, representing storage data "1".

[0004] The comparator module U1 compares the OTP storage unit output current Icell and the reference current Iref, and outputs data "0" or "1". In order to ensure that the comparator module U1 can stably output data "1", it is required that the difference at the input end of the comparator module U1 is Iref, and the current Icell of the OTP storage unit after programming is close to 2*Iref.

[0005] Due to the uncontrollable programming process of the OTP storage unit and the random differences in the manufacturing process of the storage tube device, the Icell size of the storage unit after programming will be randomly distributed, and there will generally be a small current tail current unit, and the comparator module U1 is difficult to stably output the data "1" stored by the tail current unit. SUMMARY

[0006] Therefore, the embodiments of the present application provide a differential OTP storage unit circuit and related equipment to realize stable output of the differential OTP storage unit circuit.

[0007] To achieve the above purpose, the embodiments of the present application provide the following technical solutions:

[0008] A differential OTP storage unit circuit, comprising:

[0009] A first storage unit and a second storage unit;

[0010] The first storage unit comprises a first selection tube and a first storage tube, and the second storage unit comprises a second selection tube and a second storage tube;

[0011] The control ends of the first selection tube, the first storage tube, the second selection tube and the second storage tube serve as input ends of the differential OTP storage unit structure, and are used to obtain control signals;

[0012] a drain of the first select transistor is connected to a source of the first storage transistor;

[0013] a drain of the second select transistor is connected to a source of the second storage transistor;

[0014] a source of the first select transistor is used as a first output terminal of the differential OTP storage unit circuit, and is connected to a first input terminal of a comparator;

[0015] a source of the second select transistor is used as a second output terminal of the differential OTP storage unit circuit, and is connected to a second input terminal of the comparator.

[0016] Optionally, in the differential OTP storage unit circuit, the source of the first select transistor and the source of the second select transistor are further used to obtain a voltage applied by an external device.

[0017] Optionally, in the differential OTP storage unit circuit, control terminals of the first select transistor and the second select transistor are used as first input terminals of the differential OTP storage unit structure, and are used to obtain a first control signal.

[0018] control terminals of the first storage transistor and the second storage transistor are used as second input terminals of the differential OTP storage unit structure, and are used to obtain a second control signal.

[0019] Optionally, in the differential OTP storage unit circuit, control terminals of the first storage transistor and the second storage transistor are used as second input terminals of the differential OTP storage unit structure, and are used to obtain a second control signal.

[0020] A data processing circuit, comprising the differential OTP storage unit circuit according to any one of the preceding embodiments.

[0021] A differential OTP storage unit circuit, comprising:

[0022] a first storage unit and a second storage unit;

[0023] the first storage unit comprises a first select transistor and a first storage transistor, and the second storage unit comprises a second select transistor and a second storage transistor;

[0024] control terminals of the first select transistor and the second select transistor are used as input terminals of the differential OTP storage unit structure, and are used to obtain a first control signal.

[0025] the control terminal of the first select transistor is used to obtain a second control signal, and the control terminal of the second select transistor is used to obtain a third control signal.

[0026] drains of the control terminals of the first select transistor and the second select transistor are grounded.

[0027] The source of the first selection tube is connected with the drain of the first storage tube, and the source of the first storage tube is suspended;

[0028] The source of the second selection tube is connected with the drain of the second storage tube, and the source of the second storage tube is suspended;

[0029] The control end of the first storage tube is used as the first output end of the differential OTP storage unit circuit, and is connected with the first input end of the comparator;

[0030] The control end of the second storage tube is used as the second output end of the differential OTP storage unit circuit, and is connected with the second input end of the comparator.

[0031] Optionally, the differential OTP storage unit circuit, the first control signal comprises a first sub-control signal and a second sub-control signal;

[0032] The control end of the first selection tube is used for obtaining the first sub-control signal;

[0033] The control end of the second selection tube is used for obtaining the second sub-control signal.

[0034] Optionally, the differential OTP storage unit circuit, the first control signal comprises a first sub-control signal and a second sub-control signal;

[0035] The control end of the first selection tube is used for obtaining the first sub-control signal;

[0036] The control end of the second selection tube is used for obtaining the second sub-control signal.

[0037] Optionally, the differential OTP storage unit circuit, the breakdown voltage of the first selection tube, the second selection tube, the first storage tube and the second storage tube is same or different.

[0038] The data processing circuit includes the differential OTP storage unit circuit in any of the above technical solutions, and the above scheme provided by the embodiment of the application is based on the above technical solutions, when data "0" needs to be programmed, the first storage tube is programmed, and the second storage tube is not programmed; at this time, the storage current Icell0 provided by the first selection tube is > 0uA, and the storage current Icell1 provided by the second selection tube is ~ 0uA; when data "1" is programmed, the second storage tube is programmed, and the first storage tube is not programmed; the storage current Icell0 provided by the first selection tube is ~ 0uA, and the storage current Icell1 provided by the second selection tube is > 0uA. In the case that the difference current of the two input ends of the comparator is consistent with the conventional storage unit, that is, Iref, the current Icell0 or the current Icell1 after programming only needs to be Iref, which greatly reduces the requirement on the current of the storage tube after programming. At this time, the smaller tail current unit can also stably output data, and the reliability of the output result of the differential OTP storage unit circuit is improved. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of the provided drawings.

[0040] Figure 1 It is a structural schematic diagram of a conventional OTP storage unit;

[0041] Figure 2 It is a structural schematic diagram of a differential OTP storage unit circuit disclosed by the embodiment of the application;

[0042] Figure 3 It is a structural schematic diagram of another differential OTP storage unit circuit disclosed by the embodiment of the application;

[0043] Figure 4 It is a structural schematic diagram of another differential OTP storage unit circuit disclosed by the embodiment of the application;

[0044] Figure 5 It is a structural schematic diagram of another differential OTP storage unit circuit disclosed by the embodiment of the application. DETAILED DESCRIPTION

[0045] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments of the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of the present application.

[0046] In the present scheme, in order to provide a storage unit capable of stable output, the present application discloses a differential OTP storage unit circuit, by setting two groups of selection tubes and storage tubes, when editing "0" and "1", two selection tubes are used to provide different sizes of storage current Icell0 and storage current Icell1 respectively, that is, in the present scheme, the two selection tubes are respectively referred to as a first selection tube and a second selection tube, when editing "0" and "1", the first selection tube provides a storage current Icell0 and the second selection tube provides a storage current Icell1, the storage current Icell0 and the storage current Icell1 are loaded to the non-inverting input terminal and the inverting input terminal of the comparator respectively, in the case of keeping the difference current of the non-inverting input terminal and the inverting input terminal of the comparator consistent with the conventional storage unit, both Iref, the current size of the storage tube Icell0 or Icell1 after programming only needs to be Iref, which greatly reduces the requirement for the current of the storage tube after programming. At this time, the smaller tail current unit can also stably output data.

[0047] Specifically, the embodiment of the present application discloses a differential OTP storage unit circuit, referring to Figure 2 The circuit structure specifically includes:

[0048] The first storage unit 100 and the second storage unit 200;

[0049] The first storage unit 100 includes a first selection tube M11 and a first storage tube M22, and the second storage unit 200 includes a second storage tube M33 and a second selection tube M44;

[0050] The control end of the first selection tube M11, the first storage tube M22, the second selection tube M44 and the second storage tube M33 is used as the input end of the differential OTP storage unit structure, for obtaining a control signal WL, in the present scheme, the control end of the first selection tube M11, the first storage tube M22, the second selection tube M44 and the second storage tube M33 refers to the gate of each tube;

[0051] The drain of the first selection tube M11 is connected with the source of the first storage tube M22;

[0052] The drain of the second selection tube M44 is connected with the source of the second storage tube M33;

[0053] The source of the first selection tube M11 is used as the first output end of the differential OTP storage unit circuit, and is connected with the first input end of the comparator;

[0054] The source of the second selection tube M44 is used as the second output end of the differential OTP storage unit circuit, and is connected with the second input end of the comparator. The first input end of the comparator can be the inverting input end of the comparator, and the second input end of the comparator can be the non-inverting input end of the comparator. The comparator is used to compare the input signals of the first input end and the second input end, and generate an output signal based on the comparison result.

[0055] The source of the first selection tube and the source of the second selection tube are also used to obtain the voltage applied by an external device, Figure 2 BL0 and BL1 are respectively used to represent the voltage applied to the source of the first selection tube M11 and the voltage applied to the source of the second selection tube M44. The BL0 and BL1 are provided by an external device, and the values of the BL0 and BL1 change according to the change of the storage tube required to be edited. Figure 2The control signal WL has a voltage of VPP (2-10v). The differential OTP memory cell circuit provided by the embodiment of the present application comprises a first selection transistor M11 and a first memory transistor M22, a second memory transistor M33 and a second selection transistor M44. When data "0" needs to be programmed, referring to Table 1, the external device applies a voltage BL0 of 0 to the source of the first selection transistor M11, and applies a voltage BL1 of VPP (2-10v) or floating to the source of the second selection transistor M44. At this time, the first selection transistor M11 can be turned on under the control of the control signal WL, while the second selection transistor M44 cannot be turned on under the control of the control signal WL due to the voltage of VPP (2-10v) or floating of the source of the second selection transistor M44. At this time, the first memory transistor M22 can be programmed, and the second memory transistor M33 cannot be programmed. At this time, the first selection transistor M11 provides a storage current Icell0>0uA, and the second selection transistor M44 provides a storage current Icell1<0uA. When data "1" needs to be programmed, referring to Table 1, the external device applies a voltage BL1 of 0 to the source of the second selection transistor M44, and applies a voltage BL0 of VPP (2-10v) or floating to the source of the first selection transistor M11. At this time, the second selection transistor M44 can be turned on under the control of the control signal WL, while the first selection transistor M11 cannot be turned on under the control of the control signal WL due to the voltage of VPP (2-10v) or floating of the source of the first selection transistor M11. At this time, the second memory transistor M33 is programmed, and the first memory transistor M22 is not programmed. The first selection transistor M11 provides a storage current Icell0<0uA, and the second selection transistor M44 provides a storage current Icell1>0uA. In the case that the difference current of the two input ends of the comparator is consistent with the conventional memory cell, and is Iref, the current Icell0 or the current Icell1 after programming only needs to be Iref, which greatly reduces the requirement on the current after programming of the memory transistor. At this time, a smaller tail current unit can also stably output data.

[0056] Table 1

[0057]

[0058] In the technical solution disclosed by the embodiment of the present application, the breakdown voltages of the first selection transistor M11, the first memory transistor M22, the second memory transistor M33 and the second selection transistor M44 can be partially the same or completely the same. For example, the breakdown voltages of the first selection transistor M11 and the second selection transistor M44 are the same, and the breakdown voltages of the first memory transistor M22 and the second memory transistor M33 are the same.

[0059] In the technical scheme disclosed in the embodiment, the first selection tube M11 and the second selection tube M44 can adopt different control signals, that is, the control end of the first selection tube M11 and the second selection tube M44 serves as the first input end of the differential OTP storage unit structure, and is used to obtain a first control signal PL; the control end of the first storage tube M22 and the second storage tube M33 serves as the second input end of the differential OTP storage unit structure, and is used to obtain a second control signal WL. For example, refer to Figure 3 In the scheme, the first selection tube M11 and the second selection tube M44 can adopt the control signal PL, and the first storage tube M22 and the second storage tube M33 can adopt the control signal WL. In the embodiment, the WL signal can be VPW (2-10v), and the PL signal can be VPP (2-10v). Refer to Table 2. When data "0" needs to be programmed, refer to Table 2. The voltage of the control signal PL is VPP (2-10v), the voltage of the control signal WL is VPW (2-10v), the value of the voltage BL0 applied to the source of the first selection tube M11 by an external device is 0, and the value of the voltage BL1 applied to the source of the second selection tube M44 is 2-10v or floating. At this time, the first selection tube M11 can be turned on under the control of the control signal WL, the first storage tube M22 can be turned on under the control of the control signal PL, and the second selection tube M44 cannot be turned on due to the source voltage of 2-10v or floating of the second selection tube M44. At this time, the second storage tube M33 also cannot be turned on. At this time, the first storage tube M22 can be programmed, and the second storage tube M33 cannot be programmed. At this time, the storage current Icell0 provided by the first selection tube M11 is greater than 0uA, and the storage current Icell1 provided by the second selection tube M44 is 0uA. When data "1" is programmed, refer to Table 2. The voltage of the control signal PL is VPP (2-10v), the voltage of the control signal WL is VPW (2-10v), the value of the voltage BL0 applied to the source of the first selection tube M11 by an external device is 2-10v or floating, and the value of the voltage BL1 applied to the source of the second selection tube M44 is 0. At this time, the first selection tube M11 cannot be turned on, the first storage tube M22 cannot be turned on under the control of the control signal PL, and the second selection tube M44 is turned on. At this time, the second storage tube M33 is turned on. At this time, the first storage tube M22 cannot be programmed, and the second storage tube M33 can be programmed. At this time, the storage current Icell0 provided by the second selection tube M44 is greater than 0uA, and the storage current Icell1 provided by the first selection tube M11 is 0uA.

[0060] Table 2

[0061]

[0062]

[0063] The differential OTP storage unit circuit disclosed in the above embodiments of the present application can be used as a PUF and a random number generator in addition to being used as a memory. In this case, the control modes of the WL, BL0 and BL1 are shown in Table 3 for the embodiment corresponding to Figure 2 The control modes of the WL, BL0 and BL1 are shown in Table 4 for the embodiment corresponding to Figure 3 When the differential OTP storage unit circuit is used as a PUF and a random number generator, the first storage unit and the second storage unit are programmed at the same time. After programming, Icell0 and Icell1 will randomly present two different current values. The reason for this is that there is a difference in the conduction time of the first storage tube and the second storage tube. The switch tube that conducts first will pull down the voltage of the switch tube that conducts later, so that the values of Icell0 and Icell1 are different. When Icell0 > Icell1, the comparator outputs "0". When Icell0 < Icell1, the comparator outputs "1". In this case, the comparator output data presents a random distribution. The differential OTP storage unit circuit can be applied to a PUF and a random number generator.

[0064] Table 3

[0065] WL BL0 BL1 Programming VPP (2-10v) 0 0

[0066] Table 4

[0067] WL PL BL0 BL1 Programming VPW (2-10v) VPP (2-10v) 0 0

[0068] Similarly to the above scheme principle, the present application also discloses a differential OTP storage unit circuit, which is shown in Figure 4 The circuit can also include a first storage unit 100 and a second storage unit 200.

[0069] Similarly, the first storage unit includes a first selection tube M11 and a first storage tube M22, and the second storage unit includes a second selection tube M44 and a second storage tube M33.

[0070] Unlike the differential OTP storage unit circuit disclosed in the above embodiment, in the differential OTP storage unit circuit disclosed in the present embodiment, the control end of the first selection tube M11 and the control end of the second selection tube M44 serve as the input end of the differential OTP storage unit structure, and are used to obtain a first control signal WL. In addition, the control end of the first selection tube M11 is used to obtain a second control signal PL0, and the control end of the second selection tube M44 is used to obtain a third control signal PL1.

[0071] Unlike the previous differential OTP memory cell circuit, the drains of the control terminals of the first selection transistor M11 and the second selection transistor M44 are grounded.

[0072] The source of the first selection transistor M11 is connected to the drain of the first storage transistor M22. Unlike the previous differential OTP memory cell circuit, the source of the first storage transistor M22 is left floating.

[0073] The source of the second selection transistor M44 is connected to the drain of the second storage transistor M33. Unlike the previous differential OTP memory cell circuit, the source of the second storage transistor M33 is left floating.

[0074] Unlike the previous differential OTP memory cell circuit, the control terminal of the first memory transistor M22 serves as the first output terminal of the differential OTP memory cell circuit, and is used to connect to the first input terminal of the comparator.

[0075] The control terminal of the second storage tube M33 serves as the second output terminal of the differential OTP storage cell circuit and is connected to the second input terminal of the comparator.

[0076] When Figure 4 When the differential OTP memory cell circuit shown is used as a memory, the control methods for signals WL, PL0, PL1, and BL are shown in Table 5:

[0077] Table 5

[0078]

[0079] See Figure 5 When the first control signal WL is split into a first sub-control signal WL0 and a second sub-control signal WL1, the first sub-control signal WL0 is applied to the control terminal of the first selection transistor M11, and the second sub-control signal WL1 is applied to the control terminal of the second selection transistor M44. At this time, when the differential OTP memory cell circuit is used as a memory, the control methods of signals WL0, WL1, PL0, PL1, and BL are shown in Table 6.

[0080] Table 6

[0081]

[0082] Corresponding to Figure 4 and Figure 5 The corresponding embodiment discloses a differential OTP memory cell circuit structure, which, in addition to being used as a memory, can also be used as a PUF (Programmable Array of Elements) and a random number generator. In this case, the corresponding... Figure 4 In the embodiment, the control methods of WL, BL0, and BL1 are shown in Table 7. Corresponding to... Figure 5In the embodiment, the control modes of the WL, the BL0 and the BL1 are shown in Table 8. When the differential OTP memory cell circuit is used as a PUF and a random number generator, the first memory cell and the second memory cell are programmed simultaneously, and after programming, Icell0 and Icell1 randomly present two different current values. When Icell0>Icell1, the comparator outputs "0", and when Icell0<Icell1, the comparator outputs "1". At this time, the comparator output data presents a random distribution, and the differential OTP memory cell circuit can be applied to a PUF and a random number generator.

[0083] Table 7

[0084]

[0085] Table 8

[0086]

[0087] Further, the application also discloses a data processing circuit, the memory and the PUF and the random number generator apply the differential OTP memory cell circuit which is described in any one of the preceding embodiments, and the data processing circuit can be a memory or a PUF and a random number generator. The PUF (Physical Unclonable Function, PUF) and the random number generator refer to a random number generator based on a PUF.

[0088] The application also discloses an electronic device, and the electronic device applies the differential OTP memory cell circuit which is described in any one of the preceding embodiments.

[0089] The embodiments in the specification are described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts of each embodiment can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the related parts can be referred to the method part.

[0090] The above description of the disclosed embodiments enables a person skilled in the art to implement or use the application. Various modifications of the embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the application. Therefore, the application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A differential OTP memory cell circuit, comprising: Comprising: a first storage unit and a second storage unit; the first storage unit comprises a first select transistor and a first storage transistor, and the second storage unit comprises a second select transistor and a second storage transistor; control terminals of the first select transistor, the first storage transistor, the second select transistor and the second storage transistor are used as input terminals of the differential OTP storage unit structure to obtain control signals; drains of the first storage transistor and the second storage transistor are left floating; a drain of the first select transistor is connected to a source of the first storage transistor; a drain of the second select transistor is connected to a source of the second storage transistor; a source of the first select transistor is used as a first output terminal of the differential OTP storage unit circuit to be connected to a first input terminal of a comparator, and the first select transistor is configured to be in an off state by obtaining a peak-to-peak voltage VPP or floating through the source of the first select transistor when the second storage transistor is programmed, so as to prevent a programming current from flowing to the first storage transistor; a source of the second select transistor is used as a second output terminal of the differential OTP storage unit circuit to be connected to a second input terminal of the comparator, and the second select transistor is configured to be in an off state by obtaining a peak-to-peak voltage VPP or floating through the source of the second select transistor when the first storage transistor is programmed, so as to prevent a programming current from flowing to the second storage transistor.

2. The differential OTP storage unit circuit according to claim 1, wherein: the source of the first select transistor and the source of the second select transistor are further used to obtain a voltage applied by an external device.

3. The differential OTP memory cell circuit of claim 1, wherein, control terminals of the first select transistor and the second select transistor are used as first input terminals of the differential OTP storage unit structure to obtain first control signals; control terminals of the first storage transistor and the second storage transistor are used as second input terminals of the differential OTP storage unit structure to obtain second control signals.

4. The differential OTP memory cell circuit of claim 1, wherein, breakdown voltages of the first select transistor, the second select transistor, the first storage transistor and the second storage transistor are the same or different.

5. A data processing circuit, characterized by The differential OTP storage unit circuit comprises any one of claims 1-4.

6. A differential OTP memory cell circuit, comprising: Comprising: a first storage unit and a second storage unit; the first storage unit comprises a first select transistor and a first storage transistor, and the second storage unit comprises a second select transistor and a second storage transistor; control terminals of the first select transistor and the second select transistor are used as input terminals of the differential OTP storage unit structure; the control terminal of the first select transistor is used to obtain a second control signal, and the control terminal of the second select transistor is used to obtain a third control signal; drains of the first select transistor and the second select transistor are grounded by an external device; a source of the first select transistor is connected to a drain of the first storage transistor, and a source of the first storage transistor is left floating; a source of the second select transistor is connected to a drain of the second storage transistor, and a source of the second storage transistor is left floating; a control terminal of the first storage transistor is used as a first output terminal of the differential OTP storage unit circuit to be connected to a first input terminal of a comparator; The control end of the second storage tube is connected with the second input end of the comparator as the second output end of the differential OTP storage unit circuit.

7. The differential OTP memory cell circuit of claim 6, wherein, The input end of the differential OTP storage unit structure is used for obtaining a first control signal, and the first control signal comprises a first sub-control signal and a second sub-control signal. The control end of the first selection tube is used for obtaining the first sub-control signal. The control end of the second selection tube is used for obtaining the second sub-control signal.

8. The differential OTP memory cell circuit of claim 6, wherein, The breakdown voltages of the first selection tube, the second selection tube, the first storage tube and the second storage tube are the same or different.

9. A data processing circuit, characterized by The differential OTP storage unit circuit comprises any one of claims 6-8.

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