A method and apparatus for configuration memory self-test in an FPGA

Abstract

The application provides a method and device for self-test of configuration memory in FPGA. The method comprises the following steps: firstly, locking the input of all multiplexers (MUX) in the FPGA to the same level; writing a first preset vector into the configuration memory based on a shift chain in parallel form; then, reading the configuration memory based on the shift chain to obtain first readout data; when the first readout data is consistent with the first preset vector, writing a second preset vector into the configuration memory based on the shift chain; reading the configuration memory based on the shift chain to obtain second readout data; when the second readout data is consistent with the second preset vector, determining that the configuration memory passes the test. In this way, the test path is parallelized, the test speed is accelerated, the input end of the MUX is fixed to the same level, and the short circuit problem is avoided. The distributed memory is automatically traversed and tested, the read and write vectors are not limited, and thus the test work is completed.

Description

Technical Field

[0001] This specification relates to the field of electronic technology, and more particularly to a method and apparatus for configuring memory self-test in an FPGA. Background Technology

[0002] Currently, Field Programmable Gate Array (FPGA) has emerged as a semi-custom circuit in the field of application-specific integrated circuits. It solves the shortcomings of custom circuits and overcomes the limitation of the limited number of gate circuits in the original programmable devices.

[0003] However, while current FPGAs have corresponding test circuits for various sub-modules such as Configurable Logic Blocks (CLBs), Digital Signal Processors (DSPs), and Embedded Systems (EMBs), they lack built-in self-test (BIST) circuits specifically for distributed configuration memory (cfgmem). This is because FPGAs contain many one-hot coded multiplexers (One-Hot MUXs), and the general BIST method would cause short circuits in the chip. Existing methods are time-consuming, and their costs increase exponentially with scale, resulting in high testing costs. Summary of the Invention

[0004] This invention describes a method and apparatus for configuring memory self-test in an FPGA, which can solve the above-mentioned technical problems.

[0005] According to the first aspect, a method for configuring memory self-test in an FPGA is provided. The method includes:

[0006] When the built-in self-test (BIST) signal of the FPGA is valid, the inputs of all multiplexers (MUX) in the FPGA are locked to the same level; a first preset vector is written into the configuration memory based on a parallel shift chain; the configuration memory is read based on the shift chain to obtain first read data; when the first read data and the first preset vector are consistent, a second preset vector is written into the configuration memory based on the shift chain; the configuration memory is read based on the shift chain to obtain second read data; when the second read data and the second preset vector are consistent, the configuration memory is determined to have passed the test.

[0007] In some embodiments, before the built-in self-test BIST signal of the FPGA is valid, the method further includes: configuring the configuration memory to a mode for actual use and initializing the configuration register.

[0008] In some embodiments, if the first read data and the first preset vector are inconsistent, it is determined that the configuration memory has failed the test.

[0009] In some embodiments, if the second read data and the second preset vector are inconsistent, it is determined that the configuration memory has failed the test.

[0010] In some embodiments, locking the inputs of all multiplexers (MUX) in the FPGA to the same level includes setting all signals input to the multiplexers (MUX) to a high or low level.

[0011] In some embodiments, the parallel-based shift chain is one of the following: a 4-shift shift chain, an 8-shift shift chain, or a 16-shift shift chain.

[0012] In some embodiments, all vector elements in the first preset vector are 1, and all vector elements in the second preset vector are 0.

[0013] According to a second aspect, an apparatus for configuring memory self-test in an FPGA is provided. The apparatus includes:

[0014] An input locking module is used to lock the inputs of all multiplexers (MUXs) in the FPGA to the same level when the BIST signal of the FPGA is valid; a first write module is used to write a first preset vector into the configuration memory based on a parallel shift chain; a first read module is used to read the configuration memory based on the shift chain to obtain first read data; a second write module is used to write a second preset vector into the configuration memory based on the shift chain when the first read data and the first preset vector are consistent; a second read module is used to read the configuration memory based on the shift chain to obtain second read data; and a test determination module is used to determine that the configuration memory passes the test when the second read data and the second preset vector are consistent.

[0015] In some embodiments, the test determination module is further configured to: determine that the configuration memory has failed the test when the first read data and the first preset vector are inconsistent.

[0016] In some embodiments, the test determination module is further configured to: determine that the configuration memory has failed the test when the second read data and the second preset vector are inconsistent.

[0017] In some embodiments, the parallel-based shift chain is one of the following: a 4-shift shift chain, an 8-shift shift chain, or a 16-shift shift chain.

[0018] In the methods and apparatus provided in the embodiments of this specification, the testing speed is accelerated by parallelizing the test paths. Using the self-test path automatically sets all signals input to the multiplexer (MUX) to the same level, avoiding short-circuit problems. Automatic traversal testing of the distributed memory is performed, with arbitrary read and write verifications to complete the testing. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This diagram illustrates a flowchart of a method for configuring memory self-test in an FPGA, as provided in an embodiment of this specification.

[0021] Figure 2 This diagram illustrates a configuration of memory in an FPGA distributed in a grid pattern across the entire chip, as provided in an embodiment of this specification.

[0022] Figure 3 This diagram illustrates a short circuit caused by an existing built-in self-test (BIST) method for configuring memory in an FPGA, as provided in an embodiment of this specification.

[0023] Figure 4 This diagram illustrates a parallel test path for a method of configuring memory self-test in an FPGA, as provided in an embodiment of this specification.

[0024] Figure 5 This diagram illustrates the structure of a device for configuring memory self-test in an FPGA, as provided in an embodiment of this specification. Detailed Implementation

[0025] The solution provided in this specification will now be described with reference to the accompanying drawings.

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings.

[0027] In the description of the embodiments of this application, the words "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the words "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a specific manner.

[0028] In the description of the embodiments of this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, B existing alone, and A and B existing simultaneously. Furthermore, unless otherwise stated, the term "multiple" means two or more.

[0029] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and their variations all mean "including but not limited to," unless otherwise specifically emphasized.

[0030] Figure 1 This document illustrates a flowchart of a method for configuring memory self-test in an FPGA, as provided in an embodiment of this specification. Figure 1 As shown, the method includes the following steps:

[0031] Step S100: Determine whether the FPGA's built-in self-test BIST enable signal is valid.

[0032] In some embodiments, before performing step S100, the method further includes: configuring the configuration memory in the FPGA to a mode for actual use and initializing the configuration register.

[0033] It should be understood that there are no restrictions on the type and implementation of the configured memory, nor on the process conditions. Figure 2 This diagram illustrates a configuration of memory in an FPGA distributed in a grid pattern across the entire chip, as provided in an embodiment of this specification.

[0034] Furthermore, if the BIST signal is determined to be invalid, the current process is terminated; otherwise, step S110 is executed.

[0035] Step S110: When the built-in self-test BIST signal of the FPGA is valid, lock the inputs of all multiplexers (MUX) in the FPGA to the same level.

[0036] In some embodiments, this step includes locking all signals input to the multiplexer MUX to a high or low level so that short circuits do not occur even if multiple channels are open. Figure 3 This diagram illustrates a short circuit caused by the existing built-in self-test (BIST) method for configuring memory in an FPGA, as provided in an embodiment of this specification. The following is in conjunction with... Figure 3 The following explanation is provided. The multiplexer (MUX) has four inputs: in1, in2, in3, and in4. These four selection control terminals are derived from the inputs of four configuration memory cells. The value of the configuration memory cell is used to select one of the four input lines as the valid input. In the existing built-in self-test (BIST) method, for example, in1, in2, in3, and in4, the inputs are (0, 1, 0, 0), and the selection control signal for the configuration memory (cfgmem) is (1, 1, 0, 0). The in1 and in2 paths are open, and under the influence of the selection control signal, the outputs are 0 and 1, causing a short circuit in the FPGA chip.

[0037] The method described in this application can avoid chip short circuits.

[0038] Step S120: Write a first preset vector into the configuration memory based on a parallel shift chain.

[0039] In some embodiments, this step includes setting the test path to a parallel configuration, changing the original 1-bit shift chain to a 4-bit shift chain. Figure 4 This diagram illustrates a parallel test path for a method of configuring memory self-testing in an FPGA, as provided in an embodiment of this specification. The input signal is connected to the input terminal of the memory cell through four parallel data lines, enabling simultaneous read and write operations on four memory cells.

[0040] In some more specific embodiments, the parallel form of the test path can also be implemented using 8-bit or 16-bit shift chains, and the number of parallel paths is not limited.

[0041] In some embodiments, this step includes: generating address information using an address generator, traversing all memory cells of the FPGA configuration memory, and performing write operations on all memory cells to write a first preset vector.

[0042] In some more specific embodiments, the first preset vector is all 1s, so all memory cells are written with 1s. Besides using an all-1s test vector, the first preset vector can also be a checkerboard test vector, meaning that a 1 is written to the first memory cell, a 0 to the second, a 1 to the third, and so on, until the last memory cell. This application does not limit the read / write vectors.

[0043] Step S130: Read the configuration memory based on the above-described parallel shift chain to obtain the first read data, and check whether the first read data and the first preset vector are consistent.

[0044] Furthermore, if the first read data and the first preset vector are found to be inconsistent, it is determined that the configuration memory has failed the test; otherwise, step S140 is executed.

[0045] In step S140, when the first read data matches the first preset vector, a second preset vector is written into the configuration memory based on the shift chain. It should be understood that the second preset vector is different from the first preset vector described above.

[0046] In some embodiments, if the second preset vector is all "0", then all memory cells of the FPGA configuration memory are written with 0.

[0047] In some more specific embodiments, if the second preset vector is all "1", then all memory cells of the FPGA configuration memory are written with 1.

[0048] Step S150: Read the configuration memory based on the above-described parallel shift chain to obtain the second read data, and verify whether the second read data is consistent with the second preset vector.

[0049] In step S160, when the second read data is consistent with the second preset vector, it is determined that the configuration memory has passed the test.

[0050] In some embodiments, the method further includes: determining that the configuration memory has failed the test when the second read data and the second preset vector are inconsistent.

[0051] Corresponding to the method provided by the present invention, the present invention also provides an apparatus. Figure 5 This diagram illustrates the structure of a device for configuring memory self-test in an FPGA, as provided in an embodiment of this specification. Figure 5 As shown, the device 500 includes:

[0052] The input locking module 510 is used to lock the inputs of all multiplexers (MUX) in the FPGA to the same level when the BIST signal of the FPGA is valid.

[0053] The first write module 520 is used to write a first preset vector into the configuration memory based on a parallel shift chain.

[0054] The first reading module 530 is used to read the configuration memory based on the shift chain to obtain the first read data.

[0055] The second writing module 540 is used to write a second preset vector into the configuration memory based on a shift chain when the first read data and the first preset vector are consistent.

[0056] The second reading module 550 is used to read the configuration memory based on the shift chain to obtain the second read data.

[0057] The test judgment module 560 is used to determine whether the configuration memory passes the test when the second read data is consistent with the second preset vector.

[0058] In some embodiments, the test determination module 560 is further configured to: determine that the configuration memory has failed the test when the first read data and the first preset vector are inconsistent.

[0059] In some embodiments, the test determination module 560 is further configured to: determine that the configuration memory has failed the test when the second read data and the second preset vector are inconsistent.

[0060] In some embodiments, the parallel shift chain is one of the following: a 4-shift shift chain, an 8-shift shift chain, or a 16-shift shift chain.

[0061] It needs to be explained that, for Figure 5 For a description of the apparatus, see also the description of the aforementioned method.

[0062] According to another embodiment, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed in a computer, causes the computer to perform a combination Figure 1 The method described.

[0063] According to another embodiment, a computing device is also provided, including a memory and a processor, wherein the memory stores executable code, and when the processor executes the executable code, it implements a combination... Figure 1 The methods described herein. Those skilled in the art will recognize that, in one or more of the examples above, the functions described in this invention can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium.

[0064] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for configuring memory self-test in an FPGA, characterized in that, The method includes: When the built-in self-test BIST signal of the FPGA is valid, the input terminals of all one-hot encoded multiplexers (MUX) in the FPGA are locked to the same level. A first preset vector is written into the configuration memory based on a parallel shift chain. The configuration memory is read based on the shift chain to obtain the first read data; When the first read data and the first preset vector are consistent, the second preset vector is written into the configuration memory based on the shift chain; The configuration memory is read based on the shift chain to obtain the second read data; When the second read data and the second preset vector are consistent, the configuration memory is determined to have passed the test.

2. The method according to claim 1, characterized in that, The method further includes: If the first read data and the first preset vector are inconsistent, the configuration memory is determined to have failed the test.

3. The method according to claim 1, characterized in that, The method further includes: If the second read data and the second preset vector are inconsistent, the configuration memory is determined to have failed the test.

4. The method according to claim 1, characterized in that, Locking the inputs of all multiplexers (MUX) in the FPGA to the same level includes: Set all signals input to the multiplexer MUX to either a high or low level.

5. The method according to claim 1, characterized in that, The parallel-based shift chain is one of the following: a 4-shift shift chain, an 8-shift shift chain, or a 16-shift shift chain.

6. The method according to claim 1, characterized in that, All vector elements in the first preset vector are 1, and all vector elements in the second preset vector are 0.

7. An apparatus for configuring memory self-test in an FPGA, characterized in that, The device includes: An input locking module is used to lock the input terminals of all one-hot encoded multiplexers (MUXs) in the FPGA to the same level when the BIST signal of the FPGA is valid. The first write module is used to write a first preset vector into the configuration memory based on a parallel shift chain; The first reading module is used to read the configuration memory based on the shift chain to obtain the first read data; The second writing module is used to write a second preset vector into the configuration memory based on the shift chain when the first read data and the first preset vector are consistent. The second reading module is used to read the configuration memory based on the shift chain to obtain the second read data; The test determination module is used to determine that the configuration memory passes the test when the second read data and the second preset vector are consistent.

8. The apparatus according to claim 7, characterized in that, The test determination module is also used for: If the first read data and the first preset vector are inconsistent, the configuration memory is determined to have failed the test.

9. The apparatus according to claim 7, characterized in that, The test determination module is also used for: If the second read data and the second preset vector are inconsistent, the configuration memory is determined to have failed the test.

10. The apparatus according to claim 7, characterized in that, The parallel-based shift chain is one of the following: a 4-shift shift chain, an 8-shift shift chain, or a 16-shift shift chain.

Images