Multilayer Ceramic Capacitors

Abstract

The present invention provides a laminated ceramic capacitor capable of suppressing electric field concentration at least at the end of an internal electrode and improving reliability. A second alloy portion is formed between a second dielectric ceramic layer and a first internal electrode layer and between a second dielectric ceramic layer and a second internal electrode layer, respectively, and the second alloy portion contains a metal element that is the most abundant among metal elements constituting the internal electrode layer and one or more metal elements in a metal group of Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, and Y.

Description

[0001] This application is a divisional application of the invention patent application with the application date of December 25, 2020, application number 202011572771.X, and invention name “Stacked Ceramic Capacitor”. Technical Field

[0002] The present invention relates to a laminated ceramic capacitor. Background Art

[0003] In recent years, multilayer ceramic electronic components such as multilayer ceramic capacitors have been sought to be miniaturized and have a higher capacitance. In order to achieve miniaturization and higher capacitance of multilayer ceramic capacitors, the following method is effective, that is, by thinning the side margins of each side of a stacked body having a plurality of dielectric ceramic layers and a plurality of internal electrode layers, thereby increasing the area of ​​the internal electrode layers facing each other.

[0004] Patent document 1 discloses a method for manufacturing an electronic component, comprising: a process of preparing a chip, the chip comprising a plurality of stacked dielectric ceramic layers and a plurality of internal electrode layers, with the plurality of internal electrode layers exposed on the side; a process of bonding a plurality of covering dielectric sheets to each other to form a dielectric laminate; and a process of adhering the dielectric laminate to the side of the chip.

[0005] In addition, Patent Document 2 discloses that when a multilayer ceramic capacitor is manufactured by stacking a plurality of ceramic green sheets printed with internal electrodes, pressurizing and firing them, a ceramic slurry for eliminating steps is applied to the areas where the internal electrodes are not printed, thereby preventing steps from being generated in the portions where the internal electrodes overlap and the portions where they do not overlap.

[0006] Prior Art Literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Publication No. 2017-147358

[0009] Patent Document 2: Japanese Patent Application Publication No. 2003-209025

[0010] However, in Reference 1, there is no particular mention of the composition of the ceramic dielectric sheet bonded to the side of the laminate. In addition, in Reference 2, there is no particular mention of the composition of the step-eliminating ceramic paste used. Therefore, in References 1 and 2, there is room for improving the reliability of the laminated ceramic capacitor by optimizing the composition of the dielectric laminate sheet and the step-eliminating ceramic paste.

[0011] Furthermore, at the end of the internal electrode close to the dielectric ceramic layer using the step-eliminating ceramic paste described in Reference 2, electric field concentration may occur, which may reduce reliability. Summary of the invention

[0012] Problems to be solved by the invention

[0013] An object of the present invention is to provide a multilayer ceramic capacitor capable of suppressing electric field concentration at least at the end portions of internal electrodes and improving reliability.

[0014] Technical solutions to solve problems

[0015] The multilayer ceramic capacitor of the present invention comprises: a multilayer body including dielectric ceramic layers and internal electrode layers stacked in a stacking direction; and an external electrode connected to the internal electrode layers. In the multilayer ceramic capacitor, the multilayer body has: a first main surface and a second main surface facing each other in the stacking direction; a first side surface and a second side surface facing each other in a width direction orthogonal to the stacking direction; and a first end surface and a second end surface facing each other in a length direction orthogonal to the stacking direction and the width direction. The internal electrode layers include: The invention comprises: a first internal electrode layer extending to the first end surface; and a second internal electrode layer extending to the second end surface so as to be opposite to the first internal electrode layer via the dielectric ceramic layer, the external electrode comprising: a first external electrode arranged on the first end surface and connected to the first internal electrode layer; and a second external electrode arranged on the second end surface and connected to the second internal electrode layer, the dielectric ceramic layer comprising a first dielectric ceramic layer and a second dielectric ceramic layer, the first dielectric ceramic layer being arranged on The second dielectric ceramic layer is arranged between the first internal electrode layer and the second internal electrode layer so as to include a region where the internal electrode layer is not arranged between the first dielectric ceramic layers opposed to each other via the internal electrode layer, and a portion of the second dielectric ceramic layer overlaps with the first dielectric ceramic layer in the stacking direction. The stacked body comprises: an inner layer portion in which the first internal electrode layer and the second internal electrode layer are alternately stacked via the dielectric ceramic layer; an outer layer portion arranged so as to sandwich the inner layer portion in the stacking direction and comprising a ceramic material; and a third dielectric ceramic layer arranged so as to sandwich the inner layer portion and the outer layer portion in the width direction and comprising a dielectric ceramic material. The third dielectric ceramic layer comprises a plurality of dielectric ceramic layers, including an inner layer arranged at the innermost side in the width direction of the stacked body and an outer layer arranged at the outermost side in the width direction of the stacked body, the inner layer containing at least one element among Si, Mg and Mn, and the content of the element is higher than that of the first dielectric ceramic layer and the second dielectric ceramic layer.

[0016] Effects of the Invention

[0017] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can suppress electric field concentration at least at the end portions of internal electrodes and improve reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 FIG. 1 is a perspective view schematically showing an example of a multilayer ceramic capacitor according to the present invention.

[0019] Figure 2 It schematically shows the structure Figure 1 The illustrated perspective view is an example of a laminated body of a laminated ceramic capacitor.

[0020] Figure 3 yes Figure 1 AA line cross-sectional view of the multilayer ceramic capacitor shown.

[0021] Figure 4 yes Figure 1 FIG. 1 is a cross-sectional view of a multilayer ceramic capacitor taken along line CC shown in FIG.

[0022] Figure 5 yes Figure 1 BB line cross-sectional view of the multilayer ceramic capacitor shown.

[0023] Figure 6 It is a plan view schematically showing an example of a ceramic green sheet.

[0024] Figure 7 It is a plan view schematically showing an example of a ceramic green sheet.

[0025] Figure 8 It is a plan view schematically showing an example of a ceramic green sheet.

[0026] Fig. 9 It is an exploded perspective view schematically showing an example of a mother block.

[0027] Fig.10 It is a perspective view schematically showing an example of a green chip.

[0028] Fig.11 This is a diagram schematically showing a portion of the LT cross section of the multilayer ceramic capacitor of the present invention, and a first alloy portion and a second alloy portion.

[0029] Fig.12 yes Fig.11 A magnified portion of the image.

[0030] Fig.13 It is a part of the LT cross section of the multilayer ceramic capacitor of the present invention, and is a diagram schematically showing the first diffused internal electrode, the second diffused internal electrode, and the fourth alloy portion.

[0031] Fig.14 It is a diagram schematically showing a part of the WT cross section of the multilayer ceramic capacitor of the present invention, and schematically showing the first alloy portion and the third alloy portion.

[0032] Fig.15 yes Fig.14 A partially enlarged view of is a diagram schematically showing the 5th alloy portion.

[0033] Fig.16 This is a cross-sectional view schematically showing the manner in which the end portion of the second dielectric ceramic layer overlaps the end portion of the internal electrode layer in the multilayer ceramic capacitor of the present invention.

[0034] Fig.17 This is a cross-sectional view schematically showing the manner in which the end portion of the second dielectric ceramic layer overlaps the end portion of the internal electrode layer in the multilayer ceramic capacitor of the present invention.

[0035] Fig.18 This is a diagram for explaining a TEM analysis method for analyzing the amount of metal elements contained in the internal electrode layers of the multilayer ceramic capacitor of the present invention.

[0036] Fig.19 yes Figure 5 A part of FIG. 1 is a diagram showing the vicinity of the intersection point of the present invention.

[0037] Fig. 20 It is a diagram for explaining a method of measuring the average particle diameter of dielectric particles included in the first dielectric ceramic layer and the third dielectric ceramic layer.

[0038] Fig.21 This is a diagram for explaining a method of measuring the average particle size of dielectric particles included in the third dielectric ceramic layer.

[0039] Fig. 22 This is a diagram for explaining the first stage of a method for measuring the average particle diameter of dielectric particles included in the second dielectric ceramic layer and the region near the intersection.

[0040] Fig.23 This is a diagram for explaining the second stage of the method of measuring the average particle diameter of dielectric particles included in the second dielectric ceramic layer and the region near the intersection.

[0041] Fig.24 This is a diagram for explaining a method of measuring the average particle size of dielectric particles included in the region near the intersection.

[0042] Fig.25This is a diagram schematically showing a step of removing the side surface of an unfired laminated body in the method for producing a laminated ceramic capacitor of the present invention.

[0043] Fig.26 This is a view showing an end surface of an unfired laminated body from which side surfaces have been removed in the method for producing a laminated ceramic capacitor of the present invention.

[0044] Fig. 27 This is a cross-sectional view schematically showing the manner in which the end portion of the second dielectric ceramic layer overlaps the end portion of the internal electrode layer in the method for manufacturing the multilayer ceramic capacitor of the present invention.

[0045] Fig.28 It is a part of the WT cross section of the multilayer ceramic capacitor of the present invention, and is a diagram schematically showing a defective portion of the second dielectric ceramic layer.

[0046] Fig.29 yes Fig.28 KK line cross-sectional view.

[0047] Fig.30 It is a part of the LT cross section of the multilayer ceramic capacitor of the present invention, and is a diagram schematically showing the first segregation.

[0048] Fig.31 yes Fig.30 A magnified portion of the image.

[0049] Fig.32 It is a part of the WT cross section of the multilayer ceramic capacitor of the present invention and is a diagram schematically showing the second segregation.

[0050] Fig.33 It is a part of the LW cross section of the multilayer ceramic capacitor of the present invention, and is a diagram showing the third segregation segregating to the first corner region and the second corner region.

[0051] Fig.34 It is a cross-sectional view schematically showing the manner in which the end portion of the second dielectric ceramic layer overlaps the third segregation in the multilayer ceramic capacitor of the present invention.

[0052] Fig.35 This is a diagram showing the thickness of the first dielectric ceramic layer at the center portion in the length (L) direction of the multilayer ceramic capacitor of the present invention.

[0053] Fig.36 This is a diagram showing the thickness of the second dielectric ceramic layer of the multilayer ceramic capacitor of the present invention.

[0054] Description of Reference Numerals

[0055] 1: Multilayer ceramic capacitor;

[0056] 10: laminate;

[0057] 11: first main surface of the laminate;

[0058] 12: second main surface of the laminate;

[0059] 13: first side of the laminate;

[0060] 14: The second side of the laminate;

[0061] 15: first end surface of the stack;

[0062] 16: the second end surface of the stack;

[0063] 20: dielectric ceramic layer;

[0064] 20a: first dielectric ceramic layer;

[0065] 20b: second dielectric ceramic layer;

[0066] 21: 1st internal electrode layer;

[0067] 22: second internal electrode layer;

[0068] 30: inner layer;

[0069] 31, 32: outer layer;

[0070] 41, 42: third dielectric ceramic layer;

[0071] 51: 1st external electrode;

[0072] 52: second external electrode;

[0073] 210: 1st distributed internal electrode;

[0074] 220: 2nd distributed internal electrode;

[0075] 310: 1st Alloy Department;

[0076] 320: 2nd Alloy Department;

[0077] 330: 3rd Alloy Department;

[0078] 340: 4th Alloy Department;

[0079] 350: 5th Alloy Division. DETAILED DESCRIPTION

[0080] Hereinafter, the multilayer ceramic capacitor of the present invention will be described.

[0081] However, the present invention is not limited to the following configurations, and can be applied with appropriate changes within the scope of the present invention. In addition, a configuration combining two or more of the preferred configurations described below is also the present invention.

[0082] [Multilayer Ceramic Capacitors]

[0083] Figure 1 FIG. 1 is a perspective view schematically showing an example of a multilayer ceramic capacitor according to the present invention. Figure 2 It schematically shows the structure Figure 1 The illustrated perspective view is an example of a laminated body of a laminated ceramic capacitor. Figure 3 yes Figure 1 AA line cross-sectional view of the multilayer ceramic capacitor shown. Figure 4 yes Figure 1 FIG. 1 is a cross-sectional view of a multilayer ceramic capacitor taken along line CC shown in FIG.

[0084] In this specification, the stacking direction, width direction, and length direction of a multilayer ceramic capacitor and a multilayer body are defined as Figure 1 The multilayer ceramic capacitor 1 shown and Figure 2 In the stacked body 10 shown, directions are indicated by arrows T, W, and L. Here, the stacking (T) direction, the width (W) direction, and the length (L) direction are orthogonal to each other. The stacking (T) direction is the direction in which the plurality of dielectric ceramic layers 20 and the plurality of pairs of first internal electrode layers 21 and second internal electrode layers 22 are stacked.

[0085] Figure 1 The illustrated multilayer ceramic capacitor 1 includes a multilayer body 10 , and a first external electrode 51 and a second external electrode 52 provided on both end surfaces of the multilayer body 10 , respectively.

[0086] like Figure 2 As shown, the stack 10 is in the shape of a rectangle or a substantially rectangle, having a first main surface 11 and a second main surface 12 opposite to each other in the stacking (T) direction, a first side surface 13 and a second side surface 14 opposite to each other in the width (W) direction orthogonal to the stacking (T) direction, and a first end surface 15 and a second end surface 16 opposite to each other in the length (L) direction orthogonal to the stacking (T) direction and the width (W) direction.

[0087] In this specification, the cross section of the multilayer ceramic capacitor 1 or the multilayer body 10 that is orthogonal to the first end face 15 and the second end face 16 and parallel to the stacking (T) direction is referred to as a cross section in the length (L) direction and the stacking (T) direction, that is, a LT cross section. In addition, the cross section of the multilayer ceramic capacitor 1 or the multilayer body 10 that is orthogonal to the first side face 13 and the second side face 14 and parallel to the stacking (T) direction is referred to as a cross section in the width (W) direction and the stacking (T) direction, that is, a WT cross section. In addition, the cross section of the multilayer ceramic capacitor 1 or the multilayer body 10 that is orthogonal to the first side face 13, the second side face 14, the first end face 15, and the second end face 16 and perpendicular to the stacking (T) direction is referred to as a cross section in the length (L) direction and the width (W) direction, that is, a LW cross section. Therefore, Figure 3 is the LT cross section of the multilayer ceramic capacitor 1, Figure 4 WT is a cross section of the multilayer ceramic capacitor 1 .

[0088] The laminate 10 preferably has rounded corners and ridges. A corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect.

[0089] like Figure 2 , Figure 3 as well as Figure 4 As shown, the laminated body 10 has a laminated structure including a plurality of dielectric ceramic layers 20 laminated in a laminated (T) direction and a plurality of pairs of first internal electrode layers 21 and second internal electrode layers 22 formed along interfaces between the dielectric ceramic layers 20. The dielectric ceramic layers 20 extend in a width (W) direction and a length (L) direction, and the first internal electrode layers 21 and the second internal electrode layers 22 each extend in a flat plate shape along the dielectric ceramic layers 20.

[0090] The first internal electrode layer 21 is led out to the first end surface 15 of the laminate 10 . On the other hand, the second internal electrode layer 22 is led out to the second end surface 16 of the laminate 10 .

[0091] The first internal electrode layer 21 and the second internal electrode layer 22 face each other in the stacking (T) direction via the dielectric ceramic layer 20. Electrostatic capacitance is generated at the portion where the first internal electrode layer 21 and the second internal electrode layer 22 face each other via the dielectric ceramic layer 20.

[0092] The first internal electrode layer 21 and the second internal electrode layer 22 each preferably include a metal such as Ni, Cu, Ag, Pd, Ag-Pd alloy, Au, etc. The first internal electrode layer 21 and the second internal electrode layer 22 each may include the same dielectric ceramic material as the dielectric ceramic layer 20 in addition to the above metals.

[0093] The dielectric ceramic layer 20 includes a first dielectric ceramic layer 20 a and a second dielectric ceramic layer 20 b .

[0094] The first dielectric ceramic layer 20 a is a dielectric ceramic layer disposed between the first internal electrode layer 21 and the second internal electrode layer 22 .

[0095] The second dielectric ceramic layer 20b is a dielectric ceramic layer disposed in a region where the internal electrode layers (21, 22) are not disposed between the first dielectric ceramic layers 20a that are opposed to each other with the internal electrode layers (21, 22) interposed therebetween.

[0096] The first external electrode 51 is provided on the first end surface 15 of the stacked body 10. Figure 1 The first external electrode 51 has a portion that wraps around a portion of each of the first main surface 11 , the second main surface 12 , the first side surface 13 , and the second side surface 14 . The first external electrode 51 is connected to the first internal electrode layer 21 at the first end surface 15 .

[0097] The second external electrode 52 is provided on the second end surface 16 of the stacked body 10. Figure 1 The second outer electrode 52 has a portion that wraps around a portion of each of the first main surface 11 , the second main surface 12 , the first side surface 13 , and the second side surface 14 . The second outer electrode 52 is connected to the second inner electrode layer 22 at the second end surface 16 .

[0098] The first external electrode 51 and the second external electrode 52 preferably include a Ni layer containing Ni and a ceramic material. The Ni layer is a base electrode layer. Such a Ni layer can be formed by a so-called co-firing method in which the Ni layer is fired simultaneously with the first internal electrode layer 21 and the second internal electrode layer 22. The Ni layer is preferably directly disposed on the stacked body 10.

[0099] The first external electrode 51 preferably includes a Ni layer, a first plating layer, and a second plating layer in order from the first end face 15 side of the stacked body 10. Similarly, the second external electrode 52 preferably includes a Ni layer, a first plating layer, and a second plating layer in order from the second end face 16 side of the stacked body 10. The first plating layer is preferably formed by Ni plating, and the second plating layer is preferably formed by Sn plating. The first external electrode 51 and the second external electrode 52 may each include a conductive resin layer containing conductive particles and a resin between the Ni layer and the first plating layer. As the conductive particles in the conductive resin layer, for example, metal particles such as Cu, Ag, and Ni can be listed.

[0100] Alternatively, the Ni layer may be formed by a so-called post-firing method in which a conductive paste is applied to the end surface of the fired laminate and then fired. In this case, the Ni layer may not contain a ceramic material.

[0101] Alternatively, the first external electrode 51 and the second external electrode 52 may each include a base electrode layer containing a metal such as Cu. The base electrode layer may be formed by a co-firing method or a post-firing method. In addition, the base electrode layer may be a plurality of layers.

[0102] For example, the first external electrode 51 may also have a four-layer structure, which includes a Cu layer as a base electrode layer, a conductive resin layer containing conductive particles and a resin, a first plating layer, and a second plating layer in order from the first end face 15 side of the stacked body 10. Similarly, the second external electrode 52 may also have a four-layer structure, which includes a Cu layer as a base electrode layer, a conductive resin layer containing conductive particles and a resin, a first plating layer, and a second plating layer in order from the second end face 16 side of the stacked body 10.

[0103] like Figure 3 as well as Figure 4 As shown, the dielectric ceramic layer 20 includes a first dielectric ceramic layer 20 a and a second dielectric ceramic layer 20 b .

[0104] The first dielectric ceramic layer 20 a is arranged between the first internal electrode layer 21 and the second internal electrode layer 22 .

[0105] The second dielectric ceramic layer 20 b is disposed in a region where no internal electrode layer is disposed between the first dielectric ceramic layers 20 a that are opposed to each other with the internal electrode layer interposed therebetween.

[0106] like Figure 2 , Figure 3 as well as Figure 4 As shown, the laminate 10 includes: an inner layer portion 30, a first internal electrode layer 21 and a second internal electrode layer 22 facing each other via a dielectric ceramic layer 20; outer layer portions 31 and 32 arranged to sandwich the inner layer portion 30 in a stacking (T) direction; and third dielectric ceramic layers 41 and 42 arranged to sandwich the inner layer portion 30, the outer layer portion 31, and the outer layer portion 32 in a width (W) direction. The third dielectric ceramic layers 41 and 42 are also referred to as lateral margin portions.

[0107] exist Figure 3 as well as Figure 4 In the figure, the inner layer portion 30 is a region sandwiched by the first internal electrode layer 21 closest to the first main surface 11 and the first internal electrode layer 21 closest to the second main surface 12 along the stacking (T) direction. Although not shown in the figure, the outer layer portion 31 and the outer layer portion 32 each preferably include a plurality of dielectric ceramic layers 20 stacked in the stacking (T) direction, and more preferably include the first dielectric ceramic layer 20a.

[0108] The thickness of each of the outer layer portions 31 and 32 is preferably 15 μm or more and 40 μm or less. In addition, each of the outer layer portions 31 and 32 may have a single layer structure instead of a multilayer structure.

[0109] like Figure 4 As shown, each of the third dielectric ceramic layer 41 and the third dielectric ceramic layer 42 may include a plurality of dielectric ceramic layers stacked in the width (W) direction.

[0110] Among the plurality of dielectric ceramic layers constituting the third dielectric ceramic layer, the innermost layer in the width direction is referred to as an inner layer, and the outermost layer is referred to as an outer layer. An interface exists between the inner layer and the outer layer.

[0111] exist Figure 4 , the third dielectric ceramic layer 41 has a two-layer structure including an inner layer 41a disposed at the innermost side of the stack 10 and an outer layer 41b disposed at the outermost side of the stack 10. Similarly, the third dielectric ceramic layer 42 has a two-layer structure including an inner layer 42a disposed at the innermost side of the stack 10 and an outer layer 42b disposed at the outermost side of the stack 10 as the dielectric ceramic layer.

[0112] In addition, the third dielectric ceramic layer is not limited to a two-layer structure, but may be a structure of more than three layers. When the third dielectric ceramic layer includes more than three dielectric ceramic layers, the innermost dielectric ceramic layer arranged in the width direction is set as the inner layer, and the outermost dielectric ceramic layer arranged in the width direction is set as the outer layer.

[0113] Furthermore, the number of dielectric ceramic layers may be different between the third dielectric ceramic layer on the first side surface and the third dielectric ceramic layer on the second side surface of the laminate.

[0114] When the third dielectric ceramic layer is a two-layer structure including an inner layer and an outer layer, the two-layer structure can be confirmed and the interface between the layers can be confirmed by observing in a dark field using an optical microscope based on the difference in sinterability between the inner layer and the outer layer. The same is true when the third dielectric ceramic layer is a structure of three or more layers.

[0115] The first dielectric ceramic layer 20a, the second dielectric ceramic layer 20b, and the third dielectric ceramic layers 41 and 42 include a dielectric ceramic material mainly composed of BaTiO3, etc. The dielectric ceramic layer 20 constituting the inner layer portion 30 may further contain a sintering aid element.

[0116] The dielectric ceramic layers constituting the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer may include ceramic grains. The details of the diameter of the ceramic grains will be described later.

[0117] In the multilayer ceramic capacitor of the present invention, the composition of at least one of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer is different from the composition of the other dielectric ceramic layers.

[0118] The first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer have different properties required in terms of the purpose of configuration and the manufacturing method. Therefore, by making the composition of at least one of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer different from the composition of the other dielectric ceramic layers, it is possible to achieve an optimal composition corresponding to the location where the dielectric ceramic layer is configured, thereby improving reliability.

[0119] In the multilayer ceramic capacitor of the present invention, the composition of the first dielectric ceramic layer may be different from the composition of the second dielectric ceramic layer and the composition of the third dielectric ceramic layer, the composition of the second dielectric ceramic layer may be different from the composition of the first dielectric ceramic layer and the composition of the third dielectric ceramic layer may be different from the composition of the first dielectric ceramic layer and the second dielectric ceramic layer, or the compositions of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer may be different from each other.

[0120] In the multilayer ceramic capacitor of the present invention, the second dielectric ceramic layer and the third dielectric ceramic layer preferably have different compositions, and more preferably all of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer have different compositions.

[0121] Furthermore, when the third dielectric ceramic layer includes a plurality of dielectric ceramic layers, the plurality of dielectric ceramic layers constituting the third dielectric ceramic layer may have the same composition or different compositions.

[0122] When the composition of any one of the plurality of dielectric ceramic layers constituting the third dielectric ceramic layer is different from that of the first dielectric ceramic layer, it can be said that the composition of the third dielectric ceramic layer is different from that of the first dielectric ceramic layer.

[0123] Furthermore, when the composition of any one of the plurality of dielectric ceramic layers constituting the third dielectric ceramic layer is different from that of the second dielectric ceramic layer, it can be said that the composition of the third dielectric ceramic layer is different from that of the second dielectric ceramic layer.

[0124] It is preferable that the dielectric ceramic layers having different compositions among the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer have the same main component but different kinds of additives.

[0125] As the main component, BaTiO3, CaTiO3, or SrTiO3 can be mentioned. The additive preferably contains elements such as Si, Mg, Mn, Sn, Cu, rare earths, Ni, and Al.

[0126] The first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer may contain two or more of the above elements.

[0127] The term “same composition” means that the types of elements contained in the dielectric ceramic constituting each dielectric ceramic layer are the same and the contents (molar ratios) of other elements based on Ti are all within ±0.5%.

[0128] In addition, it is assumed that the difference in diameter of the ceramic particles constituting each dielectric ceramic layer and the difference in porosity are not included in the difference in composition of the dielectric ceramic layer.

[0129] The composition of each dielectric ceramic layer can be determined by performing elemental analysis based on wavelength dispersive X-ray analysis (WDX) or transmission electron microscope-energy dispersive X-ray analysis (TEM-EDX) on the cut surface where the laminated ceramic capacitor is cut to expose the dielectric ceramic layer. In this case, the composition of each dielectric ceramic layer is measured at 5 locations and the average value is obtained.

[0130] The second dielectric ceramic layer was measured at five locations on the second dielectric ceramic layer exposed at the first end surface of the laminate and at five locations on the second dielectric ceramic layer exposed at the second end surface of the laminate, and the average value was taken.

[0131] When the third dielectric ceramic layer has a multilayer structure, the composition of each layer measured at five locations is determined to be the sum of the compositions obtained by multiplying the ratio of the thickness of each layer in the third dielectric ceramic layer.

[0132] In addition, when segregation of elements is observed near the interface with other dielectric ceramic layers or internal electrode layers, the portion where segregation of elements is observed is not used as a measurement target of WDX.

[0133] As an element added to the first dielectric ceramic layer, Mg is preferable.

[0134] The content of Mg in the first dielectric ceramic layer is preferably 0.05 mol% or more and 3.0 mol% or less relative to 100 mol of Ti.

[0135] It is more preferable that the content of Mg in the first dielectric ceramic layer is lower than the content of Mg in the second dielectric ceramic layer and the third dielectric ceramic layer.

[0136] When the Mg content in the first dielectric ceramic layer is low, the relative dielectric constant of the first dielectric ceramic layer increases, thereby increasing the capacitance of the multilayer ceramic capacitor. In some cases, it is preferable that the Mg content in the first dielectric ceramic layer is extremely low.

[0137] As an element added to the second dielectric ceramic layer, Sn is preferable.

[0138] The content of Sn in the second dielectric ceramic layer is preferably 0.05 mol% or more and 3.0 mol% or less relative to 100 mol of Ti.

[0139] The content of Sn in the second dielectric ceramic layer is preferably higher than the content of Sn in the first dielectric ceramic layer and the third dielectric ceramic layer.

[0140] As an element added to the third dielectric ceramic layer, Si is preferable.

[0141] The content of Si in the third dielectric ceramic layer is preferably 0.05 mol% or more and 5.0 mol% or less relative to 100 mol of Ti.

[0142] The Si content in the third dielectric ceramic layer is preferably higher than the Si content in the first dielectric ceramic layer and the second dielectric ceramic layer.

[0143] When the Si content in the third dielectric ceramic layer is high, the sinterability of the dielectric ceramic layer is improved, so that it is possible to suppress moisture and the like from penetrating from the first side surface and the second side surface of the laminate and deteriorating the internal electrode layer.

[0144] As an element added to the third dielectric ceramic layer, Mg is preferable.

[0145] The content of Mg in the third dielectric ceramic layer is preferably 0.05 mol% or more and 5.0 mol% or less relative to 100 mol of Ti.

[0146] The content of Mg in the third dielectric ceramic layer is preferably higher than the content of Mg in the first dielectric ceramic layer and the second dielectric ceramic layer.

[0147] When the content of Mg in the third dielectric ceramic layer is high, the grain growth of ceramic particles included in the third dielectric ceramic layer can be suppressed, and short circuits between internal electrode layers can be made less likely to occur.

[0148] As an element added to the third dielectric ceramic layer, Mn is preferable.

[0149] The content of Mn in the third dielectric ceramic layer is preferably 0.01 mol% or more and 3.0 mol% or less relative to 100 mol of Ti.

[0150] The content of Mn in the third dielectric ceramic layer is preferably higher than the content of Mn in the first dielectric ceramic layer and the second dielectric ceramic layer.

[0151] When the content of Mn in the third dielectric ceramic layer is high, the grain growth of ceramic particles contained in the third dielectric ceramic layer can be suppressed, and short circuits between internal electrode layers can be made less likely to occur.

[0152] In the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer, it is preferred that an element other than the main component contained in each dielectric ceramic layer diffuses into the other dielectric ceramic layers.

[0153] Furthermore, it is preferable that a part of the elements contained as additives in the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer diffuse into other adjacent dielectric ceramic layers and the internal electrode layer.

[0154] Figure 5 yes Figure 1 BB line cross-sectional view of the multilayer ceramic capacitor shown.

[0155] in addition, Figure 5 1 is a LW cross section of the multilayer ceramic capacitor 1 .

[0156] like Figure 5 As shown, the second internal electrode layer 22 is exposed at the second end face 16 of the laminate 10, and the second dielectric ceramic layer 20b is exposed at the first end face 15 of the laminate 10. In addition, the third dielectric ceramic layer 41 and the third dielectric ceramic layer 42 are arranged on the first side face 13 and the second side face 14 of the laminate 10, respectively.

[0157] like Figure 5 As shown, there is an interface 2220b between the second internal electrode layer 22 and the second dielectric ceramic layer 20b. In addition, there are interfaces 2241 and 2242 between the second internal electrode layer 22 and the third dielectric ceramic layers 41 and 42. Furthermore, there are interfaces 20b41 and 20b42 between the second dielectric ceramic layer 20b and the third dielectric ceramic layers 41 and 42.

[0158] In addition, although Figure 5Although not shown in the figure, the first dielectric ceramic layer 20a is arranged on both sides of the second internal electrode layer 22 and the second dielectric ceramic layer 20b in the thickness direction. Therefore, it can be said that the first dielectric ceramic layer 20a has an interface that is in direct contact with the second dielectric ceramic layer 20b, the third dielectric ceramic layers 41, 42, and the internal electrode layers 21, 22.

[0159] Furthermore, the first internal electrode layer 21 is also Figure 5 The second internal electrode layer 22 shown similarly has interfaces with the first dielectric ceramic layer 20 a , the second dielectric ceramic layer 20 b , and the third dielectric ceramic layers 41 and 42 .

[0160] The element derived from the second dielectric ceramic layer 20b may be segregated near the interface between the first dielectric ceramic layer 20a and the second dielectric ceramic layer 20b. In addition, the element derived from the third dielectric ceramic layer 41 or 42 may be segregated near the interface between the first dielectric ceramic layer 20a and the third dielectric ceramic layer 41 or 42.

[0161] The element derived from the first dielectric ceramic layer 20a may be segregated near the interface between the second dielectric ceramic layer 20b and the first dielectric ceramic layer 20a. In addition, the element derived from the third dielectric ceramic layer 41 or 42 may be segregated near the interface 20b41 or 20b42 between the second dielectric ceramic layer 20b and the third dielectric ceramic layer 41 or 42.

[0162] The element derived from the first dielectric ceramic layer 20a may be segregated near the interface between the third dielectric ceramic layers 41 and 42 and the first dielectric ceramic layer 20a. In addition, the element derived from the second dielectric ceramic layer 20b may be segregated near the interface 20b41 and 20b42 between the third dielectric ceramic layers 41 and 42 and the second dielectric ceramic layer 20b.

[0163] The element derived from the first dielectric ceramic layer 20a may be segregated near the interface between the first internal electrode layer 21 and the second internal electrode layer 22 and the first dielectric ceramic layer 20a. Furthermore, the element derived from the second dielectric ceramic layer 20b may be segregated near the interface 2220b between the first internal electrode layer 21 and the second internal electrode layer 22 and the second dielectric ceramic layer 20b. Furthermore, the element derived from the third dielectric ceramic layers 41 and 42 may be segregated near the interface 2241 and 2242 between the first internal electrode layer 21 and the second internal electrode layer 22 and the third dielectric ceramic layers 41 and 42.

[0164] In addition, both elements originating from the second dielectric ceramic layer 20b and elements originating from the third dielectric ceramic layer 41 or 42 may be segregated near the portion where the interface 2220b between the second internal electrode layer 22 and the second dielectric ceramic layer 20b and the interface 2241 or 2242 between the second internal electrode layer 22 and the third dielectric ceramic layer 41 or 42 are connected (the corner portion on the side of the first end face 15 of the second internal electrode layer 22).

[0165] The porosity of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer may be the same, or may be different from each other.

[0166] The cross-section of the laminated ceramic capacitor exposed by cutting it was observed with a scanning electron microscope (SEM) at 20,000 times. An area with a field size of 6.3 μm × 4.4 μm was photographed at 5 locations so that the areas did not overlap with each other. Based on each SEM image obtained, the ratio of the area occupied by the voids to the entire field of view was calculated by image analysis as the porosity, and the average value in the 5 fields of view was calculated. However, in the case where the third dielectric ceramic layer includes multiple layers, the porosity of each layer is calculated separately, and then the sum of the product of the value obtained by dividing the thickness of the layer by the thickness of the third dielectric ceramic layer and the porosity of each layer is taken as the porosity of the third dielectric ceramic layer.

[0167] The first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer preferably contain ceramic particles.

[0168] When the dielectric ceramic layer includes ceramic particles, interface resistance is generated at the interface between the ceramic particles, and the insulation resistance between the internal electrode layers can be increased, thereby preventing the occurrence of a short circuit.

[0169] It is preferred that the rare earth elements exist at the interface of the ceramic particles.

[0170] The presence of rare earths at the interface of the ceramic particles can be confirmed by elemental analysis based on TEM-EDX. Examples of rare earths include La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and Y.

[0171] The presence of rare earths at the interface of the ceramic particles can further increase the interface resistance of the dielectric ceramic layer, thereby further improving the reliability of the laminated ceramic capacitor. Mg, Mn, Si, etc. may also be present.

[0172] The rare earth element is preferably present in an amount of 0.2 mol% to 5 mol% based on 100 mol of Ti.

[0173] The 100 mol of Ti mentioned here is determined by the amount of rare earth elements present relative to 100 mol of Ti, assuming that the dielectric ceramic material constituting the dielectric ceramic layer contains a compound having a perovskite structure (structure represented by ABO3, B=Ti) as a main component.

[0174] The amount of rare earth elements present can be confirmed by TEM-EDX.

[0175] In the multilayer ceramic capacitor, the thickness of each of the first internal electrode layer and the second internal electrode layer is preferably 0.4 μm or less.

[0176] Furthermore, it is preferred that the thickness of each of the first internal electrode layer and the second internal electrode layer is 0.38 μm or less.

[0177] Furthermore, it is preferred that the thickness of each of the first internal electrode layer and the second internal electrode layer is 0.25 μm or more.

[0178] The thickness of the first dielectric ceramic layer is preferably 0.55 μm or less.

[0179] Furthermore, the thickness of each of the first dielectric ceramic layers is preferably 0.4 μm or more.

[0180] The thickness of the second dielectric ceramic layer is preferably the same as the thickness of the internal electrode layer.

[0181] The thickness of each of the third dielectric ceramic layers 41 and 42 is preferably 5 μm or more and 40 μm or less, and more preferably 5 μm or more and 20 μm or less. The thicknesses of the third dielectric ceramic layers 41 and 42 are preferably the same as each other. However, it is preferred that the inner layer 41a and the outer layer 41b satisfy the above range and the outer layer 41b is thicker than the inner layer 41a. Similarly, it is preferred that the inner layer 42a and the outer layer 42b satisfy the above range and the outer layer 42b is thicker than the inner layer 42a.

[0182] In order to maintain the shape and performance of the multilayer ceramic capacitor 1, the inner layer 41a is preferably thinner than the outer layer 41b. Similarly, the inner layer 42a is preferably thinner than the outer layer 42b.

[0183] The thickness of each of the inner layers 41a and 42a is preferably 0.1 μm or more and 20 μm or less. The thicknesses of the inner layers 41a and 42a are preferably the same as each other.

[0184] The thickness of each of the outer layers 41 b and 42 b is preferably 5 μm or more and 20 μm or less. The thicknesses of the outer layers 41 b and 42 b are preferably the same as each other.

[0185] The thickness of each ceramic layer in the side margin portion means an average value obtained by measuring the thickness of the third dielectric ceramic layer at a plurality of locations along the stacking (T) direction.

[0186] [Method for manufacturing multilayer ceramic capacitor]

[0187] Preferably, the manufacturing method of the laminated ceramic capacitor of the present invention comprises: a step of preparing a green chip having a laminated structure including a plurality of first dielectric ceramic layers and a plurality of second dielectric ceramic layers in an unfired state and a plurality of pairs of first internal electrode layers and second internal electrode layers, wherein the first internal electrode layers and the second internal electrode layers are exposed on a first side surface and a second side surface, and the first side surface and the second side surface are opposite to each other in a width direction orthogonal to the stacking direction; a step of forming an unfired third dielectric ceramic layer on the first side surface and the second side surface of the green chip to thereby produce an unfired laminated body; and a step of firing the unfired laminated body In the process of preparing the above-mentioned green chip, ceramic green sheets are stacked, and the above-mentioned ceramic green sheets are obtained by forming an unfired first internal electrode layer or a second internal electrode layer on the surface of an unfired first dielectric ceramic layer and forming an unfired second dielectric ceramic layer in a region where the first internal electrode layer and the second internal electrode layer are not provided. In the process of manufacturing the above-mentioned unfired laminated body, the above-mentioned unfired side margin portion is formed by forming an unfired inner layer on the above-mentioned first side surface and the above-mentioned second side surface and forming an unfired outer layer on the outermost side, and at least one of the above-mentioned first dielectric ceramic layer, the above-mentioned second dielectric ceramic layer and the above-mentioned third dielectric ceramic layer has a different composition.

[0188] The following, Figure 1 An example of a method for manufacturing the multilayer ceramic capacitor 1 shown will be described.

[0189] First, a ceramic green sheet to be the first dielectric ceramic layer 20a, the second dielectric ceramic layer 20b, and the third dielectric ceramic layer 41, 42 is prepared. In the ceramic green sheet, in addition to the ceramic raw material containing the above-mentioned dielectric ceramic material, a binder and a solvent are also contained. In addition, an additive containing rare earths can also be added to the ceramic raw material. By changing the elements contained in the additive, the composition of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer can be changed. The ceramic raw materials as the main components are preferably the same.

[0190] The ceramic green sheet is molded on a carrier film using, for example, a die coater, a gravure coater, a micro gravure coater, or the like.

[0191] Figure 6 , Figure 7 as well as Figure 8 FIG. 1 is a top view schematically showing an example of a ceramic green sheet. Figure 6 , Figure 7 as well as Figure 8 1 and 2 respectively show a first ceramic green sheet 101 for forming the inner layer portion 30 , a second ceramic green sheet 102 for forming the inner layer portion 30 , and a third ceramic green sheet 103 for forming the outer layer portion 31 or 32 .

[0192] exist Figure 6 , Figure 7 as well as Figure 8 In the embodiment, the first ceramic green sheet 101, the second ceramic green sheet 102, and the third ceramic green sheet 103 are not divided for each multilayer ceramic capacitor 1. Figure 6 , Figure 7 as well as Figure 8 2 shows cutting lines X and Y when cutting each multilayer ceramic capacitor 1. The cutting line X is parallel to the length (L) direction, and the cutting line Y is parallel to the width (W) direction.

[0193] like Figure 6 As shown, in the first ceramic green sheet 101, an unfired first internal electrode layer 121 corresponding to the first internal electrode layer 21 is formed on the unfired first dielectric ceramic layer 120a corresponding to the first dielectric ceramic layer 20a. In addition, an unfired second dielectric ceramic layer 120b corresponding to the second dielectric ceramic layer 20b is formed in a region where the unfired first internal electrode layer 121 is not formed.

[0194] The unfired first dielectric ceramic layer 120 a and the unfired second dielectric ceramic layer 120 b are also unfired dielectric ceramic layers 120 corresponding to the dielectric ceramic layer 20 .

[0195] like Figure 7 As shown, in the second ceramic green sheet 102, an unfired second internal electrode layer 122 corresponding to the second internal electrode layer 22 is formed on the unfired first dielectric ceramic layer 120a corresponding to the first dielectric ceramic layer 20a. In addition, an unfired second dielectric ceramic layer 120b corresponding to the second dielectric ceramic layer 20b is formed in a region where the unfired second internal electrode layer 122 is not formed.

[0196] The unfired first dielectric ceramic layer 120 a and the unfired second dielectric ceramic layer 120 b are also unfired dielectric ceramic layers 120 corresponding to the dielectric ceramic layer 20 .

[0197] Production Figure 6 The first ceramic green sheet 101 and Figure 7The method for forming the second ceramic green sheet shown is not particularly limited, and the following method can be cited, namely, on the surface of the unfired first dielectric ceramic layer 120a, a dielectric paste as a mixture of dielectric ceramic and solvent is applied in given areas to form the second dielectric ceramic layer 20b by firing, and a conductive paste is applied to form the internal electrode layer 21 or 22 by firing.

[0198] The order of applying the dielectric paste and the conductive paste is not particularly limited, and the dielectric paste may be applied first and then the conductive paste, or the conductive paste may be applied first and then the dielectric paste.

[0199] Alternatively, the dielectric paste and the conductive paste may be applied so that a portion of the paste applied later covers a portion of the surface of the paste applied earlier.

[0200] like Figure 8 As shown, the third ceramic green sheet 103 corresponding to the outer layer portion 31 or 32 includes an unfired first dielectric ceramic layer 120a corresponding to the first dielectric ceramic layer, and does not form an unfired internal electrode layer 121 or 122 or an unfired second dielectric ceramic layer 120b.

[0201] The first internal electrode layer 121 and the second internal electrode layer 122 can be formed using any conductive paste. When the first internal electrode layer 121 and the second internal electrode layer 122 are formed using the conductive paste, for example, a method such as screen printing or gravure printing can be used.

[0202] The first internal electrode layer 121 and the second internal electrode layer 122 are arranged across two adjacent regions in the length (L) direction separated by the cutting line Y, and extend in a strip shape in the width (W) direction. In the first internal electrode layer 121 and the second internal electrode layer 122, the regions separated by the cutting line Y are staggered in the length (L) direction in rows. That is, the cutting line Y passing through the center of the first internal electrode layer 121 passes through the region between the second internal electrode layers 122 (i.e., the center of the second dielectric ceramic layer 120b), and the cutting line Y passing through the center of the second internal electrode layer 122 passes through the region between the first internal electrode layers 121 (i.e., the center of the second dielectric ceramic layer 120b).

[0203] Then, the first ceramic green sheet 101 , the second ceramic green sheet 102 , and the third ceramic green sheet 103 are stacked to produce a mother block.

[0204] Fig. 9 It is an exploded perspective view schematically showing an example of a mother block.

[0205] exist Fig. 91, for the sake of convenience, the first ceramic green sheet 101, the second ceramic green sheet 102, and the third ceramic green sheet 103 are shown in exploded form. In the actual mother block 104, the first ceramic green sheet 101, the second ceramic green sheet 102, and the third ceramic green sheet 103 are pressed and integrated by a method such as isostatic pressing.

[0206] exist Fig. 9 In the mother block 104 shown in FIG. 1 , first ceramic green sheets 101 and second ceramic green sheets 102 corresponding to the inner layer 30 are alternately stacked in the stacking (T) direction. Furthermore, third ceramic green sheets 103 corresponding to the outer layer 31 and 32 are stacked on the upper and lower surfaces of the alternately stacked first ceramic green sheets 101 and second ceramic green sheets 102 in the stacking (T) direction. Fig. 9 In the embodiment, three third ceramic green sheets 103 are stacked, but the number of third ceramic green sheets 103 can be changed as appropriate.

[0207] By cutting the obtained mother block 100 along the cutting lines X and Y (see Figure 6 , Figure 7 as well as Figure 8 ) to produce a plurality of green chips. For this cutting, for example, dicing, shearing, laser cutting, etc. can be applied.

[0208] Fig.10 It is a perspective view schematically showing an example of a green chip.

[0209] Fig.10 The green chip 110 shown has a laminated structure including a plurality of first dielectric ceramic layers 120a and second dielectric ceramic layers 120b in an unfired state and a plurality of pairs of first internal electrode layers 121 and second internal electrode layers 122. The first side surface 113 and the second side surface 114 of the green chip 110 are surfaces that appear by cutting along a cutting line X, and the first end surface 115 and the second end surface 116 are surfaces that appear by cutting along a cutting line Y. The first internal electrode layer 121 and the second internal electrode layer 122 are exposed on the first side surface 113 and the second side surface 114. In addition, only the first internal electrode layer 121 and the second dielectric ceramic layer 120b are exposed on the first end surface 115, and only the second internal electrode layer 122 and the second dielectric ceramic layer 120b are exposed on the second end surface 116.

[0210] Although the first dielectric ceramic layer 120 a is exposed on the first side surface 113 , the second side surface 114 , the first end surface 115 , and the second end surface 116 , the second dielectric ceramic layer is exposed at different locations in the region where it is arranged.

[0211] That is, the second dielectric ceramic layer 120 b disposed on the first end face 115 side is not exposed at the second end face 116 , and the second dielectric ceramic layer 120 b disposed on the second end face 116 side is not exposed at the first end face 115 .

[0212] An unfired laminate is produced by forming an unfired third dielectric ceramic layer on the first side surface 113 and the second side surface 114 of the obtained green chip 110. The unfired third dielectric ceramic layer is formed, for example, by attaching ceramic green sheets containing dielectric ceramic to the first side surface and the second side surface of the green chip.

[0213] For example, when the third dielectric ceramic layer includes two layers, the inner layer and the outer layer, first, in order to prepare a ceramic green sheet for the inner layer, a ceramic slurry containing a binder and a solvent in addition to a ceramic raw material containing a dielectric ceramic material mainly composed of BaTiO3 or the like is prepared. Si as a sintering aid may be added to the ceramic slurry for the inner layer. The inner layer has a function of bonding with the green chip 110.

[0214] In addition, liquid phase metal may be added to the ceramic slurry for the inner layer, and more rare earth elements, Mg, and Mn may be added to the ceramic slurry for the inner layer than to the ceramic green sheet for forming the inner layer. In this way, the grain growth of ceramic particles contained in the dielectric ceramic layer sandwiched by the widthwise end portions of the internal electrode layer can be suppressed.

[0215] Next, in order to prepare the ceramic green sheet for the outer layer, a ceramic slurry containing a binder and a solvent in addition to a ceramic raw material containing a dielectric ceramic material mainly composed of BaTiO3 or the like is prepared. In addition, Si as a sintering aid may be added to the ceramic slurry for the outer layer. In addition, the Si contained in the ceramic green sheet for the inner layer is preferably more than the Si contained in the ceramic green sheet for the outer layer. The content can be determined by photographing the cross section using WDX and judging by the size of the area where Si is detected.

[0216] The outer layer ceramic slurry is applied to the surface of the resin film and dried to form an outer layer ceramic green sheet. The inner layer ceramic slurry is applied to the surface of the outer layer ceramic green sheet on the resin film and dried to form an inner layer ceramic green sheet. In this way, a ceramic green sheet having a two-layer structure can be obtained.

[0217] In addition, the ceramic green sheet with a two-layer structure can be obtained, for example, by forming a ceramic green sheet for an outer layer and a ceramic green sheet for an inner layer in advance and then bonding them together. In addition, the ceramic green sheet is not limited to two layers, but can also be a plurality of layers of more than three layers.

[0218] Then, the ceramic green sheet is peeled from the resin film.

[0219] Next, the inner layer ceramic green sheet and the first side surface 113 of the green chip 110 are placed opposite each other and pressed to form an unfired side margin 41. Furthermore, the inner layer ceramic green sheet is also placed opposite each other for the second side surface 114 of the green chip 110 and pressed to form an unfired side margin 42. At this time, it is preferred that an organic solvent serving as an adhesive is pre-coated on the side surface of the green chip. By the above, an unfired laminated body can be obtained.

[0220] The unfired laminate obtained by the above method is preferably subjected to barrel grinding or the like. By grinding the unfired laminate, the corners and ridges of the laminate 10 after firing are rounded.

[0221] Next, in the unfired laminated body, an external electrode conductive paste containing Ni and a ceramic material is applied to each of the first end face 115 and the second end face 116 of the green chip 110 .

[0222] The conductive paste for external electrodes preferably contains the same dielectric ceramic material as the first dielectric ceramic layer, the second dielectric ceramic layer or the outer layer as a ceramic material. The content of the ceramic material in the conductive paste for external electrodes is preferably 15% by weight or more. In addition, the content of the ceramic material in the conductive paste for external electrodes is preferably 25% by weight or less.

[0223] Next, the unfired laminated body coated with the conductive paste for external electrodes is degreased under given conditions, for example, in a nitrogen atmosphere, and then fired at a given temperature in a nitrogen-hydrogen-water vapor mixed atmosphere. Thus, the unfired laminated body and the conductive paste for external electrodes are fired simultaneously, and the laminated body 10, the Ni layer connected to the first internal electrode layer 21, and the Ni layer connected to the second internal electrode layer 22 are simultaneously formed by the so-called co-firing method. Then, the first plating layer based on Ni plating and the second plating layer based on Sn plating are sequentially stacked on the surface of each Ni layer. Thus, the first external electrode 51 and the second external electrode 52 are formed.

[0224] In addition, the laminate 10 and the first external electrode 51 and the second external electrode 52 can also be formed at different timings by a so-called post-firing method. Specifically, first, the unfired laminate is subjected to a degreasing treatment under given conditions in a nitrogen atmosphere, for example, and then fired at a given temperature in a nitrogen-hydrogen-water vapor mixed atmosphere, thereby forming the laminate 10. Then, a conductive paste containing Cu powder is applied to each of the first end face 15 and the second end face 16 of the laminate 10 and fired. Thus, a base electrode layer connected to the first internal electrode layer 21 and a base electrode layer connected to the second internal electrode layer 22 are formed. Then, a conductive resin layer containing conductive particles (for example, metal particles such as Cu, Ag, Ni, etc.) and a resin, a first plating layer based on Ni plating, and a second plating layer based on Sn plating are sequentially stacked on the surface of each base electrode layer. Thus, the first external electrode 51 and the second external electrode 52 are formed.

[0225] In the above manner, the multilayer ceramic capacitor 1 can be manufactured.

[0226] In the above embodiment, after the mother block 104 is cut along the cutting lines X and Y to obtain a plurality of green chips, the unfired third dielectric ceramic layers are formed on both side surfaces of the green chips. However, this may be changed as follows.

[0227] That is, the mother block may be cut only along the cutting line X to obtain a plurality of rod-shaped green blocks whose first internal electrode layer and second internal electrode layer are exposed on the side surfaces formed by cutting along the cutting line X, and then an unfired third dielectric ceramic layer is formed on both side surfaces of the green block, and then the mother block is cut along the cutting line Y to obtain a plurality of unfired laminated bodies, and then the unfired laminated bodies are fired. After firing, the same steps as those in the above-mentioned embodiment are performed, thereby manufacturing a laminated ceramic capacitor.

[0228] The present invention further includes the following structures (1) to (7).

[0229] (1) Alloy parts between dielectric ceramic layer and internal electrode layer and external electrode

[0230] In the multilayer ceramic capacitor 1 of the present invention, as Fig.11 As shown in the figure, the second alloy portion 320 is formed between the second dielectric ceramic layer 20b and the first internal electrode layer 21 and between the second dielectric ceramic layer 20b and the second internal electrode layer 22. In addition, in the multilayer ceramic capacitor 1 of the present invention, the first alloy portion 310 is formed between the first dielectric ceramic layer 20a and the first internal electrode layer 21 and between the first dielectric ceramic layer 20a and the second internal electrode layer 22.

[0231] like Fig.12 As shown, the metal element 321a is segregated at the interface 2220b between the second internal electrode layer 22 and the second dielectric ceramic layer 20b. The second alloy portion 320 is formed by the segregation layer 321, which is a layered segregation caused by the metal element 321a. Similarly, the metal element 321a is also segregated at the interface 2220b between the first internal electrode layer 21 and the second dielectric ceramic layer 20b to form the segregation layer 321, and the second alloy portion 320 based on the segregation layer 321 is formed. The second alloy portion 320 is formed on the surface of the first internal electrode layer 21 and the second internal electrode layer 22 on the second dielectric ceramic layer 20b side. The second alloy portion 320 is formed between the first internal electrode layer 21 and the second dielectric ceramic layer 20b and between the second internal electrode layer 22 and the second dielectric ceramic layer 20b.

[0232] In addition, if Fig.12 As shown, the metal element 311a is segregated at the interface 2220a between the second internal electrode layer 22 and the first dielectric ceramic layer 20a. The first alloy portion 310 is formed by the segregation layer 311, which is a layered segregation caused by the metal element 311a. Similarly, the metal element 311a is segregated at the interface 2220a between the first internal electrode layer 21 and the first dielectric ceramic layer 20a to form the segregation layer 311, and the first alloy portion 310 based on the segregation layer 311 is formed. The first alloy portion 310 is formed on the surface of the first internal electrode layer 21 and the second internal electrode layer 22 on the first dielectric ceramic layer 20a side. The first alloy portion 310 is formed between the first internal electrode layer 21 and the first dielectric ceramic layer 20a and between the second internal electrode layer 22 and the first dielectric ceramic layer 20a.

[0233] There are multiple types of segregated metal elements 321a forming the second alloy portion 320. The multiple types of metal elements 321a forming the segregated layer 321 include the metal element that is most abundant among the metal elements constituting the first internal electrode layer 21 and the second internal electrode layer 22 and the element derived from the second dielectric ceramic layer 20b. The same is true for the segregated metal elements 311a forming the first alloy portion 310. That is, the metal elements 311a include the metal element that is most abundant among the metal elements constituting the first internal electrode layer 21 and the second internal electrode layer 22 and the element derived from the first dielectric ceramic layer 20a.

[0234] As the metal element that is contained most among the metal elements constituting the first internal electrode layer 21 and the second internal electrode layer 22, for example, one of Ni, Cu, Ag, Pd, Au, and Pt can be cited. On the other hand, as the element derived from the second dielectric ceramic layer 20b and the first dielectric ceramic layer 20a, for example, a metal element as an additive can be cited. Specifically, any one or more metal elements in the metal group of Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, Y, and Ge can be cited, and among them, Sn, Ga, and Ge are particularly preferred. Hereinafter, this metal group may be referred to as a metal group M.

[0235] The segregation of the metal element 321a occurs when the metal element included in the second dielectric ceramic layer 20b moves to the first internal electrode layer 21 and the second internal electrode layer 22 when the second dielectric ceramic layer 20b is fired. In addition, the segregation of the metal element 311a occurs when the metal element included in the first dielectric ceramic layer 20a moves to the first internal electrode layer 21 and the second internal electrode layer 22 when the first dielectric ceramic layer 20a is fired.

[0236] When the first dielectric ceramic layer 20a contains BaTiO3 as the main component, the second alloy portion 320 has a higher molar ratio of the metal element contained in the second dielectric ceramic layer 20b, that is, the content of any one or more of the above-mentioned metal group M relative to 100 mols of Ti than the first alloy portion 310.

[0237] Fig.13 FIG. 2 shows a plane including the center portion in the width (W) direction, the length (L) direction, and the stacking (T) direction of the laminated body 10. In the laminated ceramic capacitor 1 of the present invention, Fig.13 In the illustrated plane, the first internal electrode layer 21 includes a plurality of first dispersed internal electrodes 210 at the end in the length (L) direction not connected to the second external electrode 52, and the plurality of first dispersed internal electrodes 210 are dispersed discontinuously in the length (L) direction. In addition, the second internal electrode layer 22 includes a plurality of second dispersed internal electrodes 220 at the end in the length (L) direction not connected to the first external electrode 51, and the plurality of second dispersed internal electrodes 220 are dispersed discontinuously in the length (L) direction. The first dispersed internal electrodes 210 and the second dispersed internal electrodes 220 are each formed inside the second dielectric ceramic layer 20b. The plurality of first dispersed internal electrodes 210 sometimes extend in the width (W) direction and are connected to the first internal electrode layer 21. In addition, the plurality of second dispersed internal electrodes 220 sometimes extend in the width (W) direction and are connected to the second internal electrode layer 22.

[0238] A fourth alloy portion 340 is formed around each of the first dispersed internal electrode 210 and the second dispersed internal electrode 220. The fourth alloy portion 340 is formed of a segregation layer 341, which is a layered segregation caused by a metal element 341a. The metal element 341a includes the most contained metal element among the metal elements constituting the first internal electrode layer 21 and the second internal electrode layer 22 and one or more metal elements of the metal group M derived from the second dielectric ceramic layer 20b.

[0239] The segregation of the metal element 341a occurs when the metal element included in the second dielectric ceramic layer 20b moves to the first dispersed internal electrode 210 and the second dispersed internal electrode 220 when the second dielectric ceramic layer 20b is fired. In addition, the segregation of the metal element 341a occurs around one or more first dispersed internal electrodes 210 and a plurality of second dispersed internal electrodes 220. Alternatively, the segregation of the metal element 341a may occur around the entire periphery of the first dispersed internal electrode 210 and the entire periphery of the second dispersed internal electrode 220.

[0240] like Fig.14 As shown, in the multilayer ceramic capacitor 1 of the present invention, the third alloy portions 330 are formed between the third dielectric ceramic layers 41 and 42 and the first internal electrode layer 21 and between the third dielectric ceramic layers 41 and 42 and the second internal electrode layer 22 .

[0241] like Fig.14 As shown, the metal element 331a is segregated at the interface 2220c between the first internal electrode layer 21 and the third dielectric ceramic layers 41 and 42. In addition, the metal element 331a is also segregated at the interface 2220c between the second internal electrode layer 22 and the third dielectric ceramic layers 41 and 42. The third alloy portion 330 is formed by the layered segregation caused by the metal element 331a, that is, by the segregation layer 331. The third alloy portion 330 is formed on the surface of the third dielectric ceramic layer 41 side and the second internal electrode layer 22. The third alloy portion 330 is formed between the first internal electrode layer 21 and the third dielectric ceramic layers 41 and 42 and between the second internal electrode layer 22 and the third dielectric ceramic layers 41 and 42, respectively.

[0242] The metal element 331a includes the most metal element among the metal elements constituting the first internal electrode layer 21 and the second internal electrode layer 22 and any one or more metal elements in the metal group M derived from the third dielectric ceramic layers 41 and 42. As the element derived from the third dielectric ceramic layers 41 and 42, for example, metal elements as additives can be cited. Specifically, any one or more metal elements in the metal group M can be cited.

[0243] The segregation of the metal element 331 a occurs when the metal element included in the third dielectric ceramic layers 41 and 42 migrates to the first internal electrode layer 21 and the second internal electrode layer 22 when the third dielectric ceramic layers 41 and 42 are fired.

[0244] In the multilayer ceramic capacitor 1 of the present invention, when the first external electrode 51 and the second external electrode 52 are each formed as a base electrode layer including a Ni layer and formed by a co-firing method, Fig.15 As shown, a fifth alloy portion 350 is formed in the Ni layer.

[0245] Fig.15 The fifth alloy portion 350 is shown in the state formed at the interface 51b between the first external electrode 51 and the second dielectric ceramic layer 20b. The fifth alloy portion 350 is formed by a segregation layer 351, which is a layered segregation caused by a metal element 351a. Similarly, the fifth alloy portion 350 formed by the segregation of the metal element 351a is also formed at the interface 51b between the second external electrode 52 and the second dielectric ceramic layer 20b. The segregation of the metal element 351a occurs when the metal element contained in the second dielectric ceramic layer 20b moves to the first external electrode 51 and the second external electrode 52 when the second dielectric ceramic layer 20b is fired.

[0246] In addition, in the laminated body 10 of the laminated ceramic capacitor 1 of the present invention, the first internal electrode layer 21 and the second internal electrode layer 22 and the second dielectric ceramic layer 20b may overlap each other at adjacent ends. Fig.16 As shown in FIG. 1 , the end of the second dielectric ceramic layer 20b overlaps the end of the second internal electrode layer 22. Fig.17 As shown, the end of the second dielectric ceramic layer 20b overlaps the end of the first internal electrode layer 21. In such an end-overlapping embodiment, the first internal electrode layer 21 and the second internal electrode layer 22 may be overlapped on the second dielectric ceramic layer 20b.

[0247] In the multilayer ceramic capacitor 1 of the present invention, a second alloy portion 320 is formed between the second dielectric ceramic layer 20b and the first internal electrode layer 21 and between the second dielectric ceramic layer 20b and the second internal electrode layer 22, respectively. The second alloy portion 320 includes a metal element that is most abundant among the metal elements constituting the internal electrode layers and any one or more metal elements of the metal group M of Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, and Y.

[0248] The electric field is easily concentrated at the ends of the first internal electrode layer 21 and the second internal electrode layer 22 that are in contact with the second dielectric ceramic layer 20b, and thus the reliability of the multilayer ceramic capacitor may be reduced. However, the multilayer ceramic capacitor 1 of the present invention can suppress the electric field concentration by forming the second alloy portion 320 between the second dielectric ceramic layer 20b and the first internal electrode layer 21 and the second internal electrode layer 22, and can improve the reliability.

[0249] In the multilayer ceramic capacitor 1 of the present invention, when the first dielectric ceramic layer 20a contains Ba and Ti, a first alloy part 310 is formed between the first dielectric ceramic layer 20a and the first internal electrode layer 21 and between the first dielectric ceramic layer 20a and the second internal electrode layer 22, respectively. The first alloy part 310 contains the most metal element among the metal elements constituting the internal electrode layers and one or more metal elements of the metal group M. The second alloy part 320 has a higher molar ratio of Ti relative to 100 mol in the content of the metal group M than the first alloy part 310.

[0250] Thus, the electric field concentration in the vicinity of the interface between the first internal electrode layer 21 and the second internal electrode layer 22 and the second dielectric ceramic layer 20b is suppressed by the second alloy portion 320, and reliability can be improved. In addition, the second alloy portion 320 formed at the end of the first internal electrode layer 21 and the second internal electrode layer 22 in contact with the second dielectric ceramic layer 20b, where electric field concentration is likely to occur, is increased in the molar ratio of Ti relative to 100 mol in the content of the metal group M compared to the first alloy portion 310 formed on the first dielectric ceramic layer 20a side, thereby effectively suppressing the electric field concentration on the second dielectric ceramic layer 20b side, and reliability can be further improved.

[0251] By controlling the amount of metal of the metal group M added to each of the first dielectric ceramic layer 20a and the second dielectric ceramic layer 20b, the thickness of the first alloy portion 310 and the second alloy portion 320 and the concentration of the metal group M contained therein can be controlled. For example, when the concentration of the metal group M added to the second dielectric ceramic layer 20b is higher than that of the first dielectric ceramic layer 20a, as shown in FIG. Fig.12 As shown, the thickness of the second alloy portion 320 increases or the concentration of the metal group M increases as the second dielectric ceramic layer 20 b approaches, and these two changes occur depending on the situation.

[0252] In the multilayer ceramic capacitor 1 of the present invention, in a plane including the center portion in the width (W) direction, the length (L) direction, and the stacking (T) direction of the multilayer body 10, the first internal electrode layer 21 includes a first dispersed internal electrode 210 at an end portion in the length (L) direction not connected to the second external electrode 52, the first dispersed internal electrode 210 being dispersed discontinuously in the length (L) direction, the second internal electrode layer 22 includes a second dispersed internal electrode 220 at an end portion in the length (L) direction not connected to the first external electrode 51, the second dispersed internal electrode 220 being dispersed discontinuously in the length (L) direction, and a fourth alloy portion 340 is formed around each of the first dispersed internal electrode 210 and the second dispersed internal electrode 220, the fourth alloy portion 340 including a metal element that is the most contained among the metal elements constituting the internal electrode layers and any one or more metal elements of the metal group M.

[0253] When the first dispersed internal electrode 210 and the second dispersed internal electrode 220 extend in the width (W) direction and are connected to the first internal electrode layer 21 and the second internal electrode layer 22, respectively, if the electric field is concentrated at the connected portion, insulation breakdown may occur, thereby reducing reliability. However, the multilayer ceramic capacitor 1 of the present invention can suppress insulation breakdown caused by electric field concentration by forming the fourth alloy portion 340 around each of the first dispersed internal electrode 210 and the second dispersed internal electrode 220, thereby improving reliability.

[0254] In the multilayer ceramic capacitor 1 of the present invention, a third alloy portion 330 is formed between the third dielectric ceramic layers 41 and 42 and the first internal electrode layer 21, and between the third dielectric ceramic layers 41 and 42 and the second internal electrode layer 22, respectively. The third alloy portion 330 includes the most abundant metal element among the metal elements constituting the internal electrode layers and any one or more metal elements of the above-mentioned metal group M.

[0255] Thus, electric field concentration is suppressed by the third alloy portion 330 in the vicinity of the interface between the first internal electrode layer 21 and the second internal electrode layer 22 and the third dielectric ceramic layers 41 and 42 , thereby improving reliability.

[0256] In the multilayer ceramic capacitor 1 of the present invention, the first external electrode 51 and the second external electrode 52 contain Ni, and a fifth alloy portion 350 is formed between the second dielectric ceramic layer 20 b and the first external electrode 51 and the second external electrode 52, in which one or more metal elements of the above-mentioned metal group M are segregated to Ni.

[0257] Therefore, when the interval between the first internal electrode layer 21 and the second external electrode 52 and between the second internal electrode layer 22 and the first external electrode 51, that is, the distance in the length (L) direction of the second dielectric ceramic layer 20b is as narrow as less than 15 μm, due to the presence of the fifth alloy portion 350, insulation breakdown caused by electric field concentration is less likely to occur between the internal electrode layers and the external electrodes, thereby improving reliability.

[0258] [Test Example 1]

[0259] Next, Test Example 1 for verifying the effects of first alloy portion 310 , second alloy portion 320 , and third alloy portion 330 in multilayer ceramic capacitor 1 of the present invention will be described.

[0260] For TEM analysis

[0261] In the manufacturing method of the multilayer ceramic capacitor of the present invention, the multilayer body 10 obtained by firing the green chip 110 without co-firing the first external electrode 51 and the second external electrode 52 is ground from the first side surface 13 and the second side surface 14 to obtain a laminated body 10 as shown in FIG. Fig.18 The polished body shown in the figure with the center portion in the width (W) direction left was used as a test body.

[0262] The types of metal elements and the metal amounts (metal concentrations) contained in the first alloy portion 310 were analyzed as follows.

[0263] like Fig.18 As shown, in the center of the length (L) direction, an imaginary line OL1 orthogonal to the length (L) direction is assumed. Then, along the imaginary line OL1, the region where the first dielectric ceramic layer 20a, the first internal electrode layer 21, and the second internal electrode layer 22 involved in obtaining the electrostatic capacitance of the grinding body are stacked is divided into three equal regions in the stacking direction, namely, an upper region E1, a central region E2, and a lower region E3.

[0264] The upper region E1, the central region E2, and the lower region E3 are cut out from the polished body and thinned by Ar ion milling or the like to obtain three thin film samples from each region.

[0265] TEM observation and element mapping using EDX attached to the TEM were performed on the three thin film samples of the upper region E1, the central region E2, and the lower region E3 of the test body obtained as described above.

[0266] As a result, no significant difference was observed between the upper region E1 and the lower region E3 and the central region E2, so the result obtained from the central region E2 was regarded as the microstructure of the dielectric ceramic layer and the internal electrode layer. As a result, the type and amount of metal elements (metal concentration) contained in the first alloy portion 310 can be known.

[0267] In addition, the type of metal element and the amount of metal (metal concentration) contained in the second alloy portion 320 can be analyzed by obtaining a thin film sample in the region where one end portion in the length (L) direction of the second alloy portion 320 exists in the same manner as described above. Fig.18 In the polishing body shown, at one end in the length (L) direction, an imaginary line OL2 orthogonal to the length (L) direction is assumed, and thin film samples of three regions, namely, an upper region E4, a central region E5, and a lower region E6, which are divided into three equal parts along the imaginary line OL2 in the stacking direction, are obtained. Then, TEM observation and element mapping based on EDX attached to TEM are performed on the three thin film samples of the upper region E4, the central region E5, and the lower region E6, and the types of metal elements and the metal amount (metal concentration) contained in the second alloy part 320 are investigated.

[0268] For the second alloy part and the first alloy part, the concentration of Sn was investigated by analyzing the EDX mapping image based on the TEM observation image. The measurement points of TEM were measured at intervals of about 5nm to 10nm. In the interface between the internal electrode layer and the dielectric ceramic layer, the area with an observation value of more than 3 times that of other measurement points was regarded as the alloy part, and the average value was regarded as the metal concentration of the alloy part.

[0269] 18 multilayer ceramic capacitors of each of the test examples 1-1 to 1-5 shown in Table 1 were prepared. In test example 1-2, in the multilayer ceramic capacitor of the present invention, the first internal electrode layer 21 and the second internal electrode layer 22 contained Ni, and the same amount of Sn as an additive was added to the first dielectric ceramic layer 20a and the second dielectric ceramic layer 20b. In test examples 1-3 to 1-5, the amount of Sn added to the second dielectric ceramic layer 20b was gradually increased compared to test example 1-2. In addition, in test example 1-1, except that Sn was not added to the second dielectric ceramic layer 20b, the multilayer ceramic capacitor was set to the same conditions as test examples 1-2 to 1-5.

[0270] For the multilayer ceramic capacitors of Test Examples 1-1 to 1-5, the resistance value (kΨ) was measured in a state where a voltage of 6.3V was applied at a temperature of 150°C, and the MTTF (mean time to failure) was investigated and determined. The MTTF is set as the time point when the resistance value becomes less than 10kΩ. When the MTTF is less than 15.3 hours (hr), it is judged as "×", and when it exceeds 15.3 hours (hr) and up to 30 hours, it is judged as "○" (good), and when it exceeds 30 hours, it is judged as "◎" (excellent). The results are recorded in Table 1. In addition, with regard to the coverage of the internal electrode layer, when it is less than 80%, it becomes difficult to obtain electrostatic capacitance, so it is set to be impossible to measure.

[0271] [Table 1]

[0272]

[0273] According to Table 1, by forming the second alloy portion, the MTTF exceeded 15.3 hours, which is a prescribed time, and was good, and the higher the Sn concentration, the better. On the other hand, in Test Example 1-1 in which the second alloy portion containing Sn was not formed, the MTTF did not exceed the prescribed time. Thus, it was confirmed that the second alloy portion improved the reliability of the laminated ceramic capacitor.

[0274] Next, in addition to Test Example 1-1, 18 multilayer ceramic capacitors of Test Examples 1-6 to 1-9 shown in Table 2 were prepared. In Test Example 1-6, in Test Example 1-2, Sn as an additive was further added to the third dielectric ceramic layer in an amount equal to that of the first dielectric ceramic layer and the second dielectric ceramic layer. In Test Examples 1-7 to 1-9, the amount of Sn added to the third dielectric ceramic layer was gradually increased compared to Test Example 1-6. In Test Example 1-1, Sn was not added to the third dielectric ceramic layer.

[0275] The MTTF evaluation was performed on Test Examples 1-1 and 1-6 to 1-9 in the same manner as in the above-mentioned Test Examples 1-1 to 1-5. The results are shown in Table 2.

[0276] [Table 2]

[0277]

[0278] According to Table 2, by forming the third alloy part together with the second alloy part, the MTTF exceeded 15.3 hours, which is a prescribed time, and was good, and the higher the Sn concentration, the better. On the other hand, in Test Example 1-1 in which neither the second alloy part nor the third alloy part containing Sn was formed, the MTTF failed to exceed the prescribed time. Thus, it was confirmed that the second alloy part and the third alloy part improved the reliability of the laminated ceramic capacitor.

[0279] (2) Average particle size of dielectric particles contained in the region near the intersection

[0280] Fig.19 FIG. 2 shows a surface including the length (L) direction and the width (W) direction of the multilayer ceramic capacitor 1 of the present invention and including the second dielectric ceramic layer 20 b and the second internal electrode layer 22 . Fig.19 As shown, the end portion on the first end face 15 side of the multilayer ceramic capacitor 1 has an intersection 400 of interfaces surrounded by the second dielectric ceramic layer 20b, the second internal electrode layer 22, and the third dielectric ceramic layers 41 and 42 on both sides in the width (W) direction. The intersection 400 is an intersection of the interface 2220b between the second dielectric ceramic layer 20b and the second internal electrode layer 22 and the inner surface 401 of the third dielectric ceramic layers 41 and 42 in the width (W) direction. Similarly, the end portion on the second end face 16 side also has an intersection 400 of interfaces surrounded by the second dielectric ceramic layer 20b, the first internal electrode layer 21, and the third dielectric ceramic layers 41 and 42 on both sides in the width (W) direction.

[0281] The area inside the circle 400r with a radius of 5 μm and centered at the intersection 400 is defined as the second intersection vicinity area 420. The area inside the circle 400r with a radius of 5 μm and centered at the intersection 400 is defined as the third intersection vicinity area 430. The area inside the circle 400r also includes the line of the circle 400r. In the following description, the second intersection vicinity area 420 on the second dielectric ceramic layer 20b side and the third intersection vicinity area 430 on the third dielectric ceramic layers 41 and 42 side are sometimes collectively referred to as the intersection vicinity area 440.

[0282] The region inside the second intersection vicinity region 420 includes a portion of the second dielectric ceramic layer 20 b . The region inside the third intersection vicinity region 430 includes a portion of the third dielectric ceramic layers 41 and 42 .

[0283] In the multilayer ceramic capacitor 1 of the present invention,

[0284] (A) The average particle size of the dielectric particles contained in each intersection vicinity region 440 is smaller than the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20 a , the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20 b , and the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 .

[0285] (B) In addition, as a ratio of the sizes, it is preferably smaller by 5% or more.

[0286] In addition, the so-called average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b in this case refers to the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b in the portion outside the second intersection vicinity region 420, and the so-called average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 refers to the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 in the portion outside the third intersection vicinity region 430.

[0287] The multilayer ceramic capacitor 1 of the present invention having the above-mentioned structure (A) or (B) preferably further has any one of the following structures (C) to (I).

[0288] (C) The difference between the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b and the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 is within 5%, the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a is larger than any of the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b and the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42, and the average particle size of the dielectric particles contained in the intersection vicinity region 440 is smaller than any of the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b and the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42.

[0289] (D) The difference between the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a and the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b is within 5%, the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 is smaller than any of the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a and the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b, and the average particle size of the dielectric particles contained in the intersection vicinity region 440 is smaller than the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42.

[0290] (E) The difference between the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a and the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 is within 5%, the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b is smaller than any of the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a and the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42, and the average particle size of the dielectric particles contained in the intersection vicinity region 440 is smaller than the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b.

[0291] (F) The difference between the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a and the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b, the difference between the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a and the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42, and the difference between the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b and the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 are all within 5%, and the average particle size of the dielectric particles contained in the intersection vicinity region 440 is smaller than any of the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a, the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b, and the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42.

[0292] (G) The average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a is smaller than the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b, the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 is smaller than the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a, and the average particle size of the dielectric particles contained in the intersection vicinity region 440 is smaller than the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42.

[0293] (H) The average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a is smaller than the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42, the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b is smaller than the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a, and the average particle size of the dielectric particles contained in the intersection vicinity region 440 is smaller than the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b.

[0294] (I) The average particle size of the dielectric particles contained in the intersection vicinity region 440 is smaller than the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a, and the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 or the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b is smaller than the average particle size of the dielectric particles contained in the intersection vicinity region 440.

[0295] The average particle size of the dielectric particles included in the first dielectric ceramic layer 20a, the second dielectric ceramic layer 20b, and the third dielectric ceramic layers 41 and 42 can be controlled by adjusting the amount of sintering aids represented by Si, Mn, etc. included in the dielectric ceramic slurry forming each dielectric ceramic layer and further adjusting the firing temperature.

[0296] As described above, in the multilayer ceramic capacitor 1 of the present invention, the average particle size of the dielectric particles contained in the intersection vicinity region 440 is smaller than the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a around the intersection vicinity region 440, the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b, and the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42.

[0297] The electric field is easily concentrated in the region 440 near the intersection. If the electric field concentration occurs, the reliability of the laminated ceramic capacitor may be reduced. However, in the laminated ceramic capacitor 1 of the present invention, the average particle size of the dielectric particles contained in the region 440 near the intersection is smaller than the average particle size of the dielectric particles contained in the surrounding first dielectric ceramic layer 20a, second dielectric ceramic layer 20b, and third dielectric ceramic layers 41 and 42. In this way, the average particle size is small, so that there are many grain boundaries, which can suppress the electric field concentration. As a result, the reliability of the laminated ceramic capacitor can be improved.

[0298] [Test Example 2]

[0299] Next, Experimental Example 2 is described. Experimental Example 2 verifies that the average particle size of the dielectric particles contained in the intersection vicinity region 440 in the multilayer ceramic capacitor 1 of the present invention is more advantageous when it is smaller than the average particle size of the dielectric particles contained in the surrounding first dielectric ceramic layer 20a and third dielectric ceramic layers 41 and 42, respectively.

[0300] The average particle size of the dielectric particles included in each of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer is measured as follows.

[0301] (Average Particle Size of Dielectric Particles Contained in First Dielectric Ceramic Layer)

[0302] In the manufacturing method of the multilayer ceramic capacitor of the present invention, the multilayer body 10 obtained by firing the green chip 110 without co-firing the first external electrode 51 and the second external electrode 52 is ground from the first end face 15 side or the second end face 16 side. Fig. 20 As shown, a test body was obtained by leaving the center portion in the length (L) direction.

[0303] like Fig. 20As shown, in the central part of the width (W) direction, an imaginary line OS1 orthogonal to the width (W) direction is assumed. Then, along the imaginary line OS1, the area where the first dielectric ceramic layer 20a, the first internal electrode layer 21, and the second internal electrode layer 22 involved in obtaining the electrostatic capacitance of the grinding body are stacked is divided into three equal parts in the stacking direction, namely, the upper area F1, the central area F2, and the lower area F3. For each area F1, F2, and F3, the first dielectric ceramic layer 20a is photographed with a field size of 4.3μm×3.2μm, and the area of ​​20 dielectric particles is measured by image processing for each of the areas F1, F2, and F3. Then, the equivalent circle diameter is calculated based on the measured area and averaged to obtain the average particle size. The average grain size was measured in each of the upper region F1 , the central region F2 , and the lower region F3 . Since no significant difference was observed in the measured values, the average grain size in the central region F2 was regarded as the average grain size of the first dielectric ceramic layer.

[0304] (Average Particle Size of Dielectric Particles Contained in Third Dielectric Ceramic Layer)

[0305] exist Fig. 20 In the test body shown, an imaginary line connecting the ends of the first side surface 13 or the second side surface 14 of the plurality of first internal electrode layers 21 and the plurality of second internal electrode layers 22 in the stacking (T) direction is assumed. Fig. 20 , an imaginary line OS3 is shown connecting the ends of the plurality of first internal electrode layers 21 and the plurality of second internal electrode layers 22 on the second side surface 14 side in the stacking (T) direction. Fig.21 As shown, the third dielectric ceramic layer 42 was imaged from the virtual line OS3 with a field size of 4.3 μm×3.2 μm in a range of 5 μm, and the area of ​​20 dielectric particles was measured by image processing for each of the regions F1 , F2 , and F3 . Fig.21 The reference numeral 42F of FIG. 4 shows the photographed area. Then, the equivalent circle diameter is calculated from the measured area and the average is taken as the average particle size. The average particle size is measured in each of the upper region F1, the central region F2, and the lower region F3, and no significant difference is observed in the measured values, so the average particle size of the central region F2 is regarded as the average particle size of the third dielectric ceramic layer.

[0306] (Average Particle Size of Dielectric Particles Contained in Second Dielectric Ceramic Layer)

[0307] The laminate 10 is ground from the first end face 15 side or the second end face 16 side until at least one of the internal electrode layers appears. Fig. 22As shown in FIG. 1 , the second end face 16 is ground to a surface J immediately before the second internal electrode layer 22 appears. Fig.23 As shown, in the central part of the width (W) direction, an imaginary line OS2 orthogonal to the width (W) direction is assumed. Then, along the imaginary line OS2, the second dielectric ceramic layer 20b is divided into three equal parts in the stacking direction, namely, the upper region G1, the central region G2, and the lower region G3. The second dielectric ceramic layer is photographed in each region G1, G2, and G3 with a field of view size of 4.3μm×3.2μm, and the area of ​​20 dielectric particles is measured by image processing for each of the regions G1, G2, and G3. Then, the equivalent circle diameter is calculated based on the measured area and the average is taken as the average particle size. The average particle size is measured in each of the upper region G1, the central region G2, and the lower region G3, and no significant difference is observed in the measured values, so the average particle size of the central region G2 is regarded as the average particle size of the second dielectric ceramic layer.

[0308] (Average particle size of dielectric particles contained in the region near the intersection)

[0309] exist Fig.23 In the test body shown, it is assumed that an imaginary line OS4 connects the ends of the second side surface 14 of the plurality of first internal electrode layers 21 and the plurality of second internal electrode layers 22 in the stacking (T) direction. Then, along the imaginary line OS4, the area on both sides of the width (W) direction of the imaginary line OS4 including the area 440 near the intersection is divided into three equal areas in the stacking direction, namely, the upper area H1, the central area H2, and the lower area H3. Fig.24 As shown, the second dielectric ceramic layer 20b and the third dielectric ceramic layer 42 are photographed with a field of view size of 4.3μm×3.2μm in a range of 5μm on both sides of the width (W) direction of the imaginary line OS4, and the area of ​​20 dielectric particles is measured by image processing for each of the regions F1, F2 and F3. Fig.24 The reference numeral 42H in the figure shows the shooting area. Then, the equivalent circle diameter is calculated based on the measured area and averaged to obtain the average particle size. The average particle size is measured in each of the upper area H1, the central area H2, and the lower area H3, and no significant difference is observed in the measured values, so the average particle size of the central area H2 is regarded as the average particle size of the area 440 near the intersection.

[0310] As a laminated ceramic capacitor corresponding to the above-mentioned (C) to (I), Test Examples 2-1 to 2-24 shown in Table 3 were prepared. In addition, in Test Examples 2-25 to 2-27, the average particle size of the dielectric particles contained in the intersection vicinity region 440 was set to be larger than any of the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a, the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b, and the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42. For these Test Examples 2-1 to 2-27, the average particle size was investigated by the above-mentioned measurement method.

[0311] In addition, in Table 3, "1st" in the item of comparison of average particle size is the average particle size of the dielectric particles contained in the first dielectric ceramic layer, "2nd" is the average particle size of the dielectric particles contained in the second dielectric ceramic layer, "3rd" is the average particle size of the dielectric particles contained in the third dielectric ceramic layer, and "intersection" is the average particle size of the dielectric particles contained in the area near the intersection.

[0312] On the other hand, for the laminated ceramic capacitors of test examples 2-25 to 2-27, the resistance value (kΩ) was measured in a state where a voltage of 6.3V was applied at a temperature of 150°C, and the MTTF (mean time to failure) was investigated and determined. The MTTF was set to the time point when the resistance value became less than 10kΩ, and the case where the MTTF was less than 15.3 hours (hr) was judged as "×", and the case where it exceeded 15.3 hours (hr) until 30 hours was judged as "○" (good), and the case where it exceeded 30 hours was judged as "◎" (excellent). The results are recorded in Table 3. In addition, with regard to the coverage of the internal electrode layer, when it is less than 80%, it becomes difficult to obtain electrostatic capacitance, so it is set to be impossible to measure.

[0313] [Table 3]

[0314]

[0315] Table 3 shows that when the average particle size of dielectric particles contained in the intersection vicinity region is smaller than the average particle size of dielectric particles contained in each of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer, the MTTF increases and the reliability of the multilayer ceramic capacitor improves.

[0316] (3) Manufacturing method with an additional step of removing the side surface of the laminate

[0317] In the above-mentioned method for manufacturing the multilayer ceramic capacitor 1 of the present invention, when obtaining the green chip 110 as the unfired laminated body 10, the method includes: a step of printing the unfired first internal electrode layer 121 and the second internal electrode layer 122 on the unfired first dielectric ceramic layer 120a; a step of forming the unfired second dielectric ceramic layer 120b outside the region on which the first internal electrode layer 121 and the second internal electrode layer 122 are printed in the first dielectric ceramic layer 120a; and a step of placing the plurality of first dielectric ceramic layers 120a on the first dielectric ceramic layer 120b. The process of stacking ceramic layers 120a to form a raw chip 110; the process of exposing the first internal electrode layer 121 and the second internal electrode layer 122, the first dielectric ceramic layer 120a, and the second dielectric ceramic layer 120b from the first side surface 113 and the second side surface 114 of each raw chip 110 by cutting the mother block 104; and the process of bonding and forming an unfired third dielectric ceramic layer (side margin portions 41 and 42) on the first side surface 113 and the second side surface 114 of each raw chip 110.

[0318] Here, the green chip 110 is an example of a laminate. The first dielectric ceramic layer 120a is an example of a dielectric layer. The first internal electrode layer 121 and the second internal electrode layer 122 are examples of internal electrode patterns. The second dielectric ceramic layer 120b is an example of a dielectric pattern. The first side surface 113 and the second side surface 114 are examples of side surfaces. The side margins 41 and 42 as the unfired third dielectric ceramic layer are examples of dielectric gap layers.

[0319] In this manufacturing method, after the step of exposing the first internal electrode layer 121 and the second internal electrode layer 122, the first dielectric ceramic layer 120a, and the second dielectric ceramic layer 120b from the first side surface 113 and the second side surface 114 of the green chip 110 by cutting the mother block 104, and before the step of forming the third dielectric ceramic layer by bonding the first side surface 113 and the second side surface 114 of the green chip 110, a removal step of removing a certain thickness from the first side surface 113 and the second side surface 114 can be added. Thus, the side surfaces of the first dielectric ceramic layer 120a, the second dielectric ceramic layer 120b, the first internal electrode layer 121, and the second internal electrode layer 122 exposed on the first side surface 113 and the second side surface 114 can be removed.

[0320] Fig.25 FIG. 1 shows a state where the first side surface 113 and the second side surface 114 of the green chip 110 are planarized by removing a certain thickness (for example, less than 1 μm). Fig.25In the figure, the left side shows before the removal process, and the right side shows after the removal process. The first side surface 113 and the second side surface 114 of the raw chip 110 may be subjected to stress applied to the lower side of the figure as the cutting direction when the mother block 104 is cut to obtain a plurality of raw chips 110, such as Fig.25 As shown in FIG. 1 , the side surface flows slightly downward and undergoes plastic deformation. In addition, sometimes the cut surface is not sufficiently smooth, or there is foreign matter on the cut surface. Therefore, the thickness of the degree to which the deformed portion disappears is removed. The method for removing the first side surface 113 and the second side surface 114 is not limited, but grinding based on an appropriate grinding method is suitable, for example.

[0321] like Fig.26 As shown, the first side surface 113 and the second side surface 114 after the removal process are formed into smooth surfaces and become surfaces from which foreign matter is removed. The third dielectric ceramic layer (side margin portions 41 and 42) is bonded and formed on the first side surface 113 and the second side surface 114 after the removal process.

[0322] In the present invention, each of the second dielectric ceramic layer 20b, the first internal electrode layer 21, and the second internal electrode layer 22 may contain a resin. The resin can be contained by adding it to the material during manufacturing. That is, in the second dielectric ceramic layer 20b, the resin is contained in the dielectric paste, and in the first internal electrode layer 21 and the second internal electrode layer 22, the resin is contained in the conductive paste.

[0323] The resin contained in the dielectric paste and the conductive paste is added for the purpose of functioning as an adhesive and improving the viscosity of the material. Examples of such resins include polyvinyl acetal resins such as polyvinyl butyral and polyvinyl acetoacetal, polyvinyl alcohol resins such as polyvinyl alcohol, cellulose resins such as methylcellulose, ethylcellulose, and cellulose phthalate acetate, (meth) acrylic resins such as (meth) acrylic acid esters, imide resins such as polyamideimide and polyimide, ethylene resins such as polyethylene oxide, nitrile resins such as polyacrylonitrile and polymethacrylonitrile, and urethane resins such as polyurethane. The present invention may include, but is not limited to, vinyl resins such as polyethylene, polypropylene, and vinyl acetate, and rubber resins such as styrene-butadiene rubber.

[0324] In addition, as for the content of the resin, it is preferred that the content contained in the second dielectric ceramic layer 20b is different from the content contained in the first dielectric ceramic layer 20a. The resin content of the first dielectric ceramic layer 20a and the second dielectric ceramic layer 20b is preferably, for example, 30 wt% or more and 50 wt% or less. It is preferred that the resin content of the first dielectric ceramic layer and the second dielectric ceramic layer 20b is different from each other within this range.

[0325] In addition, in the manufacturing method of the multilayer ceramic capacitor of the present invention, the thickness of the first dielectric ceramic layer 120a is preferably not less than 0.4 μm and not more than 0.8 μm. In addition, in the manufacturing method of the multilayer ceramic capacitor of the present invention, the thickness of the first internal electrode layer 121 and the second internal electrode layer 122 is preferably not less than 0.4 μm and not more than 0.8 μm.

[0326] Furthermore, when forming the green chip 110, a portion of the second internal electrode layer 122 may overlap with a portion of the first internal electrode layer 121 and the second internal electrode layer 122. Specifically, the second dielectric ceramic layer 120b and the ends of the first internal electrode layer 121 and the second internal electrode layer 122 that are adjacent to each other in the length (L) direction may overlap with each other. For example, Fig. 27 As shown, in the length (L) direction, the end of the second dielectric ceramic layer 120b overlaps the end of the first internal electrode layer 121. Similarly, the end of the second dielectric ceramic layer 120b may overlap the end of the second internal electrode layer 122. In this way, in the method of overlapping the ends in the length (L) direction, the end of the first internal electrode layer 121 and the end of the second dielectric ceramic layer 120b may overlap the end of the second dielectric ceramic layer 120b.

[0327] In the method for manufacturing a laminated ceramic capacitor of the present invention, after a predetermined thickness is removed from the first side surface 113 and the second side surface 114 of the green chip 110 as the unfired laminated body 10, an unfired third dielectric ceramic layer is adhered and formed on the first side surface 113 and the second side surface 114. Thus, the unfired third dielectric ceramic layer can be formed in a smooth and clean state with respect to the first side surface 113 and the second side surface 114.

[0328] In the method for manufacturing a multilayer ceramic capacitor of the present invention, first side surface 113 and second side surface 114 are removed by polishing, so that first side surface 113 and second side surface 114 can be easily and accurately removed by a predetermined thickness.

[0329] Preferably, in the method for manufacturing a multilayer ceramic capacitor of the present invention, the second dielectric ceramic layer 120b contains a resin whose amount is larger than the amount of resin contained in the first internal electrode layer 121 and the second internal electrode layer 122. Thus, the viscosity of the second dielectric ceramic layer 120b is relatively high, and it is possible to suppress the occurrence of defects such as cracks and fragments of the cut surface of the second dielectric ceramic layer 20b when the mother block 104 is cut.

[0330] In addition, in the method for manufacturing a multilayer ceramic capacitor of the present invention, the thickness of the first dielectric ceramic layer 120a is preferably not less than 0.4 μm and not more than 0.8 μm. In addition, in the method for manufacturing a multilayer ceramic capacitor of the present invention, the thickness of the first internal electrode layer 121 and the second internal electrode layer 122 is preferably not less than 0.4 μm and not more than 0.8 μm. By having such thicknesses of the unfired dielectric layer and the internal electrode layer, the first dielectric ceramic layer 20a, the first internal electrode layer 21, and the second internal electrode layer 22 after firing can be formed to appropriate thicknesses.

[0331] In the method for manufacturing a multilayer ceramic capacitor of the present invention, a portion of the second internal electrode layer 122 may overlap the first internal electrode layer 121 and the second internal electrode layer 122. Thus, after firing, the second dielectric ceramic layer 20b can be arranged with a sufficient thickness without any gap.

[0332] (4) Defective portion of the second dielectric ceramic layer

[0333] In the multilayer ceramic capacitor 1 of the present invention, as Fig.28 as well as Fig.29 As shown, a defect portion 520 in which a part of the second dielectric ceramic layer 20b is missing is provided between at least one second dielectric ceramic layer 20b and one third dielectric ceramic layer 42. Similarly, a defect portion 520 in which a part of the second dielectric ceramic layer 20b is missing is provided between at least one second dielectric ceramic layer 20b and the other third dielectric ceramic layer 41.

[0334] In the region where the second dielectric ceramic layer 20b is arranged, that is, in the length (L) direction of the stacked body 10, in at least one region between the end of the first internal electrode layer 21 not connected to the second external electrode 52 and the second external electrode 52, and between the end of the second internal electrode layer 22 not connected to the first external electrode 51 and the first external electrode 51, a defect portion 520 is formed in a plane including the stacking (T) direction and the width (W) direction, where the position in the stacking (T) direction is between the first dielectric ceramic layers 20a and the position in the width (W) direction is between the second dielectric ceramic layer 20b and the third dielectric ceramic layer 41 or 42.

[0335] When manufacturing the green chip 110 as the unfired laminated body 10, the side surface of the unfired second dielectric ceramic layer 120b is processed and then fired, thereby obtaining the laminated body 10 having the defective portion 520 on the side surface of the second dielectric ceramic layer 20b. The processing method for obtaining the defective portion 520 is arbitrary, and for example, it can be formed by drilling with an appropriate tool or the like.

[0336] In addition, in the above-mentioned "manufacturing method with an additional step of removing the side of the laminate", when the first side 113 or the second side 114 of the unfired green chip 110 is removed by grinding or the like, a part of the side of the second dielectric ceramic layer 20b is sometimes missing and a fine hole is opened. In the case where a hole is generated like this, the hole can also be regarded as a defective portion 520. The defective portion 520 does not need to be formed on all the side surfaces of the second internal electrode layer 22, as long as at least one defective portion 520 is formed on the first side 13 side and the second side 14 side at both ends in the length (L) direction.

[0337] In addition, you can Fig.28 as well as Fig.29 As shown in FIG. 1 , a segregation 530 of Si is arranged in the defect portion 520. The segregation 530 of Si is a segregation of Si added as an additive to the second dielectric ceramic layer 20b.

[0338] The size of the Si segregation 530 is preferably larger than 1 / 3 of the thickness of the second dielectric ceramic layer 20 b in terms of the diameter of the equivalent circle, and may be greater than or equal to 100 nm and less than or equal to 600 nm.

[0339] The defective portion 520 is preferably arranged close to the first internal electrode layer 21 or the second internal electrode layer 22. Fig.29 In the embodiment, the defective portion 520 is arranged near the end of the second internal electrode layer 22 in the length (L) direction. Similarly, it is preferable that the defective portion 520 is arranged near the end of the first internal electrode layer 21 in the length (L) direction.

[0340] The size of the Si segregation 530 is preferably not less than 0.1% and not more than 5% of the size of the third dielectric ceramic layers 41 and 42 in the width (W) direction.

[0341] In the multilayer ceramic capacitor 1 of the present invention, in the region where the second dielectric ceramic layer 20b is arranged, that is, in at least one region between the end of the first internal electrode layer 21 not connected to the second external electrode 52 and the second external electrode 52, and between the end of the second internal electrode layer 22 not connected to the first external electrode 51 and the first external electrode 51 in the length (L) direction of the multilayer body 10, a defect portion 520 is provided in a plane including the stacking (T) direction and the width (W) direction, where the position in the stacking (T) direction is between the first dielectric ceramic layers 20a and the position in the width (W) direction is between the second dielectric ceramic layer 20b and the third dielectric ceramic layers 41 and 42.

[0342] Thus, the stress generated in the second dielectric ceramic layer 20b during firing can be relieved by the defective portion 520. As a result, the generation of cracks and chipping in the second dielectric ceramic layer 20b can be suppressed.

[0343] In the multilayer ceramic capacitor 1 of the present invention, a segregation 530 of Si may be arranged in the defect portion 520. When the segregation 530 exists in the defect portion 520, the intrusion of moisture can be suppressed by the segregation 530. The presence of the segregation 530 in the defect portion 520 improves the moisture resistance of the multilayer ceramic capacitor 1. The segregation 530 may exist in the entire defect portion 520 or in a part of the defect portion 520. The defect portion 520 having the segregation 530 can suppress the generation of cracks and fragments in the second dielectric ceramic layer 20b, and can also improve the moisture resistance of the multilayer ceramic capacitor 1.

[0344] In the multilayer ceramic capacitor 1 of the present invention, the Si segregation 530 is equal to or greater than 1 / 3 (or less than 1 / 3) of the thickness of the second dielectric ceramic layer 20 b .

[0345] In the multilayer ceramic capacitor 1 of the present invention, the defect portion 520 is arranged near the first internal electrode layer 21 and the second internal electrode layer 22. Although the stress generated in the region near the first internal electrode layer 21 and the second internal electrode layer 22 during firing is relatively large, the stress is relieved by the defect portion 520, so that the generation of cracks and fragments can be effectively suppressed.

[0346] Preferably, in the multilayer ceramic capacitor 1 of the present invention, in the width direction, the size of the Si segregation 530 is not less than 0.1% and not more than 5% of the size of the third dielectric ceramic layers 41 and 42. When the Si segregation 530 exists in the defect portion 520, the generation of cracks and fragments can be effectively suppressed, and the moisture resistance of the multilayer ceramic capacitor 1 can also be improved.

[0347] (5) Segregation formed at the end of the second dielectric ceramic layer on the internal electrode layer side

[0348] like Fig.30 As shown, in the multilayer ceramic capacitor 1 of the present invention, the first segregation 610 may exist at the end of the first internal electrode layer 21 in the length (L) direction that is not connected to the second external electrode 52. In addition, the first segregation 610 may exist at the end of the second internal electrode layer 22 in the length (L) direction that is not connected to the first external electrode 51.

[0349] like Fig.31As shown, the first segregation 610 is generated by the metal element 610a originating from the second dielectric ceramic layer 20b segregating into a layered state. As the metal element 610a, for example, at least one of Mg, Mn, and Si can be cited. The segregation 610 caused by the metal element 610a is generated because the metal element contained in the second dielectric ceramic layer 20b moves to the first internal electrode layer 21 and the second internal electrode layer 22 during the firing of the second dielectric ceramic layer 20b.

[0350] On the other hand, Fig.32 As shown, the second segregation 620 may be present at the end of the first internal electrode layer 21 in the width (W) direction. In addition, the second segregation 620 may be present at the end of the second internal electrode layer 22 in the width (W) direction.

[0351] The second segregation 620 is generated by the segregation of metal elements 620a originating from the third dielectric ceramic layers 41 and 42 in contact with the first internal electrode layers 21 and the second internal electrode layers 22 in a layered manner. As the metal element 620a, for example, at least one of Mg, Mn, and Si can be cited as in the first segregation 610. The segregation 620 caused by the metal element 620a is generated because the metal element contained in the third dielectric ceramic layers 41 and 42 moves to the first internal electrode layers 21 and the second internal electrode layers 22 when the third dielectric ceramic layers 41 and 42 are fired.

[0352] Preferably, in the multilayer ceramic capacitor 1 of the present invention, regarding the first segregation 610 segregated to the first internal electrode layer 21, the first segregation 610 segregated to the second internal electrode layer 22, the second segregation 620 segregated to the first internal electrode layer 21, and the second segregation 620 segregated to the second internal electrode layer 22, the metal elements contained in at least one set of the segregations are different from the metal elements contained in the other segregations.

[0353] When the first dielectric ceramic layer 20a contains BaTiO3 as a main component, the content of the metal element contained in the first segregation 610 with respect to the first internal electrode layer 21 and the second internal electrode layer 22 is 0.3 mol% or more with respect to 100 mol of Ti. Similarly, the content of the metal element contained in the second segregation 620 with respect to the first internal electrode layer 21 and the second internal electrode layer 22 is 0.3 mol% or more with respect to 100 mol of Ti.

[0354] In the present invention, the region where the first segregation 610 exists in the first internal electrode layer 21 preferably has a length of 0.1 μm or more along the length (L) direction. In addition, the region where the first segregation 610 exists in the second internal electrode layer 22 preferably has a length of 0.1 μm or more along the length (L) direction. In addition, the region where the second segregation 620 exists in the first internal electrode layer 21 preferably has a length of 0.1 μm or more along the width (W) direction. In addition, the region where the second segregation 620 exists in the second internal electrode layer 22 preferably has a length of 0.1 μm or more along the width (W) direction. By having these lengths, the effect of improving reliability by suppressing electric field concentration by segregation can be reliably obtained.

[0355] If the length of the first segregation 610 and the second segregation 620 is shorter than the above-mentioned length, it becomes difficult to suppress the electric field concentration. In addition, in the case where the length (L) direction of the first segregation 610 exceeds 0.5%, and in the case where the width (W) direction of the second segregation 620 exceeds 1.0%, the segregated metal element (at least one of Mg, Mn, and Si) becomes excessive, and the function of storing charge in the internal electrode layer is reduced.

[0356] The length of the first segregation 610 in the length (L) direction can be controlled by adjusting the content of the metal element 610a contained in the second dielectric ceramic layer 20b and segregated by moving to the first internal electrode layer 21 and the second internal electrode layer 22. In addition, the length of the second segregation 620 in the width (W) direction can be controlled by adjusting the content of the metal element 620a contained in the third dielectric ceramic layers 41 and 42 and segregated by moving to the first internal electrode layer 21 and the second internal electrode layer 22.

[0357] In the multilayer ceramic capacitor 1 of the present invention, at the end of the first internal electrode layer 21 in the length (L) direction that is not connected to the second external electrode 52, and at the end of the second internal electrode layer 22 in the length (L) direction that is not connected to the first external electrode 51, there is a first segregation 610 caused by at least one metal element among Mg, Mn, and Si.

[0358] The electric field is easily concentrated at the ends of the first internal electrode layer 21 and the second internal electrode layer 22 in the length (L) direction that are in contact with the second dielectric ceramic layer 20b. If the electric field concentration occurs, the reliability of the multilayer ceramic capacitor may be reduced. However, the multilayer ceramic capacitor 1 of the present invention can suppress the electric field concentration by the first segregation 610, and can improve the reliability.

[0359] In the multilayer ceramic capacitor 1 of the present invention, second segregation 620 caused by at least one metal element of Mg, Mn, and Si exists at the ends of the first internal electrode layer 21 and the second internal electrode layer 22 in the width (W) direction.

[0360] The electric field is easily concentrated at the ends of the first internal electrode layer 21 and the second internal electrode layer 22 in the width (W) direction that are in contact with the third dielectric ceramic layers 41 and 42. If the electric field concentration occurs, the reliability of the multilayer ceramic capacitor may be reduced. However, the multilayer ceramic capacitor 1 of the present invention can suppress the electric field concentration by the second segregation 620, so that the reliability can be improved.

[0361] In the multilayer ceramic capacitor 1 of the present invention, regarding the first segregation 610 segregated to the first internal electrode layer 21, the first segregation 610 segregated to the second internal electrode layer 22, the second segregation 620 segregated to the first internal electrode layer 21, and the second segregation 620 segregated to the second internal electrode layer 22, the metal elements contained in at least one set of the segregations are different from the metal elements contained in the other segregations.

[0362] Thereby, it is possible to arrange the optimum metal element according to the locations where the first segregation 610 and the second segregation 620 are arranged, and reliability can be improved.

[0363] In the multilayer ceramic capacitor 1 of the present invention, the first dielectric ceramic layer 20a contains Ba and Ti, and the content of the metal element 610a contained in the first segregation 610 and the metal element 620a contained in the second segregation 620 relative to the internal electrode layer is 0.3 mol% or more relative to 100 mol of Ti.

[0364] This can effectively suppress the above-mentioned electric field concentration and further improve reliability.

[0365] In the multilayer ceramic capacitor 1 of the present invention, the area where the first segregation 610 exists in the first internal electrode layer 21 is preferably larger than 0.3 μm in the length (L) direction, the area where the first segregation 610 exists in the second internal electrode layer 22 is preferably larger than 0.3 μm in the length (L) direction, the area where the second segregation 620 exists in the first segregation 610 is preferably larger than 0.3 μm in the width (W) direction, and the area where the second segregation 620 exists in the second segregation 620 is preferably larger than 0.3 μm in the width (W) direction.

[0366] This can reliably achieve the effect of suppressing electric field concentration by segregation and improving reliability.

[0367] [Test Example 3]

[0368] Next, Test Example 3 for verifying the effects of the first segregation 610 and the second segregation 620 in the multilayer ceramic capacitor 1 of the present invention will be described.

[0369] As shown in Table 4, test examples 3-1 to 3-18 of laminated ceramic capacitors having a second dielectric ceramic layer 20b containing any one of the elements of Mg, Mn, and Si, and third dielectric ceramic layers 41 and 42 were prepared. Then, the concentration of the element of the first segregation generated at the end of the length (L) direction of the first internal electrode layer 21 and the second internal electrode layer 22, and the length in the length (L) direction and the length in the width (W) direction were investigated for each test example. The concentration of the metal element of the first segregation and the second segregation was investigated using the same method as the concentration of the second alloy part and the concentration of the third alloy part in the above-mentioned "Test Example 1". In addition, the length of each of the first segregation and the second segregation was measured by EDX analysis.

[0370] For the multilayer ceramic capacitors of Test Examples 3-1 to 3-18, the resistance value (kΩ) was measured in a state where a voltage of 6.3 V was applied for 1 hour at a temperature of 150°C, and then the MTTF (mean time to failure) was investigated. In addition, the presence or absence of a decrease in electrostatic capacitance was investigated using an LCR meter (manufactured by Keysight: E4980).

[0371] The case where the electrostatic capacitance decreased by 3% or more or the MTTF was less than 15.3 hr was marked as "×", the case where the electrostatic capacitance decreased by less than 3% and the MTTF exceeded 15.3 hr and was less than 30 hours was marked as "○" (good), and the case where the electrostatic capacitance decreased by less than 3% and the MTTF exceeded 30 hours was marked as "◎" (excellent). The results are recorded in Table 4.

[0372] [Table 4]

[0373]

[0374] By making the second dielectric layer contain Mg, Mn, and Si, segregation parts are formed at the ends of the internal electrode in the length direction and the width direction, thereby eliminating the main cause of reliability degradation that is easy to occur at the ends. However, if the content is too high, the area that functions as the metal of the internal electrode becomes narrower, resulting in a decrease in electrostatic capacitance.

[0375] (6) Segregation formed in the corner region of the second dielectric ceramic layer on the internal electrode layer side

[0376] In the case of the first segregation 610 and the second segregation 620, as Fig.33As shown, it is preferable that there is also a third segregation 630. The third segregation 630 exists in the first corner region 710 and the second corner region 720, respectively.

[0377] The first corner region 710 is a region in the first internal electrode layer 21 where the length (L) direction of the first segregation 610 and the width (W) direction of the second segregation 620 overlap. The second corner region 720 is a region in the second internal electrode layer 22 where the length (L) direction of the first segregation 610 and the width (W) direction of the second segregation 620 overlap. The third segregation 630 is generated by the segregation of the metal element 610a of the first segregation 610 and the metal element 620a of the second segregation 620.

[0378] Preferably, in the present invention, the metal elements 610a included in the first segregation 610 and the metal elements 620a included in the second segregation 620 are different from each other, and the metal elements 630a of the third segregation 630 include both the metal elements 610a included in the first segregation 610 and the metal elements 620a included in the second segregation 620.

[0379] Furthermore, in the present invention, preferably, the region where the first segregation 610 exists is 0.1 μm or more in the length (L) direction, and the region where the second segregation 620 exists is 0.1 μm or more in the width (W) direction.

[0380] Fig.33 The surface including the length (L) direction and the width (W) direction in the multilayer ceramic capacitor 1 of the present invention is shown. The third segregation 630 is preferably segregated in a substantially right triangle shape in the surface including the length (L) direction and the width (W) direction so that its existence area becomes larger toward the end in the length (L) direction. A part or all of the third segregation 630 is included in Fig.19 The area near the intersection 440.

[0381] In addition, preferably, in the multilayer ceramic capacitor 1 of the present invention, the second dielectric ceramic layer 20b is arranged relative to the first internal electrode layer 21 and the second internal electrode layer 22 so that a part thereof overlaps with the region where the third segregation 630 exists in the stacking (T) direction. Specifically, the following modes can be cited, namely, Fig.34 As shown, in the length (L) direction, the end of the second dielectric ceramic layer 120b overlaps the end of the second internal electrode layer 22 in the region including the third segregation 630. Similarly, the end of the second dielectric ceramic layer 20b may overlap the end of the first internal electrode layer 21. In this way, in the method of overlapping the ends in the length (L) direction, the end of the first internal electrode layer 121 or the end of the second dielectric ceramic layer 120b may overlap the end of the second dielectric ceramic layer 20b.

[0382] In the multilayer ceramic capacitor 1 of the present invention, at the end of the first internal electrode layer 21 in the length (L) direction not connected to the second external electrode 52, and at the end of the second internal electrode layer 22 in the length (L) direction not connected to the first external electrode 51, there is a first segregation 610 caused by at least one metal element among Mg, Mn, and Si, and at the end of the first internal electrode layer 21 in the width (W) direction, and at the end of the second internal electrode layer 22 in the width (W) direction, there is at least one metal element among Mg, Mn, and Si. The second segregation 620 is caused by the metal element, the first corner region 710 in the first internal electrode layer 21 where the end of the first segregation 610 in the length (L) direction overlaps with the end of the second segregation 620 in the width (W) direction, and the second corner region 720 in the second internal electrode layer 22 where the end of the first segregation 610 in the length (L) direction overlaps with the end of the second segregation 620 in the width (W) direction, respectively, and the third segregation 630 is caused by the metal elements of the first segregation 610 and the second segregation 620.

[0383] The electric field is easily concentrated in the first corner region 710 and the second corner region 720. If the electric field concentration occurs, the reliability of the multilayer ceramic capacitor may be reduced. However, the multilayer ceramic capacitor 1 of the present invention can suppress the electric field concentration in the first corner region 710 and the second corner region 720 through the third segregation 630, so the reliability can be improved.

[0384] In the multilayer ceramic capacitor 1 of the present invention, the metal element 610 a contained in the first segregation 610 and the metal element 620 a contained in the second segregation 620 are different from each other, and the metal element contained in the third segregation 630 includes both the metal element 610 a contained in the first segregation 610 and the metal element 620 a contained in the second segregation 620 .

[0385] Thus, the third segregation 630 can suppress the electric field concentration in the first corner region 710 and the second corner region 720, thereby improving reliability.

[0386] In addition, in the third segregation 630, as a metal element arranged on the side close to the third dielectric ceramic layers 41 and 42, Mg is preferred. On the other hand, in the third segregation 630, as a metal element arranged on the side close to the second dielectric ceramic layer 20b, Si is preferred from the viewpoint of the possibility of improving moisture resistance. Therefore, it is preferred that both Mg and Si are segregated in the first corner region 710 and the second corner region 720. In addition, short circuit recovery is possible by the first segregation 610 at the end of the width (W) direction of the first internal electrode layer 21 and the second internal electrode layer 22. In addition, it is further preferred that Sn is solid-dissolved in the first internal electrode layer 21 and the second internal electrode layer 22.

[0387] In the multilayer ceramic capacitor 1 of the present invention, the region where the first segregation 610 exists is 0.1 μm or more in the length (L) direction, and the region where the second segregation 620 exists is 0.1 μm or more in the width (W) direction. Thus, the effect of improving reliability by suppressing electric field concentration by segregation can be reliably obtained.

[0388] In the multilayer ceramic capacitor 1 of the present invention, in a plane including the length (L) direction and the width (W) direction, the region where the third segregation 630 exists increases toward the end in the length (L) direction.

[0389] Thus, the area of ​​the third segregation 630 in the end portion of the second dielectric ceramic layer 20b in the length (L) direction where electric field concentration is likely to occur is increased, and the third segregation 630 can more effectively suppress electric field concentration, thereby further improving reliability.

[0390] In the multilayer ceramic capacitor 1 of the present invention, the second dielectric ceramic layer 20 b is arranged relative to the first internal electrode layer 21 and the second internal electrode layer 22 so that a portion thereof overlaps with the region where the third segregation 630 exists in the stacking (T) direction.

[0391] This makes it easy to form the third segregation 630 so that its existing region becomes larger toward the end in the length (L) direction in a plane including the length (L) direction and the width (W) direction.

[0392] [Test Example 4]

[0393] Next, Test Example 4 for verifying the effect of the third segregation 630 in the multilayer ceramic capacitor 1 of the present invention will be described.

[0394] As shown in Table 5, test examples 4-1 to 4-18 of laminated ceramic capacitors having a second dielectric ceramic layer containing any one of the metal elements of Mg, Mn, and Si and a third dielectric ceramic layer containing any one of Mg, Mn, and Si were prepared. Then, the concentration of the metal element contained in the third segregation generated in the first corner region and the second corner region of each laminated ceramic capacitor and the length in the length (L) direction and the length in the width (W) direction were investigated. The concentration of the metal element in the third segregation was investigated using the same method as the concentration of the second alloy part and the concentration of the third alloy part in the above-mentioned "Test Example 1". In addition, the length of each third segregation was measured by EDX analysis.

[0395] For the multilayer ceramic capacitors of Test Examples 4-1 to 4-14, the resistance value (kΩ) was measured in a state where a voltage of 6.3V was applied at a temperature of 150°C, and the MTTF (mean time to failure) was investigated and determined. The MTTF is set as the time point when the resistance value becomes less than 10kΩ. When the MTTF is less than 15.3 hours (hr), it is judged as "×", and when it exceeds 15.3 hours (hr) and until 30 hours, it is judged as "○" (good), and when it exceeds 30 hours, it is judged as "◎" (excellent). The results are recorded in Table 5. In addition, the electrostatic capacitance is investigated by an LCR meter (manufactured by Keysight: E4980), and the case where the capacity decreases by more than 3% is judged as "×". In addition, with regard to the coverage of the internal electrode layer, when it is less than 80%, it becomes difficult to obtain the electrostatic capacitance, so it is set to be impossible to measure.

[0396] [Table 5]

[0397]

[0398] By making the second ceramic dielectric layer and the third ceramic dielectric layer contain Si, Mg, and Mn, many segregation regions can be formed at the corners. In particular, although it is easy to cause electric field concentration at the corners and reduce reliability, the reliability can be improved by forming segregation regions. However, if the content is too high, the area that functions as the metal of the internal electrode becomes narrower, resulting in a decrease in electrostatic capacitance.

[0399] (7) Thickness of the second dielectric ceramic layer

[0400] Fig.35 A WT cross section at the center of the length (L) direction of the laminated body 10 in the laminated ceramic capacitor 1 of the present invention is schematically shown, with T1 representing the thickness of the first dielectric ceramic layer 20a in the cross section and T2 representing the thickness of the end portions in the width (W) direction of the cross section.

[0401] also, Fig.36 FIG. 1 shows a portion of the LT cross section of the multilayer ceramic capacitor 1 of the present invention, where T3 is the thickness of the second dielectric ceramic layer 20b. Fig.36 , the second dielectric ceramic layer 20b in contact with the second internal electrode layer 22 is shown, but the thickness of the second dielectric ceramic layer 20b in contact with the first internal electrode layer 21 is also regarded as T3. In other words, the thickness T3 of the second dielectric ceramic layer 20b is the thickness between the end of the first internal electrode layer 21 in the length (L) direction that is not connected to the second external electrode 52 and the second external electrode 52, and between the end of the second internal electrode layer 22 in the length (L) direction that is not connected to the first external electrode 51 and the second external electrode 52, respectively.

[0402] In the present invention, the difference between the thicknesses of T1 and T2 is relatively small, being within 10% of T1. In contrast, the thickness of T3 is larger than that of T1 and T2, and the difference between them is preferably not less than 10% of T1 and T2.

[0403] There is no limitation on the method for making the thickness T3 of the second dielectric ceramic layer 20b thicker than the thicknesses T1 and T2 of the first dielectric ceramic layer 20a as described above, and this can be achieved, for example, by making the unfired green chip 110 so that the end of the unfired second dielectric ceramic layer 120b in the length (L) direction overlaps with the end of the unfired first internal electrode layer 121 and the unfired second internal electrode layer 122 in the length (L) direction, and then firing the green chip 110.

[0404] Among T1, T2, and T3, the thickness T1 of the center portion of the first dielectric ceramic layer 20a is preferably 0.7 μm or less. Also, the thickness T3 of the second dielectric ceramic layer 20b is preferably 0.4 μm or more.

[0405] In the multilayer ceramic capacitor 1 of the present invention, the thickness of the first dielectric ceramic layer 20a in the center of the stacking (T) direction in a plane including the center of the length (L) direction, the stacking (T) direction, and the width (W) direction is set to T1, the thickness of the end of the first dielectric ceramic layer 20a in the width (W) direction is set to T2, and the thickness between the end of the first internal electrode layer 21 in the length (L) direction not connected to the second external electrode 52 and the second external electrode 52, and between the end of the second internal electrode layer 22 in the length (L) direction not connected to the first external electrode 51 and the first external electrode 51 are set to T3, respectively. In this case, the difference between the thickness of T1 and T2 is within 10% of T1, and the thickness of T3 is larger than T1 and T2, and the difference is not less than 10% of T1 and T2.

[0406] Thus, between the first dielectric ceramic layers 20a sandwiching the first internal electrode layer 21 and the second internal electrode layer 22, the element thickness due to the second dielectric ceramic layer 20b arranged for eliminating the step has a sufficient thickness, resulting in improved reliability.

Claims

1. A multilayer ceramic capacitor comprising: a laminate including dielectric ceramic layers and internal electrode layers stacked in a stacking direction; and an external electrode connected to the internal electrode layer, In the multilayer ceramic capacitor, The stacked body comprises: a first main surface and a second main surface, which are opposite to each other in the stacking direction; a first side surface and a second side surface, which are opposite to each other in a width direction orthogonal to the stacking direction; and a first end surface and a second end surface, which are opposite to each other in a length direction orthogonal to the stacking direction and the width direction. The internal electrode layer includes: a first internal electrode layer extending to the first end surface; and a second internal electrode layer extending to the second end surface so as to face the first internal electrode layer via the dielectric ceramic layer. The external electrode includes: a first external electrode disposed on the first end surface and connected to the first internal electrode layer; and a second external electrode disposed on the second end surface and connected to the second internal electrode layer. The dielectric ceramic layer includes a first dielectric ceramic layer and a second dielectric ceramic layer, The first dielectric ceramic layer is disposed between the first internal electrode layer and the second internal electrode layer. The second dielectric ceramic layer is arranged to include a region where the internal electrode layer is not arranged between the first dielectric ceramic layers opposed to each other via the internal electrode layer, and a portion thereof overlaps with the first dielectric ceramic layer in the stacking direction. The laminate comprises: an inner layer portion, wherein the first inner electrode layer and the second inner electrode layer are alternately laminated with the dielectric ceramic layer interposed therebetween; an outer layer portion, which is arranged to sandwich the inner layer portion in the lamination direction and contains a ceramic material; and a third dielectric ceramic layer, which is arranged to sandwich the inner layer portion and the outer layer portion in the width direction and contains a dielectric ceramic material. The third dielectric ceramic layer includes a plurality of dielectric ceramic layers, including an inner layer disposed innermost in the width direction of the stacked body and an outer layer disposed outermost in the width direction of the stacked body. The inner layer contains at least one element among Si, Mg, and Mn, and the content of the element is higher than that of the first dielectric ceramic layer and the second dielectric ceramic layer. A first segregation derived from at least one element of Mg, Mn, and Si exists at an end portion of the first internal electrode layer in the longitudinal direction not connected to the second external electrode and at an end portion of the second internal electrode layer in the longitudinal direction not connected to the first external electrode.

2. The multilayer ceramic capacitor according to claim 1, wherein A defective portion in which a part of the second dielectric ceramic layer is defective is provided between the second dielectric ceramic layer and the third dielectric ceramic layer.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein: A defective portion in which a part of the second dielectric ceramic layer is defective is provided between the second dielectric ceramic layer and the third dielectric ceramic layer, and segregation of Si is arranged in the defective portion.

4. The multilayer ceramic capacitor according to claim 3, wherein: The segregation of Si is equal to or greater than 1 / 3 of the thickness of the second dielectric ceramic layer.

5. The multilayer ceramic capacitor according to claim 1 or 2, wherein: A defective portion in which a part of the second dielectric ceramic layer is defective is provided between the second dielectric ceramic layer and the third dielectric ceramic layer. The defective portion is arranged close to the internal electrode layer.

6. The multilayer ceramic capacitor according to claim 3, wherein: In the width direction, a size of the Si segregation is not less than 0.1% and not more than 5% of a size of the third dielectric ceramic layer.

7. The multilayer ceramic capacitor according to claim 1, wherein The content rate of Si in the said 3rd dielectric ceramic layer is 0.05 mol% or more and 5.0 mol% or less with respect to 100 mol of Ti.

8. The multilayer ceramic capacitor according to claim 1 or 7, wherein: The content rate of Mg in the said 3rd dielectric ceramic layer is 0.05 mol% or more and 5.0 mol% or less with respect to 100 mol of Ti.

9. The multilayer ceramic capacitor according to claim 1, wherein The content of Mn in the third dielectric ceramic layer is 0.01 mol % or more and 3.0 mol % or less relative to 100 mol of Ti.

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