Method for trimming chip parameter test values

Abstract

The application provides a chip parameter test value trimming method, which comprises the following steps: S1, setting the gear of the chip parameter test value of different regions on a wafer; S2, calculating the initial trimming gear of a to-be-tested chip according to the gears of the chips around the to-be-tested chip on the wafer by using a convolution operation; and S3, testing the parameter value of the to-be-tested chip and trimming the parameter test value according to the initial trimming gear of the to-be-tested chip. The initial trimming gear of the to-be-tested chip can be calculated in real time according to the gears of the chips around the to-be-tested chip, and the trimming gear can be accurately set when the processes of the multiple chips on the wafer are uneven.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for adjusting chip parameter test values. Background Technology

[0002] In the semiconductor technology field, multiple chips are simultaneously formed on a wafer using a specific process. Due to process deviations during chip manufacturing, all chip parameters eventually exhibit a normal distribution, affecting the accuracy of product parameters. Some parameters may exceed the range required by the product specifications, thus impacting product yield. To improve product parameter accuracy and yield, all parameters are typically measured after chip production, and key parameters are then adjusted based on the measurement results. This adjustment is performed during the Chip Probe testing phase, testing key parameters before chip packaging. There are usually multiple key parameters. The adjustment method involves adjusting the tested analog parameter values ​​to the nearest adjustment level. There are typically multiple adjustment levels, for example, 16. Therefore, setting the adjustment levels is a crucial step. The adjustment levels for each chip are calculated individually, and the analog parameter values ​​for each chip are tested and adjusted accordingly.

[0003] In existing technologies, two methods are used to set the adjustment level value. The first method is the three-point method. Since the values ​​of all adjustment levels increase linearly, it is necessary to test the values ​​of the first two adjustment levels to infer the value of the third adjustment level. The second method is the statistical distribution method. The adjustment level value that appears most frequently in the statistical distribution is then used as the adjustment level value for subsequent chips.

[0004] However, if the manufacturing process of each chip is not uniform, the simulated parameter values ​​may differ significantly. If the adjustment levels are set using the two existing methods, the resulting differences in adjustment may be large, leading to inaccurate adjustments. For example, Figure 1 Due to uneven manufacturing processes, the wafer is mainly divided into a first region 110 and a second region 120. The processes within the first region 110 and the second region 120 are similar, but the area of ​​the first region 110 is larger than that of the second region 120. The trimming method involves testing and trimming chips row by row, with each chip in each row undergoing parameter testing and trimming individually. If the first method is used, the trimming level of the chips in the second region 120 might be predicted and set based on the trimming level of the chips in the first region 110. If the second trimming method is used, the trimming level of the second region 120 might also be set based on the trimming level of the first region 110. This results in a significant difference between the trimming level of the second region 120 and the simulated parameter values. For example... Figure 2Besides the first region 110 and the second region 120, the wafer also has a boundary between the first region 110 and the second region 120. If the first method is used, the adjustment settings of the second region 120 chip and the boundary between the first and second regions 110 may be predicted and set according to the adjustment settings of the first region 110 chip. If the second adjustment method is used, the adjustment settings of the second region 120 and the boundary between the first and second regions 110 may also be set using the adjustment settings of the first region 110. Therefore, this leads to a large difference between the adjustment settings of the second region 120 and the simulated parameter values. For example... Figure 3 The third region, 130, is a relatively small area, almost a straight line. If the first method is used, the adjustment level of the chip in the third region, 130, might be predicted and set according to the adjustment level of the chip in the first region, 110. If the second adjustment method is used, the adjustment level of the third region, 130, might also be set using the adjustment level of the first region, 110. This results in a significant difference between the adjustment level of the third region, 130, and the simulated parameter value.

[0005] When there is a large difference between the adjustment setting and the analog parameter value, it cannot be adjusted directly. It is necessary to reset the adjustment setting for that area. The method is to test the analog parameter values ​​of three chips in that area, take the average value as the adjustment setting for that chip, which wastes a lot of testing time. Summary of the Invention

[0006] The purpose of this invention is to provide a method for adjusting chip parameter test values. When the processes of multiple chips on a wafer are not uniform, the adjustment level can be accurately set, thereby reducing the test time.

[0007] To achieve the above objectives, the present invention provides a method for adjusting chip parameter test values, comprising:

[0008] Step S1: Set the test value range for chip parameters in different areas of the wafer;

[0009] Step S2: Calculate the initial trimming position of the chip under test using a convolution operation based on the trimming positions of the chips surrounding the chip under test on the wafer;

[0010] Step S3: Test the parameter values ​​of the chip under test, and adjust the parameter test values ​​according to the initial adjustment setting of the chip under test.

[0011] Optionally, in the method for adjusting the chip parameter test values, the parameters include: current, voltage, and frequency.

[0012] Optionally, in the chip parameter test value adjustment method, the initial adjustment level of the chip under test in different regions may be the same or different.

[0013] Optionally, in the chip parameter test value adjustment method, the wafer has multiple chips, and the multiple chips are arranged in multiple rows and columns.

[0014] Optionally, in the chip parameter test value adjustment method, starting from the leftmost or rightmost chip, the chips are sequentially processed according to each row in steps S2 to S3.

[0015] Optionally, in the chip parameter test value adjustment method, if the chip under test is an edge chip, then the chips around the chip under test are filled in.

[0016] Optionally, in the chip parameter test value adjustment method, the initial adjustment level of the chip under test is calculated using a convolution operation based on the levels of the eight chips surrounding the chip under test on the wafer.

[0017] Optionally, in the chip parameter test value adjustment method, the initial adjustment level of the chip under test is calculated using a 3x3 convolution operation based on the level of the chips surrounding the chip under test on the wafer.

[0018] Optionally, in the chip parameter test value adjustment method, the initial adjustment level of the chip under test is calculated using a convolution operation based on the levels of the twenty-four chips surrounding the chip under test on the wafer.

[0019] Optionally, in the chip parameter test value adjustment method, the initial adjustment level of the chip under test is calculated using a 5x5 convolution operation based on the level of the chips surrounding the chip under test on the wafer.

[0020] In the chip parameter test value adjustment method provided by this invention, the method includes: Step S1: setting the chip parameter test value levels for different regions on the wafer; Step S2: calculating the initial adjustment level of the chip under test using a convolution operation based on the levels of the chips surrounding the chip under test on the wafer; Step S3: testing the parameter values ​​of the chip under test and adjusting the parameter test values ​​according to the initial adjustment level of the chip under test. This invention can calculate the initial adjustment level of the chip under test in real time based on the levels of the chips surrounding the chip under test. Even when the processes of multiple chips on the wafer are not uniform, the adjustment level is accurately set, reducing testing time. Attached Figure Description

[0021] Figures 1 to 3 This is a distribution diagram of wafer chips in existing technology;

[0022] Figure 4 This is a flowchart of a chip parameter test value adjustment method according to an embodiment of the present invention;

[0023] In the diagram: 110 - Area 1, 120 - Area 2, 130 - Area 3. Detailed Implementation

[0024] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0025] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.

[0026] Please refer to Figure 4 This invention provides a method for adjusting chip parameter test values, including:

[0027] Step S1: Set the test value range for chip parameters in different areas of the wafer;

[0028] Step S2: Calculate the initial trimming position of the chip under test using a convolution operation based on the trimming positions of the chips surrounding the chip under test on the wafer;

[0029] Step S3: Test the parameter values ​​of the chip under test, and adjust the parameter test values ​​according to the initial adjustment range of the chip under test.

[0030] In this embodiment of the invention, the parameters include: current, voltage, and frequency. Each parameter is tested separately, and the simulated parameter values ​​for each parameter are different, resulting in different actual gear settings. Each parameter is adjusted for gear settings separately.

[0031] In this embodiment of the invention, the initial trimming settings of the chips under test in different regions may be the same or different. If the chip manufacturing process on the wafer is uniform, the initial trimming settings of all chips will be similar or even the same. If they are not uniform, the initial trimming settings will differ; if the manufacturing processes of the chips differ greatly, the differences in the initial trimming settings may also be significant.

[0032] In this embodiment of the invention, the wafer has multiple chips arranged in multiple rows and columns. Starting from the leftmost or rightmost chip, the chips are sequentially processed according to steps S2 to S3, following the order of each row. Each chip requires adjustment of its analog parameter values. After the analog parameter values ​​of each chip are adjusted, the process proceeds to the next chip, until all chips are processed. The parameter adjustment steps for each chip are steps S2 to S3.

[0033] In one embodiment of the present invention, if the chip under test (DUT) is an edge chip, the chips surrounding the DUT are padded. The initial trimming position of the DUT is calculated using a convolution operation based on the trimming positions of the eight chips surrounding the DUT on the wafer. A 3x3 convolution operation is then used to calculate the initial trimming position of the DUT based on the trimming positions of the chips surrounding the DUT on the wafer. Essentially, in a 3x3 array, the chip in the middle is the DUT, and the top row, bottom row, leftmost column, and rightmost column are all surrounding chips, so the number of surrounding chips is eight. When the chip is the first leftmost chip in the first row, since the chips in the previous row and leftmost column are not present, the trimming positions in the previous row and leftmost column are padded. Then, the DUT moves to the right to the next chip, using the next chip as the center of the convolution kernel. Similarly, since the chips in the previous row are not present, the trimming positions of the chips in the previous row are padded, with the padded value being a set value. If the range values ​​of the chips surrounding the chip under test are already at the initial adjustment range obtained in step S2 (e.g., chips that have already undergone adjustment), then the actual range values ​​are used. If they have not yet undergone adjustment, then the range values ​​set in step S1 are used. This embodiment of the invention uses this method of calculating the initial adjustment range using a convolutional kernel to complete the adjustment of all chips, avoiding situations where there is a large difference between the adjustment range and the test value. Specifically, refer to... Figures 1 to 3 Compared to the first method in the prior art, this method avoids situations where the gear value of the second region is calculated entirely from the gear value of the first region, and also avoids situations where the gear values ​​of the second and / or third regions are calculated from the gear value of the first region. Compared to the second method in the prior art, it also avoids situations where the first, second, and third regions all use specific gear values. Using the method of this embodiment, the initial adjustment gear of the chip under test can be calculated in real time based on the gear values ​​of the chips surrounding the chip under test, resulting in a more accurate gear value. The adjusted parameter values ​​will also be more accurate.

[0034] In another embodiment of the present invention, the initial adjustment level of the chip under test (DUT) is calculated using a convolution operation based on the levels of the twenty-four chips surrounding the DUT on the wafer. A 5x5 convolution operation is also used to calculate the initial adjustment level of the DUT based on the levels of the chips surrounding the DUT on the wafer. The difference between Embodiment 2 and Embodiment 1 is that the number of surrounding chips used in Embodiment 2 to calculate the unit value of the DUT is different from that in Embodiment 1. However, the calculation method is the same, and the effect of Embodiment 2 compared to the prior art is the same as that of Embodiment 1. Embodiment 2 can also obtain a more accurate level value compared to Embodiment 1. The division of the first and second regions on the wafer may also be other cases, and the present invention does not specifically limit this. For the boundary between the first and second regions, if the level value obtained using the methods of Embodiments 1 and 2 is still large compared to the simulated parameter value obtained from the test, the level value is recalculated in the region where the difference between the level value and the simulated parameter value is large. The calculation method can be to select the level values ​​of the first two chips of the DUT in that region to calculate the level value of the DUT.

[0035] In other embodiments of the present invention, the number of surrounding chips used may be other than the number of chips used, so the number of convolution kernels may also be other than the number of kernels used. No further examples will be given here.

[0036] In summary, the chip parameter test value adjustment method provided in this embodiment of the invention includes: Step S1: setting the chip parameter test value levels for different regions on the wafer; Step S2: calculating the initial adjustment level of the chip under test using convolution operations based on the levels of the chips surrounding the chip under test on the wafer; Step S3: testing the parameter values ​​of the chip under test and adjusting the parameter test values ​​based on the initial adjustment level of the chip under test. This invention can calculate the initial adjustment level of the chip under test in real time based on the levels of the chips surrounding the chip under test. Even when the processes of multiple chips on the wafer are not uniform, the adjustment level is accurately set, reducing testing time.

[0037] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for adjusting chip parameter test values, characterized in that, include: Step S1: Set the test value range for chip parameters in different areas of the wafer; Step S2: Calculate the initial trimming position of the chip under test using a convolution operation based on the trimming positions of the chips surrounding the chip under test on the wafer; Step S3: Test the parameter values ​​of the chip under test, and adjust the parameter test values ​​according to the initial adjustment setting of the chip under test.

2. The method for adjusting chip parameter test values ​​as described in claim 1, characterized in that, The parameters include: current, voltage, and frequency.

3. The method for adjusting chip parameter test values ​​as described in claim 1, characterized in that, The initial adjustment settings of the chips under test in different regions may be the same or different.

4. The method for adjusting chip parameter test values ​​as described in claim 1, characterized in that, The wafer has multiple chips, which are arranged in multiple rows and columns.

5. The method for adjusting chip parameter test values ​​as described in claim 4, characterized in that, Starting with the first chip from the leftmost or rightmost position, proceed with the chip installation in each row according to steps S2 to S3.

6. The method for adjusting chip parameter test values ​​as described in claim 1, characterized in that, If the chip under test is an edge chip, then the chips around the chip under test will be filled in.

7. The method for adjusting chip parameter test values ​​as described in claim 1, characterized in that, The initial adjustment setting of the chip under test (DUT) is calculated using a convolution operation based on the settings of the eight chips surrounding the DUT on the wafer.

8. The method for adjusting chip parameter test values ​​as described in claim 7, characterized in that, The initial trimming position of the chip under test (DUT) is calculated using a 3x3 convolution operation based on the trim levels of the chips surrounding the DUT on the wafer.

9. The method for adjusting chip parameter test values ​​as described in claim 1, characterized in that, The initial adjustment setting of the chip under test is calculated using a convolution operation based on the settings of the twenty-four chips surrounding the chip under test on the wafer.

10. The method for adjusting chip parameter test values ​​as described in claim 9, characterized in that, The initial trimming position of the chip under test (DUT) is calculated using a 5x5 convolution operation based on the trim levels of the chips surrounding the DUT on the wafer.

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