High voltage electrostatic devices

Abstract

The present disclosure relates to high-voltage electrostatic discharge (ESD) devices. The present disclosure relates to semiconductor structures, and more particularly to improved on-state voltages and methods of manufacturing high-voltage ESD devices. The structure includes a high-voltage NPN having polysilicon material on an isolation structure at a base region, the polysilicon material extending to at least one of a collector and an emitter of a bipolar junction transistor (BJT), and the polysilicon material completely covering the base region of the BJT.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly to high voltage electrostatic discharge devices and methods of manufacturing the same. Background Art

[0002] Electrostatic discharge (ESD) devices protect integrated circuits from sudden currents caused by, for example, contact, electrical shorts, or dielectric breakdown. ESD devices can thus protect integrated circuits from malfunctioning.

[0003] ESD devices come in a variety of different configurations, such as resistors and fuses. In any of these configurations, the ESD device must operate within an ESD safety window with high current capabilities and a high holding voltage (Vh) for high-voltage applications. For example, the holding voltage must be higher than the operating voltage, or the device will fail to shut off. In this case, current will discharge, potentially damaging the integrated circuit.

[0004] However, meeting both high current performance and high holding voltage requirements for high voltage ESD is very challenging. For example, there is generally a trade-off between high current performance and high holding voltage. That is, conventional devices typically provide either high current performance or high holding voltage. For example, a high voltage PNP can provide relatively high holding voltage control but cannot provide high current performance; while a low voltage / high voltage silicon controlled rectifier (SCR) can provide relatively high current performance but cannot provide high holding voltage control. In particular, it is challenging to manufacture high voltage ESD devices for protecting high voltage output drivers because, due to the junction avalanche based triggering structure, many ESD devices do not turn on fast enough and the turn-on voltage is not low enough.

[0005] In known circuits, the delayed turn-on of high-voltage ESD devices (i.e., high turn-on voltages above the avalanche breakdown voltage) can damage core components (e.g., open-drain output drivers). Consequently, undesirable ESD outcomes can occur due to specific circuit failures caused by the high turn-on voltage. Summary of the Invention

[0006] In one aspect of the present disclosure, a structure includes a high voltage NPN having a polysilicon material on an isolation structure at a base region, the polysilicon material extending to at least one of a collector and an emitter of a bipolar junction transistor (BJT), and the polysilicon material completely covering the base region of the BJT.

[0007] In one aspect of the present disclosure, a structure includes a polysilicon material and a high voltage silicon controlled rectifier (SCR) located on an isolation structure at a base region, the polysilicon material extending to at least one of a collector and an emitter of a bipolar junction transistor (BJT), the polysilicon material completely covering the base region of the BJT, and the SCR located below an anode and in contact with the isolation structure.

[0008] In one aspect of the present disclosure, a method includes: forming an electrostatic high voltage device having a single polysilicon material located on an isolation structure; forming a bipolar junction transistor (BJT) having a base region completely covered by the single polysilicon material; and forming a buried layer to isolate the electrostatic high voltage device from a substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In the following detailed description, the present disclosure is described by way of non-limiting examples of exemplary embodiments of the present disclosure with reference to the several accompanying drawings mentioned.

[0010] Figures 1A to 1D Intermediate and final structures including high voltage electrostatic discharge (ESD) devices and corresponding manufacturing processes are shown according to some aspects of the present disclosure.

[0011] Figure 2 ESD devices according to further aspects of the present disclosure are shown.

[0012] Figure 3 Representatively shown by Figure 2 current of the ESD device.

[0013] Figures 4 to 7 ESD devices in various configurations according to further aspects of the present disclosure are shown.

[0014] Figures 8A to 8C A layout diagram of an ESD device according to some aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0015] The present disclosure relates to semiconductor structures, and more particularly to high-voltage electrostatic discharge (ESD) devices and methods of manufacturing the same. More specifically, the present disclosure provides a high-voltage ESD device having a high-voltage (HV) field MOSFET (i.e., field LDMOS). In an exemplary embodiment, the high-voltage ESD device includes a high-voltage NPN / PNP structure and a high-voltage silicon-controlled rectifier (SCR). Advantageously, as an example, the improved ESD device provides a fast turn-on time / low trigger voltage while maintaining a high DC breakdown voltage to protect the output driver.

[0016] More specifically, in some embodiments, polysilicon material can be provided at a field located in the base region and extending to the collector and emitter regions. For example, the ESD device can be a high voltage (HV) NPN and SCR having a single polysilicon located at a field located in the base region and extending to the collector / emitter doped regions. In this configuration, the field plate transistor effect can be utilized to cause the ESD transistor to turn on very early.

[0017] Furthermore, the ESD device may include various well dopings located below the polysilicon material, wherein in an embodiment, the polysilicon material is connected to an RC circuit. In this configuration, the Vt1 of the ESD device can be controlled by the p-well doping level and the field oxide thickness, and furthermore, the device can be turned on quickly only against ESD stress while maintaining a high DC breakdown voltage (DCBV) for normal operation. The ESD device may also include complementary metal-oxide-semiconductor (CMOS) / bipolar digital components and high voltage transistor (BCD) processes.

[0018] The ESD devices of the present disclosure can be manufactured in a variety of ways using a variety of different tools. However, in general, methods and tools are used to form structures with micrometer and nanometer dimensions. Methods (i.e., techniques) for manufacturing the ESD devices of the present disclosure have been adopted based on integrated circuit (IC) technology. For example, these structures are built on a wafer and implemented in a film of material patterned on top of the wafer using a photolithographic process. Specifically, the manufacture of the structure uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by photolithographic imaging; and (iii) selectively etching the film to the mask.

[0019] Figures 1A to 1D The intermediate and final structures of a high voltage ESD device according to some aspects of the present disclosure and the corresponding manufacturing process are shown. In particular, Figure 1A Structure 10 is shown including substrate 12. In embodiments, substrate 12 may be composed of any suitable semiconductor material including, but not limited to, Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors.

[0020] The substrate 12 includes an n+ region 14. In an embodiment, the n+ region 14 may be an n+ buried layer (NBL) formed by introducing dopants, for example, using an ion implantation process. In an embodiment, the NBL may be a continuous collector NBL. In the ion implantation process, the n+ region 14 may be formed by introducing a concentration of a dopant of an n+ dopant type into the substrate 12 using a patterned implantation mask to define selected areas exposed for implantation. The implantation mask may include a layer of photosensitive material, such as an organic photoresist layer, which is applied by a spin coating process, prebaked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer. The implantation mask has a thickness and blocking capability sufficient to prevent the masked areas from receiving a dose of implanted ions. The continuous n+ region 14 may be doped with an n-type dopant, such as arsenic (As), phosphorus (P), and Sb, among other suitable examples, at a dopant dose concentration of approximately 1E18 cm -3 to 5E20cm -3 .

[0021] Still refer to Figure 1A , epitaxial semiconductor material 16 may be grown on substrate 12, and preferably above n+ region 14. In an embodiment, epitaxial semiconductor material 16 may be an n-type semiconductor material. In an alternative embodiment, substrate 12 may be thicker, such that the upper portion is, for example, about 1E15 cm thick. -3 to 5E17cm -3 In either case, semiconductor material 16 can be used for a deep N-well structure as described in more detail herein.

[0022] A p-well 18 may be formed within semiconductor material 16 in electrical contact with n+ region 14. In an embodiment, p-well 18 is a high voltage p-well formed using a p-type dopant, such as boron (B). As with any well region described herein, high voltage p-well 18 may be formed by depositing an implant mask 20 (similar to the mask described above), followed by a patterning process to form an opening 22, and then, for example, at a rate of approximately 4E16 cm -3 to 2E18cm -3 An ion implantation process of a particular dopant type (e.g., a p-type dopant for a p-well) is performed at a concentration representatively shown by arrow 24. In an embodiment, p-well 18 may be a p-type high voltage double diffused drain (HVPDDD) formed using an ion implantation process with an appropriate implantation mask.

[0023] exist Figure 1BIn the embodiment, n-well 28 can be formed in semiconductor material 16 away from p-well 18. In other words, n-well 28 can be separated from p-well 18 by semiconductor material 16. In an embodiment, n-well 28 can be an n-type high voltage double diffused drain (HVNDDD) formed using an ion implantation process with an appropriate implantation mask, as described herein. In an embodiment, n-well 28 can have a thickness of, for example, about 5E15 cm -3 to 4E18cm -3 A lower dopant dose concentration is used to control the breakdown voltage.

[0024] Figure 1B Also shown is a shallow trench isolation structure 32 in the p-well 18, wherein the shallow trench isolation structure 30 spans between the wells 34 and 36. The shallow trench isolation structures 30 and 32 can be formed by conventional photolithography, etching, and deposition methods known to those skilled in the art. For example, a resist formed above the semiconductor material 16 is exposed to energy (light) to form a pattern (opening). Using an etching process with selective chemistry, such as reactive ion etching (RIE), one or more trenches are formed in the semiconductor material 16 through the openings in the resist. After the resist is removed by a conventional oxygen ashing process or other known stripping agent, an insulator material, such as an oxide, can be deposited in the trenches by any conventional deposition process, such as a chemical vapor deposition (CVD) process, to form the shallow trench isolation structures 30 and 32. Any residual insulator material on the surface of the semiconductor material 16 can be removed by a conventional chemical mechanical polishing (CMP) process.

[0025] In an embodiment, the lateral dimensions of the shallow trench isolation region can be adjusted to provide a high DC breakdown voltage and prevent lateral SCR. In addition, the shallow trench isolation structure 30 can be a local oxidation of silicon (LOCOS) structure. For example, the LOCOS structure 30 can be a process that forms silicon dioxide in selected areas on a silicon wafer, where the Si-SiO2 interface is located at a lower point than the rest of the silicon surface. In this embodiment, the LOCOS structure 30 extends between the p-well 18 and the n-well 28. As known to those skilled in the art, thermal treatment (e.g., dopant activation diffusion) for the high voltage well can be provided, and therefore, no further explanation is required to fully understand the present disclosure.

[0026] exist Figure 1C In the embodiment of the present invention, a p-well 34 and an n-well 36 can be formed in the semiconductor material 16. More specifically, the p-well 34 can be formed in the p-well 18, and the n-well 36 can be formed in the p-well 18 and the n-well 28. Likewise, the wells 34, 36 can be formed using a dopant concentration of, for example, about 1E17 cm -3 to 1E19cm -3The appropriate dopant type is formed by conventional ion implantation. In addition, the p+ doped region 38 can be formed in the p-well 18, and the n+ doped region 40 can be formed in the n-well 36; and the p+ doped region 38a and the n+ doped region 40a can be formed in the n-well 36 using corresponding p-type dopants and n-type dopants. In an embodiment, the n+ doped region 40 can be an emitter region. In addition, the combination of the p-well 34 and the p-well 18 can be a p-type base region. The p+ doped region 38 and the n+ doped region 40 can be formed with a higher dopant concentration (e.g., 5E19cm -3 to 5E21cm -3 ) doping. The structure may undergo a thermal treatment (eg, rapid thermal processing) for dopant activation and diffusion. Well doping may be used to control the Vt of the device.

[0027] Figure 1C Also shown is a polysilicon material 42 formed on the LOCOS or shallow trench isolation structure 30. A polysilicon material 44, such as a resistor, may be formed on the shallow trench isolation structure 32. In an embodiment, the polysilicon material 44 may be formed to have a thickness of, for example, approximately 1E18 cm -3 to 1E20cm -3 The polysilicon material 42 and the polysilicon material 44 may be formed by conventional deposition and patterning processes known to those skilled in the art, such as photolithography and etching methods, as described herein. For example, the polysilicon material 42 and the polysilicon material 44 may be formed by depositing and patterning a polysilicon layer.

[0028] like Figure 1D As further shown, a silicide blocking layer (SALPR) 46 can be formed over portions of the structure, including, for example, partially blocking n+ doped regions 40, 40a and partially blocking p+ doped region 38a. Those skilled in the art will appreciate that silicide blocking layer 46 can be formed using conventional deposition and patterning processes using materials that cannot be silicided. For example, silicide blocking layer 46 can be an oxide material or other insulator or blocking material, such as a nitride.

[0029] After forming the silicide barrier layer 46, a silicide process can be performed on the exposed portions of the semiconductor material 16 (e.g., the exposed portions of the doped regions 38, 38a, 40, 40a and the polysilicon material 42). The silicide process begins by depositing a thin layer of transition metal, such as nickel, cobalt, or titanium, over the fully formed and patterned device (e.g., the doped or ion-implanted regions 38, 38a, 40, 40a, 42). After the material is deposited, the structure is heated to cause the transition metal to react with the exposed silicon (or other semiconductor materials described herein) in the active regions of the device (e.g., the doped or ion-implanted regions 38a, 40, 40a), thereby forming a low-resistance transition metal silicide. After the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts in the active regions of the device.

[0030] After the silicide process, an insulator material 47 may be formed over the structure using a conventional deposition process for an oxide material, such as a chemical vapor deposition (CVD) process. The insulator material 47 undergoes a conventional etching (RIE) process to form openings that expose the silicide of the doped regions 38, 38a, 40, 40a and the polysilicon material 42. A contact metal (e.g., aluminum, tungsten, etc.) may be deposited within the openings of the insulator material 47 to form contacts that are in direct contact with the silicide of the regions 38, 38a, 40, 40a and the polysilicon 42.

[0031] In addition, resistor 48 can be connected to doped region 38 via a contact between polysilicon material 42 and p-well 38. In addition, a high voltage alternating polarity metal-oxide-metal (HV APMOM) capacitor 50 can be connected to doped region 40a via a contact (i.e., between doped region 40a and polysilicon material 42). In an embodiment, resistor 48 can have a resistance of, for example, approximately 100 kohm, thereby enabling fast triggering. In addition, capacitor 50 can have a high voltage of, for example, approximately 40 volts and a capacitance of, for example, approximately 2 pF. In an embodiment, the RC circuit can reduce ESD device conduction. In an embodiment, resistor 48 and capacitor 50 can be formed using conventional CMOS processes, so no further explanation is required to fully understand the present disclosure.

[0032] Figure 2 An ESD device according to another aspect of the present disclosure is shown. In particular, Figure 2 The ESD device 10a has a resistor 48 located on a contact of the cathode 52. For example, the resistor 48 can be located on a contact for the p+ doped region 38. In addition, the HV APMOM capacitor 50 can be located on a contact of the anode 54. The anode 54 receives the charge 58. For example, the HV APMOM capacitor 50 can be located on a contact of the n+ doped region 40a. Figure 2, dashed line 56 represents the ESD N field with a single polysilicon material 42 covering the entire base region and connected to the RC circuit (ie, resistor 48 and HV APMOM capacitor 50).

[0033] exist Figure 2 In the embodiment of the present invention, the ESD device 10a includes a high voltage SCR 49, 51 having a polysilicon material 42 (e.g., a single layer of polysilicon material) located on the field at the base region 43 and extending to the collector / emitter doping region 45. The high voltage SCR includes a PNPN region (i.e., p+ doped region 38a / n-type region (n-well 36, n-well 28, and semiconductor material 16 on the right) / p-type region (p-well 18 and p-well 34) / n-type region (n-well 36 and n+ doped region 40 on the left)). Specifically, the layer of polysilicon material 42 located on the field completely covers the base region 43 of the bipolar junction transistor (BJT) to enable the ESD transistor to turn on very early under the field plate transistor effect. In the ESD device 10a, an additional base doping level (e.g., p-well 34) can be located below the polysilicon material 42 field (i.e., LOCOS or shallow trench isolation structure 30). Therefore, the threshold voltage (ie, Vt1 ) of the ESD device 10 a can be controlled by the doping level of the p-well 34 and the thickness of the field oxide.

[0034] In the ESD device 10a, the single polysilicon material 42 can also be connected to the RC circuit (i.e., resistor 48 and HVAPMOM capacitor 50) to quickly turn on only for ESD stress, thereby maintaining a high dc breakdown voltage for normal operation. The ESD device 10a with the silicide barrier layer (SALPR) 46 in the collector and emitter regions has a high dc breakdown voltage that can be controlled to be as high as the base region junction design for high voltage applications. For high voltage applications, there is no need to worry about gate oxide (i.e., STI or The RC constant of the RC circuit (ie, resistor 48 and HV APMOM capacitor 50) can be adjusted to the response of the ESD device 10a to the rise time of the stress signal in different applications.

[0035] Figure 3 Representatively shown is the flow Figure 254 side of the device to the cathode 52 side of the device, the current flow is representatively shown by dashed arrow 60. In an embodiment, the current will flow through the p+ doped region 38a, the n-well 36, the n-well 28, the p-well 18, and the n+ doped region 40. It should be recognized by those skilled in the art that the current flow is similar in any of the devices described herein, for example, from the anode 54 side to the cathode 52 side of the ESD device 10a. To explain the conduction phase SCR, electrons move toward the anode 54 in the reverse current, as shown by arrow 62, and holes move toward the cathode 52 in the avalanche / multiplication, as shown by arrow 64. After avalanche and triggering the SCR, the current flow for the ESD discharge is represented by dashed arrow 60.

[0036] exist Figure 3 In the present disclosure, the ESD device 10a has a breakdown voltage of, for example, approximately 27 volts. In the present disclosure, the ESD device 10a can reduce the trigger voltage for the ESD stress signal compared to the high dc breakdown voltage of the ESD device 10a. In particular, when the ESD device 10a is under ESD stress, a high potential is generated. For example, the voltage can rise to more than 20 volts in an instant. When the ESD device 10a is under stress, the field transistor of the ESD device 10a can reduce the threshold voltage (i.e., Vt1). In addition, the field transistor threshold voltage (i.e., Vt) can be controlled by well doping.

[0037] Figure 4 FIG. 1 shows an ESD device 10b according to another aspect of the present disclosure. Specifically, Figure 4 The ESD device 10b is an electrostatic discharge device (ESD) high voltage NPN having a polysilicon material 42 extending to a collector / emitter doped region 45 on a local oxidation of silicon (LOCOS) or shallow trench isolation structure 30 at a base region 43. For example, the polysilicon material 42 on the LOCOS or shallow trench isolation structure 30 completely covers the base region 43 of a bipolar junction transistor (BJT). The n-type regions of the anode 54 and the cathode 52 are partially located below the polysilicon material 42 and the LOCOS or shallow trench isolation structure 30 to form a field transistor. In addition, for high voltage applications, there is no thin gate oxide below the polysilicon material 42.

[0038] In addition, Figure 4In the ESD device 10b of FIG. 1 , an additional base doping level (e.g., p-well 34) is located below the polysilicon material 42 and the LOCOS or shallow trench isolation structure 30 to control the threshold voltage (e.g., Vt). The polysilicon material 42 is connected to the RC circuit (i.e., resistor 48 and HV APMOM capacitor 50). The entire structure of the ESD device 10b is isolated from the substrate 12 by the n+ region 14. In addition, each of the doped regions (e.g., p+ doped regions 38, 38a and n+ doped regions 40, 40a) is different and separated by shallow trench isolation structures 30, 32. The remaining features are the same as those described with respect to FIG. Figure 1D or Figure 2 Same as described.

[0039] Figure 5 An ESD device 10c according to another aspect of the present disclosure is shown. Specifically, Figure 4 The ESD device 10b includes an SCR having a polysilicon material 42 extending to a collector / emitter doping region 45 on a local oxidation of silicon (LOCOS) or shallow trench isolation structure 30 at a base region 43; and Figure 5 In FIG, p+ doped region 38a is sandwiched between n+ doped regions 40a. The remaining features are the same as those of FIG. Figure 4 Same as described.

[0040] Figure 6 Another ESD device according to some aspects of the present disclosure is shown. Specifically, Figure 6 The ESD device 10d is an ESD high voltage PNP having a polysilicon material 42 extending to the collector / emitter region on a local oxidation of silicon (LOCOS) or shallow trench isolation structure 30 located at the base region. For example, the polysilicon material 42 on the LOCOS or shallow trench isolation structure 30 completely covers the base region of a bipolar junction transistor (BJT). The p-type regions of the anode 54 and cathode 52 are partially located below the polysilicon material 42 and the LOCOS or STI structure 30 to form a field transistor. In addition, for high voltage applications, there is no thin gate oxide below the polysilicon material 42. Figure 6 Also shown are p-well 70 , p-type high voltage double diffused drain (HVPDDD) 72 , n-type high voltage double diffused drain (HVNDDD) 74 , n-well 76 , and p-type epitaxial semiconductor material 78 .

[0041] and Figure 4 and Figure 5 compared to, Figure 6 and Figure 7A field N transistor with an RC circuit and a high voltage electrostatic discharge (ESD) device is applied. In addition, the ESD device 10d includes an additional base doping level (e.g., n-well 76) located below the polysilicon material 42 and the LOCOS or shallow trench isolation structure 30 to provide threshold voltage (e.g., Vt) control. In addition, the polysilicon material 42 is connected to the RC circuit (i.e., resistor 48 and HV APMOM capacitor 50). In addition, the overall structure of the ESD device 10d is isolated from the substrate 12 by the n+ region 14. The remaining features are the same as those described with respect to FIG. Figure 1D or Figure 2 Same as described.

[0042] Figure 7 An ESD device according to another aspect of the present disclosure is shown. Specifically, Figure 7 The ESD device 10e is an ESDSCR having a polysilicon material 42 extending to the collector / emitter region on a LOCOS or STI structure 30 at the base region. Figure 7 In FIG. 4 , n+ doped region 40a is sandwiched between p+ doped regions 38a. Figure 7 Also shown are p-well 70, p-type high voltage double diffused drain (HVPDDD) 72, n-type high voltage double diffused drain (HVNDDD) 74, n-well 76, and p-type epitaxial semiconductor material 78 (similar to Figure 6 ). The remaining features are the same as above. Figure 6 Same as described.

[0043] Figures 8A to 8C 1 shows a layout diagram of an ESD device according to some aspects of the present disclosure. Specifically, Figures 8A to 8C Shown Figure 4 The layout and cross-sectional view of the ESD device shown in FIG. Figure 8A This is a layout diagram without metal contact. Figure 8B is a layout diagram including the HV APMOM capacitor 50 with metal, Figure 8C is a cross-sectional view of the ESD device 10b (similar to Figure 4 ).exist( Figure 4 Lines are provided between the top view and the cross-sectional view of the structure shown to illustrate the relationship between the structures (e.g., p+ doped region 38, n+ doped regions 40, 40a, polysilicon material 42, polysilicon resistor 44, SALPR 46, and HV APMOM capacitor 50). Figure 8B In FIG. 5 , the HV APMOM capacitor 50 may include a gate metal 66 and a drain metal 68 and may be drawn as a FEOL device region to save area.

[0044] These ESD devices can be utilized in system-on-chip (SoC) technology. Those skilled in the art will appreciate that an SoC is an integrated circuit (also known as a "chip") that integrates all the components of an electronic system on a single chip or substrate. Because the components are integrated on a single substrate, an SoC consumes much less power and occupies much less area than a multi-chip design with equivalent functionality. As a result, SoCs are becoming a dominant force in the mobile computing (e.g., in smartphones) and edge computing markets. SoCs are also commonly used in embedded systems and the Internet of Things.

[0045] The above-described method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single-chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0046] The description of various embodiments of the present disclosure has been given for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the various embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure comprising a high voltage NPN having polysilicon material, the polysilicon material being bounded by a silicide barrier layer at the collector and emitter regions, the polysilicon material being located on an isolation structure at the base region, the polysilicon material extending to at least one of the collector and emitter of a bipolar junction transistor (BJT), and the polysilicon material completely covering the base region of the BJT; and an epitaxial semiconductor material located between the collector and base regions.

2. The structure according to claim 1, wherein The isolation structure extends between the wells connected to the anode and cathode. 3 . The structure of claim 2 , further comprising an n-type region of a field transistor located below the isolation structure. 4 . The structure of claim 3 , further comprising a p-dopant well located below the isolation structure.

5. The structure according to claim 4, wherein The polysilicon material is located only on the isolation structure.

6. The structure of claim 1 further comprising an RC circuit connected to the polysilicon material.

7. The structure according to claim 6, wherein The RC circuit includes a resistor connected to the cathode of the high voltage NPN.

8. The structure according to claim 6, wherein The RC circuit includes a high voltage alternating polarity metal-oxide-metal (HV APMOM) capacitor connected to the anode of the high voltage NPN.

9. The structure according to claim 6, further comprising: A silicon controlled rectifier (SCR) includes an NPN structure below an anode in an insulator material, the anode being connected to the RC circuit.

10. The structure according to claim 1, further comprising: A substrate is isolated from the rest of the high voltage NPN by an n+ buried layer.

11. A semiconductor structure comprising a polysilicon material and a silicon controlled rectifier (SCR), the polysilicon material being defined by a silicide barrier layer at the collector and emitter regions, the polysilicon material being located on an isolation structure at the base region, the polysilicon material extending to at least one of the collector and emitter of a bipolar junction transistor (BJT), the polysilicon material completely covering the base region of the BJT; and an epitaxial semiconductor material being located between the collector and base regions, the SCR being located below an anode in an insulator material, and the SCR being in contact with the isolation structure.

12. The structure according to claim 11, wherein The isolation structure includes one of a shallow trench isolation (STI) structure and a local oxidation of silicon (LOCOS) structure.

13. The structure of claim 12, further comprising a p-type region of a field transistor located below the isolation structure.

14. The structure of claim 13 further comprising an n-dopant well beneath the isolation structure.

15. The structure of claim 14 further comprising a high voltage NPN located below the anode in the insulator material.

16. The structure of claim 11 further comprising an RC circuit connected to the polysilicon material.

17. The structure according to claim 16, wherein The RC circuit includes a resistor connected to the cathode of the SCR.

18. The structure according to claim 16, wherein The RC circuit includes a high voltage alternating polarity metal-oxide-metal (HV APMOM) capacitor connected to the anode.

19. The structure of claim 11, further comprising: A substrate is isolated from the rest of the SCR by an n+ buried layer (NBL).

20. A method of forming a semiconductor structure, comprising: forming an electrostatic high voltage device having a single polysilicon material defined by silicide blocking layers at the collector and emitter regions, the single polysilicon material being located on an isolation structure; forming a bipolar junction transistor (BJT) having a base region and an epitaxial semiconductor material between a collector of the BJT and the base region, wherein the base region is completely covered by the single polysilicon material; as well as A buried layer is formed to isolate the electrostatic high voltage device from the substrate.

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