A high-density capacitor device with electrostatic protection and its manufacturing method
By interleaving TVS devices and capacitors in parallel within a silicon-based chip, the problems of performance loss and large-area installation during installation are solved, achieving miniaturization of high-density capacitors and improved electrostatic protection capabilities.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI CHANGYUAN WAYON MICROELECTRONICS
- Filing Date
- 2023-02-14
- Publication Date
- 2026-06-30
AI Technical Summary
In the prior art, when silicon-based capacitors and TVS devices are used in parallel, performance loss is easily caused during installation, the product has a large installation area, which affects the miniaturization of microelectronic devices and has consistency issues.
Several TVS devices and capacitors are integrated into the same silicon-based chip in an alternating parallel manner. By forming a deep trench structure with horizontal and vertical cross-sections, multiple preset regions are formed, and TVS devices and capacitors are connected in parallel. The chips are packaged with polysilicon layers and dielectric layers, and metal layers are used for electrode connection.
It achieves miniaturization of high-density capacitor components, strong electrostatic discharge capability, uniform electrostatic discharge channel, reduced warpage, improved capacitance density and electrostatic protection capability, simplified manufacturing process, and reduced cost.
Smart Images
Figure CN115985908B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a high-density capacitor device with electrostatic protection function and its preparation method. Background Technology
[0002] Silicon-based capacitors solve the problem of balancing capacitance and performance inherent in traditional capacitors. They offer advantages such as high capacitance density, low leakage current, high temperature resistance, high reliability, and high precision, and are currently widely used in ultra-miniature decoupling, high-frequency, and high-reliability applications. Furthermore, silicon-based capacitors are manufactured using semiconductor processes, resulting in high process compatibility and easily controllable costs.
[0003] A transient voltage suppressor (TVS) is a protective device used to absorb ESD energy and protect a system from ESD / Surge damage. It is generally used in the front stage of the protected system to clamp transient high voltage to a predetermined level, thereby protecting the downstream stage.
[0004] In electronic circuit applications, a voltage spike generated on the power line of a device can have a significant impact, especially for devices operating at relatively low DC voltages. This voltage spike can affect the normal operation of the circuit and even cause hardware damage. Current technology typically involves installing a capacitor at the power input of the device. While this capacitor is effective in eliminating voltage spikes, its voltage rating must be able to withstand them. If voltage division by a capacitor alone is insufficient, a TVS (Transient Voltage Suppressor) device can be used for clamping to reduce the surge voltage amplitude and limit the spike voltage to a certain level, thus protecting the circuit. By connecting a high-reliability, high-quality chip capacitor in parallel with a TVS device, the combined use of the TVS device and capacitor can achieve even better absorption of switching voltage spikes.
[0005] If discrete capacitors and TVS devices are directly soldered in parallel, the multiple soldering processes during installation can easily cause performance losses in both the capacitors and TVS devices, such as increased insertion loss in the capacitors. Furthermore, the large installation area of the product is not conducive to the miniaturization of microelectronic devices, and there are inconsistencies after installation. Even small differences in the installation process can lead to performance variations between products, resulting in significant differences in product performance after installation. Summary of the Invention
[0006] To address the above technical problems, this invention provides a high-density capacitor device with electrostatic protection and its manufacturing method.
[0007] The technical problem solved by this invention can be achieved by the following technical solutions:
[0008] A high-density capacitor integrated device with electrostatic discharge protection includes:
[0009] Several first deep trench structures are formed in a substrate to divide the substrate into multiple preset regions in a crisscross pattern. Several TVS devices and several capacitors are connected in parallel and staggered in the multiple preset regions.
[0010] Each of the TVS devices includes: a well region formed in the substrate; and a first heavily doped region formed in the well region;
[0011] Each of the capacitors includes: a plurality of second deep trench structures extending downward from the upper surface of the substrate and spaced apart in the substrate; and a second heavily doped region formed on the surface of the substrate having the plurality of second deep trench structures;
[0012] A dielectric layer is formed on the inner surface of the plurality of second deep trench structures and on the upper surface of the substrate;
[0013] A polycrystalline silicon layer is disposed on the upper surface of the dielectric layer in the corresponding region of the capacitor, and the polycrystalline silicon layer fills the plurality of second deep trench structures;
[0014] An insulating layer is disposed on the surface of the dielectric layer and the surface of the polysilicon layer, and the insulating layer is provided with contact hole windows corresponding to the polysilicon layer and contact hole windows corresponding to the first heavily doped region;
[0015] The metal layer includes a front metal layer disposed on the surface of the insulating layer and filling the contact hole window; and a back metal layer disposed on the lower surface of the substrate.
[0016] Preferably, the depth of the first deep groove structure is 10μm to 50μm.
[0017] Preferably, the conductivity type of the well region is N-type, and the conductivity type of the first heavily doped region is P-type; or
[0018] The conductivity type of the well region is P-type, and the conductivity type of the first heavily doped region is N-type.
[0019] Preferably, the depth of the second deep groove structure is less than the depth of the first deep groove structure.
[0020] Preferably, the depth of the second deep groove structure is 5μm to 30μm.
[0021] Preferably, the cross-sectional shape of the second deep groove structure is any one of strip, circle, square or regular polygon.
[0022] Preferably, the thickness of the polycrystalline silicon layer is 100nm to 900nm.
[0023] The present invention also provides a method for manufacturing a high-density capacitor device with electrostatic protection function, for manufacturing a high-density capacitor device with electrostatic protection function as described above, comprising:
[0024] Step S1: A first barrier layer is grown on the upper surface of a substrate, and then a plurality of first deep trench structures are formed and filled with insulating material to isolate the substrate into a plurality of preset regions in a crisscross pattern.
[0025] Step S2: A well region is formed in the substrate of the preset region corresponding to the plurality of TVS devices;
[0026] Step S3: Remove the first barrier layer and generate a new second barrier layer to form a plurality of second deep trench structures spaced apart in the substrate of the preset region corresponding to the plurality of capacitors;
[0027] Step S4: Remove the second barrier layer and form a first heavily doped region in the well region, and form a second heavily doped region on the substrate surface having the plurality of second deep trench structures;
[0028] Step S5: A dielectric layer is formed on the inner surface of the plurality of second deep trench structures and on the upper surface of the substrate;
[0029] Step S6: A polysilicon layer is formed on the upper surface of the dielectric layer in the region corresponding to the capacitor, and the polysilicon layer fills the plurality of second deep trench structures;
[0030] Step S7: Selectively perform photolithography on the polysilicon layer to retain the polysilicon layer in the regions corresponding to the plurality of second deep trench structures;
[0031] Step S8: An insulating layer is formed on the surface of the dielectric layer and the surface of the polysilicon layer, and then photolithography and etching are performed to form contact hole windows corresponding to the polysilicon layer and contact hole windows corresponding to the first heavily doped region.
[0032] Step S9: A front metal layer is formed on the surface of the insulating layer and inside the contact hole window;
[0033] Step S10: Deposit metal on the lower surface of the substrate and thin it to form a back metal layer.
[0034] Preferably, in step S2, the conductivity type of the well region is P-type, the implanted element of the well region is boron, the implantation dose is 1E13~1E14cm-2, the implantation energy is 60~150keV, and the implantation angle is 7 degrees.
[0035] Preferably, in step S3, the plurality of second deep trench structures are formed using a periodic etching-passivation-etching process.
[0036] The advantages or beneficial effects of the technical solution of this invention are as follows:
[0037] This invention integrates several three-dimensional capacitors and TVS devices in parallel and interleaved configurations within the same silicon-based chip through process compatibility. Several vertically arranged TVS devices are embedded between the segmented, horizontally and vertically interleaved three-dimensional capacitors. When used in conjunction with the capacitors, they better absorb switching voltage spikes, thereby protecting downstream circuits. The device has a high capacitance density, and the interleaved TVS devices make the electrostatic discharge channel more uniform and the electrostatic discharge capability stronger. The interleaved three-dimensional trench capacitors make the wafer stress distribution more uniform and the warpage smaller. Attached Figure Description
[0038] Figure 1a-1j This is a schematic diagram of each step in the fabrication method of a high-density capacitor integrated device with electrostatic protection function in a preferred embodiment of the present invention.
[0039] Figure 2 This is a schematic diagram of the equivalent circuit of the high-density capacitor integrated device with electrostatic protection function prepared in a preferred embodiment of the present invention.
[0040] Figure 3 This is a schematic diagram of a number of TVS devices and a number of capacitors arranged laterally in an alternating pattern in the prior art;
[0041] Figure 4 This is a schematic diagram of a plurality of TVS devices and a plurality of capacitors arranged in a crisscross pattern in a preferred embodiment of the present invention.
[0042] Figure 5 This is a schematic diagram of a high-density capacitor integrated device with electrostatic protection function prepared in another preferred embodiment of the present invention.
[0043] Figure 6 In another preferred embodiment of the present invention, an equivalent circuit diagram of the high-density capacitor integrated device with electrostatic protection function is provided. Detailed Implementation
[0044] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0045] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.
[0046] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.
[0047] Example 1
[0048] In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a high-density capacitor integrated device with electrostatic protection function is provided, belonging to the field of semiconductor technology. The device includes a substrate 1, a plurality of first deep trench structures 2, a plurality of TVS devices 100, a plurality of capacitors 101, a dielectric layer 7, a polysilicon layer 8, an insulating layer 9, a front metal layer 10, and a back metal layer 11. The TVS devices 100 include a well region 3 and a first heavily doped region 4. The capacitors 101 include a plurality of second deep trench structures 5 and a second heavily doped region 6. The second deep trench structures 5 are filled with the dielectric layer 7 and the polysilicon layer 8.
[0049] As shown in Figures 1-6, several first deep trench structures 2 are formed in a substrate 1 to divide the substrate 1 into multiple preset regions in a crisscross pattern. Several TVS devices 100 and several capacitors 101 are connected in parallel and staggered in the multiple preset regions.
[0050] Preferably, the substrate 1 should be an N-type substrate with low resistivity. Specifically, the substrate 1 includes one or more horizontally arranged first deep trench structures 2 and one or more vertically arranged first deep trench structures 2. Preferably, it includes at least two first deep trench structures 2, one horizontally arranged and the other vertically arranged, to divide the substrate 1 into at least four predetermined regions. A plurality of TVS devices 100 and a plurality of capacitors 101 are connected in parallel and staggered in the multiple predetermined regions, that is, one predetermined region is used to fabricate TVS devices 100, and its adjacent predetermined regions are used to fabricate capacitors 101.
[0051] Furthermore, before forming several first deep trench structures 2, a SiO2 barrier layer is first grown on the surface of the substrate 1. The thickness of the SiO2 barrier layer is 1 to 5 μm. Then, the region of the first deep trench structure 2 is defined by isolation deep trench photolithography. The first deep trench structure 2 extends from the upper surface of the substrate 1 to the lower surface. The depth of the first deep trench structure 2 is 10 to 50 μm. The first deep trench structure 2 is filled with silicon dioxide or other insulating materials.
[0052] Each TVS device 100 includes: a well region 3 formed in the substrate 1; and a first heavily doped region 4 formed in the well region 3;
[0053] Specifically, in the region of the TVS device 100 isolated by the first deep trench structure 2, well regions 3 are formed alternately by photolithography and ion implantation; then, a first heavily doped region 4 is formed within the well region 3 as the conductive region of the TVS device 100. Preferably, different TVS breakdown voltages can be achieved by adjusting the doping concentration of the first heavily doped region 4.
[0054] In a preferred embodiment, the conductivity type of the well region 3 can be either N-type or P-type, and the conductivity type of the first heavily doped region 4 is opposite to that of the well region 3.
[0055] If the conductivity type of well region 3 is P-type, then the conductivity type of the first heavily doped region 4 is N-type. In this case, the TVS device 100 formed is an NPN bidirectional diode structure. (See [link to relevant documentation]). Figure 2 .
[0056] If the conductivity type of well region 3 is N-type, then the conductivity type of the first heavily doped region 4 is P-type. In this case, the TVS device 100 is a PN-type unidirectional diode structure. See [link to relevant documentation]. Figure 6 .
[0057] Preferably, if the conductivity type of the well region 3 is P-type, the implanted element is boron, the implantation dose is 1E13~1E14cm-2, the implantation energy is 60~150keV, and the implantation angle is 7 degrees.
[0058] Each capacitor 101 includes: a plurality of second deep trench structures 5 extending downward from the upper surface of the substrate 1 and spaced apart in the substrate 1; and a second heavily doped region 6 formed on the surface of the substrate 1 having the plurality of second deep trench structures 52.
[0059] Specifically, before fabricating capacitor 101, the aforementioned SiO2 barrier layer is removed, and a new barrier layer is grown. On the aforementioned surface, the second deep trench structure 5 of capacitor 101 is etched by photolithography using the barrier layer. The second deep trench structure 5 extends from the upper surface of substrate 1 to the lower surface and is arranged in a spaced-out pattern. Then, the barrier layer is removed again. On the surface of substrate 1 in the predetermined region of capacitor 101 and on the unfilled surface of the second deep trench structure 5, N-type impurities are doped and pushed together using phosphorus oxychloride POCl3 to obtain an N+ type second heavily doped region 6, which serves as the conductive region of the lower electrode of capacitor 101.
[0060] As a preferred option, the formation of the second deep trench structure 5 adopts a periodic "etching-passivation-etching" process, which can effectively control the key dimensions and steepness of the trench etching, prevent the occurrence of long burrs, and has a high selectivity. The good trench morphology makes the capacitor have better reliability and higher withstand voltage.
[0061] Preferably, the thickness of the new second barrier layer is 1–5 μm. The barrier layer is selectively masked and etched, and the depth of the second deep trench structure 5 is 5–30 μm, and the depth of the second deep trench structure 5 is less than the depth of the first deep trench structure 2.
[0062] The dielectric layer 7 is formed on the inner surface of the plurality of second deep trench structures 5 and the upper surface of the substrate 1;
[0063] Specifically, the thickness of the dielectric layer 7 is 10 to 500 nm, and the dielectric layer 7 includes at least one of the following: silicon oxide, silicon nitride, and silicon oxynitride.
[0064] The dielectric layer 7 can be an oxide layer or a composite layer formed by multiple insulating dielectrics. Preferably, the dielectric layer 7 is a composite dielectric composed of oxide-nitride-oxide, such as SiO2-Si3N4-SiO2. This type of composite dielectric has advantages such as relatively high dielectric constant, high breakdown electric field, and low leakage current, thus effectively improving the capacitance and withstand voltage characteristics of the capacitor.
[0065] A polysilicon layer 8 is disposed on the upper surface of the dielectric layer 7 in the corresponding region of the capacitor 101, and the polysilicon layer 8 is filled with a plurality of second deep trench structures 5.
[0066] Specifically, a polysilicon layer 8 is grown on the surface of the dielectric layer 7 and within the second trench structure 5, filling the second trench structure 5 with polysilicon. Preferably, the thickness of the polysilicon layer 8 is 100–900 nm. Then, annealing is performed, with preferred annealing conditions of 850°C–950°C for 60–120 minutes. Next, selective photolithography is performed on the grown polysilicon layer 8 to etch the desired patterns, preserving the polysilicon within the second trench structure 5 and the polysilicon on the upper surface of the dielectric layer 7 corresponding to the capacitor 101.
[0067] The aforementioned polycrystalline silicon layer 8 can, on the one hand, serve as a conductive layer and make full contact with the dielectric layer 7 within the second deep trench structure 5, and on the other hand, it can fill the second deep trench structure 5, which is helpful for the subsequent electrode fabrication.
[0068] An insulating layer 9 is disposed on the surface of the dielectric layer 7 and the surface of the polysilicon layer 8. The insulating layer 9 has contact hole windows corresponding to the polysilicon layer 8 and contact hole windows corresponding to the first heavily doped region 4.
[0069] The metal layer includes a front metal layer 10 disposed on the surface of the insulating layer 9 and filling the contact hole window; and a back metal layer 11 disposed on the lower surface of the substrate 1.
[0070] Specifically, a front metal layer 10 is formed through metal deposition, followed by photolithography and etching, serving as the top electrode. This front metal layer 10 contacts the polysilicon layer 8 and the first heavily doped region 4 of the TVS device 100 through contact holes, and connects several capacitors 101 in parallel with the TVS device 100. Then, the back side of the substrate 1 is thinned to obtain the required chip thickness, and a back metal layer 11 is sputtered to form, serving as the bottom electrode.
[0071] Preferably, the metal deposited in the metal layer can be pure aluminum or an aluminum-silicon compound; more preferably, it is a three-layer composite structure, consisting of titanium, titanium nitride, and aluminum-silicon-copper layers from bottom to top.
[0072] In a preferred embodiment, the cross-sectional shape of the second deep groove structure 5 is any one of strip, circle, square or regular polygon.
[0073] Using the above technical solution, the present invention integrates several three-dimensional capacitors 101 and TVS devices 100 in parallel and interleaved configurations within the same silicon-based chip through process compatibility. Several vertically arranged TVS devices 100 are embedded between the segmented, horizontally and vertically interleaved three-dimensional capacitors 101, working in conjunction with the capacitors 101 to better absorb switching voltage spikes and protect downstream circuits. The devices have high capacitance density, and the interleaved TVS devices 100 make the electrostatic discharge channel more uniform and the electrostatic discharge capability stronger. The interleaved three-dimensional trench capacitors 101 make the wafer stress distribution more uniform and the warpage smaller.
[0074] Example 2
[0075] The present invention also provides a method for manufacturing a high-density capacitor device with electrostatic protection function, for manufacturing a high-density capacitor device with electrostatic protection function as described above, comprising:
[0076] Step S1, as follows Figure 1a As shown, a first barrier layer is grown on the upper surface of a substrate 1, and then several first deep trench structures 2 are formed and filled with insulating material to isolate the substrate 1 into multiple predetermined areas in a crisscross pattern.
[0077] Specifically, a silicon substrate is used as the substrate 1 material, a SiO2 barrier layer is grown on its upper surface, and then the isolation trench region is defined by isolation trench photolithography, with the trench extending from the upper surface of the substrate 1 to the lower surface.
[0078] Preferably, the substrate 1 should be an N-type substrate with low resistivity, and the thickness of the first barrier layer is 1 to 5 μm. The barrier layer is selectively masked and etched to form a first deep trench with a depth of 10 to 50 μm on the upper surface of the substrate 1, and the first deep trench is filled with silicon dioxide or other insulating material to form a first deep trench structure 2 with an isolation function.
[0079] Step S2, as follows Figure 1b As shown, a well region 3 is formed in a substrate 1 in a predetermined region corresponding to a plurality of TVS devices 100;
[0080] Specifically, in the region of the TVS device 100 isolated by the first deep trench structure 2, P-type well regions 3PW are formed alternately by photolithography and ion implantation.
[0081] Preferably, the PW implantation element is boron, the implantation dose is 1E13~1E14cm-2, the implantation energy is 60~150keV, and the implantation angle is 7 degrees.
[0082] Step S3, as follows Figure 1c As shown, the first barrier layer in step S1 is removed and a new second barrier layer is generated, forming multiple second deep trench structures 5 spaced apart in the substrate 1 of the preset area corresponding to the capacitors 101.
[0083] Specifically, on the aforementioned surface, the second deep trench structure 5 of the capacitor 101 is etched by photolithography through the second barrier layer. The second deep trench structure 5 extends from the upper surface of the substrate 1 to the lower surface and is arranged in a crisscross pattern.
[0084] Preferably, the capacitor trench is generated using a periodic "etch-passivation-etch" process, which can effectively control the key dimensions and steepness of the trench etching, prevent long spikes from appearing, and has a high selectivity. The good trench morphology gives the capacitor better reliability and higher withstand voltage.
[0085] Preferably, the thickness of the second barrier layer is 1–5 μm. The barrier layer is selectively masked and etched to form several trench structures with a depth of 5–30 μm on the surface of the capacitor region, and the depth of the trenches is less than the depth of the isolation trenches.
[0086] Step S4, as follows Figure 1d As shown, the second barrier layer is removed, and a first heavily doped region 4 is formed in the well region 3, and a second heavily doped region 6 is formed on the surface of the substrate 1 having a plurality of second deep trench structures 5.
[0087] Specifically, the barrier layer is removed again, forming a first heavily doped region 4 within the well region 3, which serves as the conductive region of the TVS device 100. Preferably, different TVS breakdown voltages can be achieved by adjusting the doping concentration of the first heavily doped region 4. Simultaneously, phosphorus oxychloride (POCl3) is used to dope and push N-type impurities onto the surface of the substrate 1 in the preset region of the capacitor 101 and the surface of the unfilled second deep trench structure 5, resulting in an N+ type second heavily doped region 6, which serves as the conductive region of the lower electrode of the capacitor 101.
[0088] Step S5, as follows Figure 1e As shown, a dielectric layer 7 is formed on the inner surface of the plurality of second deep trench structures 5 and the upper surface of the substrate 1;
[0089] Specifically, the thickness of the dielectric layer 7 is 10 to 500 nm, and the dielectric layer 7 includes at least one of the following: silicon oxide, silicon nitride, and silicon oxynitride.
[0090] The dielectric layer 7 can be an oxide layer or a composite layer formed by multiple insulating dielectrics. Preferably, the dielectric layer 7 is a composite dielectric composed of oxide-nitride-oxide, such as SiO2-Si3N4-SiO2. This type of composite dielectric has advantages such as relatively high dielectric constant, high breakdown electric field, and low leakage current, thus effectively improving the capacitance and withstand voltage characteristics of the capacitor.
[0091] Step S6, as follows Figure 1f As shown, a polysilicon layer 8 is formed on the upper surface of the dielectric layer 7 in the region corresponding to the capacitor 101, and the polysilicon layer 8 is filled with a plurality of second deep trench structures 5.
[0092] Specifically, a polycrystalline silicon layer 8 is grown on the surface of the dielectric layer 7 and within the second deep trench structure 5, so that the second deep trench structure 5 is filled with polycrystalline silicon. Preferably, the thickness of the polycrystalline silicon layer 8 is 100–900 nm. Then, annealing is performed, with the preferred annealing conditions being a temperature of 850°C–950°C and a time of 60–120 minutes.
[0093] Step S7, as follows Figure 1g As shown, the polysilicon layer 8 is selectively photolithographically ...
[0094] Specifically, the grown polysilicon layer 8 is selectively photolithographically etched to create the desired pattern, while retaining the polysilicon within the second deep trench structure 5 and the polysilicon on the upper surface of the dielectric layer 7 corresponding to the capacitor 101.
[0095] The aforementioned polycrystalline silicon layer 8 can, on the one hand, serve as a conductive layer and make full contact with the dielectric layer 7 within the second deep trench structure 5, and on the other hand, it can fill the second deep trench structure 5, which is helpful for the subsequent electrode fabrication.
[0096] Step S8, as follows Figure 1h As shown, an insulating layer 9 is formed on the surface of the dielectric layer 7 and the surface of the polysilicon layer 8, and then photolithography and etching are used to form contact hole windows corresponding to the polysilicon layer 8 and contact hole windows corresponding to the first heavily doped region 4.
[0097] Step S9, as follows Figure 1i As shown, a front metal layer 10 is formed on the surface of the insulating layer 9 and inside the contact hole window;
[0098] Specifically, metal deposition is performed, and then a front metal layer 10 is formed by photolithography and etching, which serves as the top electrode. The front metal layer 10 contacts the polysilicon layer 8 and the first heavily doped region 4 of the TVS device 100 through contact holes, and connects several capacitors 101 in parallel with the TVS device 100.
[0099] Preferably, the metal deposited in the metal layer can be pure aluminum or an aluminum-silicon compound; more preferably, it is a three-layer composite structure, consisting of titanium, titanium nitride, and aluminum-silicon-copper layers from bottom to top.
[0100] Step S10, as follows Figure 1j As shown, metal is deposited on the lower surface of substrate 1 and thinned to obtain the required chip thickness, forming a back metal layer as the bottom electrode.
[0101] In a preferred embodiment, in step S2, the conductivity type of the well region 3 is P-type, the implanted element of the well region 3 is boron, the implantation dose is 1E13~1E14cm-2, the implantation energy is 60~150keV, and the implantation angle is 7 degrees.
[0102] In a preferred embodiment, in step S3, the plurality of second deep trench structures 5 are formed using a periodic etching-passivation-etching process.
[0103] Specifically, the formation of the second deep trench structure 5 adopts a periodic "etching-passivation-etching" process, which can effectively control the key dimensions and steepness of the trench etching, prevent long burrs from occurring, and has a high selectivity. The good trench morphology makes the capacitor more reliable and has a higher withstand voltage.
[0104] Example 3
[0105] Based on Example 1, the doping types of the well region 3 and the first heavily doped region 4 in the TVS device 100 are changed, such as... Figure 5 As shown, ion implantation is performed sequentially on the preset region corresponding to the TVS device 100 to form an N-type well region (NW) and a P+ type heavily doped region. See also... Figure 6 The TVS device 100 is an NPN bidirectional diode structure that is transformed into a PN unidirectional diode structure, which can realize ESD protection from the back of the chip to the front and can be flexibly applied to the required circuit.
[0106] The above technical solution has the following advantages or beneficial effects: This invention integrates several three-dimensional capacitors and TVS devices in parallel and interleaved configurations within the same silicon-based chip through process compatibility. Several vertically arranged TVS devices are embedded between the segmented, horizontally and vertically interleaved three-dimensional capacitors, working in conjunction with the capacitors to better absorb switching voltage spikes and protect downstream circuits. The device has high capacitance density, while the interleaved TVS devices make the electrostatic discharge channel more uniform and the electrostatic discharge capability stronger. The interleaved three-dimensional trench capacitors make the wafer stress distribution more uniform and the warpage smaller. At the same time, the manufacturing process is compatible, requires fewer photolithography steps, is simple, low-cost, safe, and reliable.
[0107] The embodiments of the present invention can avoid the performance loss of the device caused by multiple soldering processes during the assembly of discrete devices, and are conducive to the miniaturization of the device. The resulting device has the characteristics of small size, large capacitance density, long life, high reliability and high temperature resistance. The device provided by the present invention can be applied to various applications of embedded capacitors.
[0108] Furthermore, the number, shape, aspect ratio, distribution pattern, and distribution density of the second isolation structure of the capacitor in the embodiments of the present invention can be varied according to different requirements, thereby satisfying the capacitance density requirements of different capacitors. In the present invention, the TVS device can achieve various types of ESD protection, such as unidirectional, bidirectional, and negative resistance types, through structural changes.
[0109] The above description is merely a preferred embodiment of the present invention and does not limit the implementation and protection scope of the present invention. Those skilled in the art should realize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.
Claims
1. A high-density capacitor integrated device with electrostatic protection function, characterized by, include: Several first deep trench structures are formed in a substrate to divide the substrate into multiple preset regions in a crisscross pattern. Several TVS devices and several capacitors are connected in parallel and staggered in the multiple preset regions. Each of the TVS devices includes: a well region formed in the substrate; and a first heavily doped region formed in the well region; Each of the capacitors includes: a plurality of second deep trench structures extending downward from the upper surface of the substrate and spaced apart in the substrate; and a second heavily doped region formed on the surface of the substrate having the plurality of second deep trench structures; A dielectric layer is formed on the inner surface of the plurality of second deep trench structures and on the upper surface of the substrate; A polycrystalline silicon layer is disposed on the upper surface of the dielectric layer in the corresponding region of the capacitor, and the polycrystalline silicon layer fills the plurality of second deep trench structures; An insulating layer is disposed on the surface of the dielectric layer and the surface of the polysilicon layer, and the insulating layer is provided with contact hole windows corresponding to the polysilicon layer and contact hole windows corresponding to the first heavily doped region; The metal layer includes a front metal layer disposed on the surface of the insulating layer and filling the contact hole window; and a back metal layer disposed on the lower surface of the substrate.
2. The high-density capacitor integrated device with electrostatic protection function according to claim 1, wherein, The depth of the first deep groove structure is 10μm to 50μm.
3. The high-density capacitor integrated device with electrostatic protection function according to claim 1, characterized in that, The well region has an N-type conductivity, and the first heavily doped region has a P-type conductivity; or The conductivity type of the well region is P-type, and the conductivity type of the first heavily doped region is N-type.
4. The high-density capacitor integrated device with electrostatic protection function according to claim 1, characterized in that, The depth of the second deep groove structure is less than the depth of the first deep groove structure.
5. The high-density capacitor integrated device with electrostatic protection function according to claim 1, characterized in that, The depth of the second deep groove structure is 5μm to 30μm.
6. The high-density capacitor integrated device with electrostatic protection function according to claim 1, characterized in that, The cross-sectional shape of the second deep groove structure can be any one of strip, circle, square or regular polygon.
7. The high-density capacitor integrated device with electrostatic protection function according to claim 1, characterized in that, The thickness of the polycrystalline silicon layer is 100nm to 900nm.
8. A method for manufacturing a high-density capacitor with electrostatic protection function, characterized in that, For manufacturing a high-density capacitor device with electrostatic protection as described in any one of claims 1-7, comprising: Step S1: A first barrier layer is grown on the upper surface of a substrate, and then a plurality of first deep trench structures are formed and filled with insulating material to isolate the substrate into a plurality of preset regions in a crisscross pattern. Step S2: A well region is formed in the substrate of the preset region corresponding to the plurality of TVS devices; Step S3: Remove the first barrier layer and generate a new second barrier layer to form a plurality of second deep trench structures spaced apart in the substrate of the preset region corresponding to the plurality of capacitors; Step S4: Remove the second barrier layer and form a first heavily doped region in the well region, and form a second heavily doped region on the substrate surface having the plurality of second deep trench structures; Step S5: A dielectric layer is formed on the inner surface of the plurality of second deep trench structures and on the upper surface of the substrate; Step S6: A polysilicon layer is formed on the upper surface of the dielectric layer in the region corresponding to the capacitor, and the polysilicon layer fills the plurality of second deep trench structures; Step S7: Selectively perform photolithography on the polysilicon layer to retain the polysilicon layer in the regions corresponding to the plurality of second deep trench structures; Step S8: An insulating layer is formed on the surface of the dielectric layer and the surface of the polysilicon layer, and then photolithography and etching are performed to form contact hole windows corresponding to the polysilicon layer and contact hole windows corresponding to the first heavily doped region. Step S9: A front metal layer is formed on the surface of the insulating layer and inside the contact hole window; Step S10: Deposit metal on the lower surface of the substrate and thin it to form a back metal layer.
9. The method for preparing a high-density capacitor with electrostatic protection function according to claim 8, characterized in that, In step S2, the conductivity type of the well region is P-type, the implanted element of the well region is boron, the implantation dose is 1E13~1E14cm-2, the implantation energy is 60~150keV, and the implantation angle is 7 degrees.
10. The method for preparing a high-density capacitor device with electrostatic protection function according to claim 8, characterized in that, In step S3, the plurality of second deep trench structures are formed using a periodic etching-passivation-etching process.