Light-emitting diode with improved voltage anomaly and preparation method thereof

Abstract

The present disclosure provides a light-emitting diode (LED) with improved voltage anomalies and a method for preparing the same, which belongs to the field of optoelectronic manufacturing technology. The light-emitting diode includes: a substrate, an epitaxial layer, an electrode, a passivation layer, and a solder block. The epitaxial layer is located on the substrate, the electrode is located on the surface of the epitaxial layer away from the substrate, and the passivation layer is located on the surface of the epitaxial layer away from the substrate and covers part of the surface of the electrode. The electrode includes a first metal layer and a second metal layer sequentially stacked on the epitaxial layer, the first metal layer includes Au metal, the second metal layer does not include Au metal, the passivation layer has a through hole exposing the surface of the second metal layer, the surface of the second metal layer has a countersunk hole, and the through hole is connected to the countersunk hole. The solder block is attached to the surface of the passivation layer away from the substrate and is connected to the second metal layer in sequence through the through hole and the countersunk hole. The embodiment of the present disclosure can improve the problem of high voltage easily formed on the contact surface between the solder block and the electrode, and improve the yield of the light-emitting diode.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light emitting diode capable of improving voltage anomaly and a preparation method thereof. Background Art

[0002] Light emitting diodes (LEDs) are a highly influential new product in the optoelectronics industry. They have the characteristics of small size, long service life, rich colors, and low energy consumption. They are widely used in lighting, display screens, signal lights, backlight sources, toys and other fields.

[0003] In related technologies, a light-emitting diode generally includes a substrate, an epitaxial layer, an electrode, a passivation layer, and a solder joint block. The substrate, epitaxial layer, and electrode are stacked in sequence. The passivation layer is located on the surface of the epitaxial layer and covers the electrode. The surface of the passivation layer has a through hole exposed by etching, and the solder joint block is located on the surface of the passivation layer and is connected to the electrode through the through hole.

[0004] However, since the electrode is located below the passivation layer, it is easily etched during the process of etching the passivation layer to form a through hole, thereby exposing the Au metal in the electrode. When making solder bumps, it is necessary to go through the passivation layer degumming, solder bump photolithography, glue application and flushing processes. The exposed Au in the electrode will absorb other substances to form compounds during these processes, thereby forming a slight base film on the surface of Au. After the solder bump is formed by vapor deposition in the through hole, the base film on the surface of Au will affect the contact between the solder bump and Au. After power is applied, a high voltage is generated between the contact surface of the solder bump and Au, affecting the yield of the light-emitting diode. Summary of the Invention

[0005] The present disclosure provides a light-emitting diode with improved voltage anomaly and a method for manufacturing the same, which can improve the problem of high voltage easily forming on the contact surface between the solder joint block and the electrode, and improve the yield of the light-emitting diode. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a light-emitting diode, which includes: a substrate, an epitaxial layer, an electrode, a passivation layer and a solder block, wherein the epitaxial layer is located on the substrate, the electrode is located on the surface of the epitaxial layer away from the substrate, and the passivation layer is located on the surface of the epitaxial layer away from the substrate and covers a portion of the surface of the electrode; the electrode includes a first metal layer and a second metal layer stacked in sequence on the epitaxial layer, the first metal layer includes Au metal, and the second metal layer does not include Au metal, the passivation layer has a through hole exposing the surface of the second metal layer, the surface of the second metal layer has a countersunk hole, and the through hole is connected to the countersunk hole; the solder block is attached to the surface of the passivation layer away from the substrate and is connected to the second metal layer through the through hole and the countersunk hole in sequence.

[0007] Optionally, the second metal layer includes a first Ti layer, a Pt layer, and a second Ti layer stacked in sequence, and the bottom of the countersunk hole is located in the Pt layer.

[0008] Optionally, the thickness of the first Ti layer and the second Ti layer are both in a range of 100 angstroms to 400 angstroms, and the thickness of the Pt layer is in a range of 1000 angstroms to 3000 angstroms.

[0009] Optionally, the first metal layer includes a first Au layer, an AuGeNi alloy layer, and a second Au layer stacked in sequence; or, the first metal layer includes a first Au layer, an AuBe alloy layer, and a second Au layer stacked in sequence.

[0010] Optionally, the thickness of the first Au layer ranges from 100 angstroms to 400 angstroms, the thickness of the second Au layer ranges from 1000 angstroms to 4500 angstroms; the thickness of the AuGeNi alloy layer ranges from 1000 angstroms to 3000 angstroms, or the thickness of the AuBe alloy layer ranges from 1000 angstroms to 2000 angstroms.

[0011] Optionally, the passivation layer is a SixN layer, and the thickness of the passivation layer ranges from 300 nm to 500 nm.

[0012] On the other hand, the embodiment of the present disclosure also provides a method for preparing a light-emitting diode, which comprises: providing a substrate; forming an epitaxial layer on the substrate; forming an electrode on the epitaxial layer, the electrode comprising a first metal layer and a second metal layer sequentially stacked on the epitaxial layer, the first metal layer comprising Au metal, and the second metal layer not comprising Au metal; forming a passivation layer on the surface of the epitaxial layer away from the substrate and the surface of the electrode, etching the passivation layer and the second metal layer, forming a through hole on the surface of the passivation layer to expose the second metal layer, forming a countersunk hole on the surface of the second metal layer, the through hole being connected to the countersunk hole; making a solder joint block on the surface of the passivation layer away from the substrate, and connecting the solder joint block to the second metal layer through the through hole and the countersunk hole in sequence.

[0013] Optionally, etching the passivation layer and the second metal layer includes dry etching the passivation layer and the second metal layer, and a dry etching gas used in the dry etching includes oxygen.

[0014] Optionally, the dry etching gas includes carbon tetrafluoride, oxygen and argon, the volume percentage of carbon tetrafluoride ranges from 50% to 70%, the volume percentage of oxygen ranges from 10% to 30%, and the volume percentage of argon ranges from 5% to 40%.

[0015] Optionally, after etching the passivation layer and the second metal layer, the method further includes: placing the light-emitting diode in the manufacturing process into a spin dryer, cleaning the light-emitting diode in the manufacturing process by spraying, and removing moisture from the light-emitting diode in the manufacturing process by spinning.

[0016] The beneficial effects of the technical solutions provided by the embodiments of the present disclosure include at least:

[0017] The electrode in the light-emitting diode provided by the embodiment of the present disclosure includes a first metal layer and a second metal layer sequentially stacked on the epitaxial layer, wherein the first metal layer contains Au metal, and the second metal layer does not contain Au metal. The second metal layer is stacked on the first metal layer so that the second metal layer can be electrically connected to the Au metal in the first metal layer. The passivation layer has a through hole exposing the second metal layer, and the second metal layer has a countersunk hole connected to the through hole, that is, the hole structure provided in the passivation layer only extends to the second metal layer and does not penetrate into the first metal layer, thereby preventing the Au metal in the electrode from being exposed through the hole structure. In this way, after the solder block is made, a base film will not be formed on the surface of the Au, and a high voltage will be generated at the contact surface between the solder block and the Au after power is applied, thereby improving the yield of the light-emitting diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 is a structural schematic diagram of a light emitting diode provided by an embodiment of the present disclosure;

[0020] Figure 2 is a partial structural diagram of a light emitting diode provided by an embodiment of the present disclosure;

[0021] Figure 3 is a partial structural diagram of another light emitting diode provided by an embodiment of the present disclosure;

[0022] Figure 4 This is a flow chart of a method for preparing a light emitting diode provided in an embodiment of the present disclosure.

[0023] The symbols in the figure are explained as follows:

[0024] 10. Substrate;

[0025] 20. Epitaxial layer;

[0026] 30. Electrode; 31. Countersunk hole;

[0027] 310, first metal layer; 311, first Au layer; 312, AuGeNi alloy layer; 313, second Au layer; 314, AuBe alloy layer;

[0028] 320, second metal layer; 321, first Ti layer; 322, Pt layer; 323, second Ti layer;

[0029] 40. passivation layer; 41. through hole;

[0030] 50. Solder point block. DETAILED DESCRIPTION

[0031] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0032] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," "third," and similar words used in the patent specification and claims of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish between different components. Similarly, terms such as "a" or "an" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Terms such as "include" or "comprise" mean that the elements or objects preceding "include" or "comprises" encompass the elements or objects listed after "include" or "comprises," and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," "right," "top," and "bottom" are used only to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0033] In the related art, before the solder joint block is evaporated, it is necessary to go through the processes of passivation layer degumming, solder joint block photolithography, glue application and water flushing. The exposed Au in the through hole will absorb other substances to form compounds during these processes, including: (1) the passivation layer dry etching and degumming process reacts with chlorine-containing gas and chlorine-containing substances in the degumming solution; (2) Au will adsorb impurities in the cavity during the glue application process; (3) Au will complex with impurity ions in the water during the water flushing process. These reactions will form a slight bottom film on the surface of the Au in the through hole, which will affect the contact between the solder joint block and Au after the solder joint block is evaporated, forming a high voltage, which will affect the yield of the light-emitting diode.

[0034] Figure 1 Schematic diagram of the structure of a light emitting diode provided by an embodiment of the present disclosure. Figure 1 As shown, the light emitting diode includes: a substrate 10, an epitaxial layer 20, an electrode 30, a passivation layer 40 and a solder joint block 50. The epitaxial layer 20 is located on the substrate 10, and the electrode 30 is located on the surface of the epitaxial layer 20 away from the substrate 10 and covers a portion of the surface of the electrode 30.

[0035] Figure 2 FIG. 1 is a partial structural diagram of a light emitting diode provided by an embodiment of the present disclosure. Figure 2 As shown, the electrode 30 includes a first metal layer 310 and a second metal layer 320 stacked in sequence on the epitaxial layer 20, the first metal layer 310 includes Au metal, the second metal layer 320 does not include Au metal, the passivation layer 40 has a through hole 41 exposing the surface of the second metal layer 320, and the surface of the second metal layer 320 has a countersunk hole 31, and the through hole 41 is connected to the countersunk hole 31.

[0036] like Figure 2 As shown, the soldering block 50 is attached to the surface of the passivation layer 40 away from the substrate 10 and is connected to the second metal layer 320 through the through hole 41 and the countersunk hole 31 in sequence.

[0037] The electrode 30 in the light-emitting diode provided in the embodiment of the present disclosure includes a first metal layer 310 and a second metal layer 320 sequentially stacked on the epitaxial layer 20, wherein the first metal layer 310 contains Au metal, and the second metal layer 320 does not contain Au metal. The passivation layer 40 has a through hole 41 exposing the second metal layer 320, and the second metal layer 320 has a countersunk hole 31 connected to the through hole 41, that is, the hole structure provided on the passivation layer 40 only extends to the second metal layer 320 and does not penetrate into the first metal layer 310, thereby preventing the Au metal in the electrode 30 from being exposed through the hole structure. In this way, after the solder block 50 is manufactured, a base film will not be formed on the surface of the Au, and a high voltage will be formed at the contact surface between the solder block 50 and the Au, thereby improving the yield of the light-emitting diode.

[0038] Alternatively, as Figure 2 As shown, the second metal layer 320 includes a first Ti layer 321 , a Pt layer 322 and a second Ti layer 323 stacked in sequence, and the bottom of the countersunk hole 31 is located in the Pt layer 322 .

[0039] The metal in the second metal layer 320 that is closest to the passivation layer 40 is the second Ti layer 323, which can improve the adhesion between the passivation layer 40 and the metal layer, thereby improving the connection reliability between the electrode 30 and the passivation layer 40. The provision of the first Ti layer 321 can improve the adhesion between the second metal layer 320 and the first metal layer 310, making the connection between the first metal layer 310 and the second metal layer 320 more reliable.

[0040] At the same time, the countersunk hole 31 only exposes the surface of the Pt layer 322. On the one hand, it prevents the Au in the first metal layer 310 from reacting with the chlorine in the etching gas to form a compound; on the other hand, the Pt layer 322 exposed by the countersunk hole 31 will not adsorb impurities in the cavity during the subsequent gluing process, and will not form a complex with the impurity ions in the water tank during the cleaning and flushing process.

[0041] Optionally, the thickness of the first Ti layer 321 and the second Ti layer 323 are both in the range of 100 angstroms to 400 angstroms, and the thickness of the Pt layer 322 is in the range of 1000 angstroms to 3000 angstroms. The thickness refers to the dimension in the direction perpendicular to the substrate 10 .

[0042] For example, the thickness of the first Ti layer 321 is 200 angstroms, the thickness of the second Ti layer 323 is 200 angstroms, and the thickness of the Pt layer 322 is 2000 angstroms.

[0043] The thickness of the Ti layer is set within the above range to ensure that the Ti layer has sufficient thickness, so that the Ti layer can fully exert the adhesion of the Ti metal and improve the connection reliability between the metal layer and the passivation layer, the first metal layer and the second metal layer.

[0044] In one implementation of the present disclosure, Figure 1 As shown, the first metal layer 310 includes a first Au layer 311, an AuGeNi alloy layer 312, and a second Au layer 313 stacked in sequence. Each film layer of the first metal layer 310 includes Au, which can improve the conductivity of the first metal layer 310 and thus enhance the current spreading performance of the electrode 30.

[0045] Optionally, the thickness of the first Au layer 311 ranges from 100 angstroms to 400 angstroms, the thickness of the AuGeNi alloy layer 312 ranges from 1000 angstroms to 3000 angstroms, and the thickness of the second Au layer 313 ranges from 1000 angstroms to 3000 angstroms.

[0046] For example, the thickness of the first Au layer 311 is 200 angstroms, the thickness of the AuGeNi alloy layer 312 is 2000 angstroms, and the thickness of the second Au layer 313 is 2000 angstroms.

[0047] In one implementation of the present disclosure, Figure 3 As shown, the first metal layer 310 includes a first Au layer 311, an AuBe alloy layer 314, and a second Au layer 313 stacked in sequence. The AuBe alloy layer 314 has a higher Au content and better conductivity, which is beneficial for improving the current spreading performance of the electrode 30.

[0048] Optionally, the thickness of the first Au layer 311 ranges from 100 angstroms to 400 angstroms, the thickness of the AuBe alloy layer 314 ranges from 1000 angstroms to 2000 angstroms, and the thickness of the second Au layer 313 ranges from 2000 angstroms to 4500 angstroms.

[0049] For example, the thickness of the first Au layer 311 is 200 angstroms, the thickness of the AuBe alloy layer 314 is 1500 angstroms, and the thickness of the second Au layer 313 is 3000 angstroms.

[0050] In the embodiment of the present disclosure, the epitaxial layer 20 may include a p-GaP ohmic contact layer, a p-AlInP confinement layer, an AlInP transition layer, a first u-AlGaInP layer, an active layer, a second u-AlGaInP layer, an n-AlInP confinement layer, an n-AlGaInP current blocking layer, an n-AlGaInP window layer and an n-GaAs ohmic contact layer stacked sequentially on the substrate 10.

[0051] The substrate is a sapphire substrate, a silicon substrate or a silicon carbide substrate, and can be a flat substrate or a patterned substrate.

[0052] As an example, in the embodiments of the present disclosure, the substrate is a sapphire substrate. Sapphire substrate is a commonly used substrate with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a sapphire flat sheet substrate.

[0053] The electrode 30 may include an n-electrode and a p-electrode. The n-electrode is located on the surface of the n-GaAs ohmic contact layer. The surface of the n-GaAs ohmic contact layer has a groove extending to the p-GaP ohmic contact layer, and the p-electrode is located on the surface of the groove to connect to the p-GaP ohmic contact layer.

[0054] The passivation layer 40 at least covers the surface of the p-GaP ohmic contact layer exposed by the groove, the surface of the n-GaAs ohmic contact layer, the n-electrode, the surface exposed by the groove, and the surface of the p-electrode.

[0055] Optionally, the p-GaP ohmic contact layer has a thickness ranging from 5 μm to 8 μm.

[0056] The thickness of the p-GaP ohmic contact layer can meet the requirements for preparing a p-electrode on the p-GaP ohmic contact layer, and the overall quality of the p-GaP ohmic contact layer with a thickness within this range is good, which can ensure the stable preparation and connection of the p-electrode and the luminous efficiency of the final red light-emitting diode.

[0057] Optionally, the thickness of the p-AlInP confinement layer ranges from 280 nm to 400 nm. The quality of the obtained light-emitting diode is good.

[0058] Optionally, the thickness of the AlInP transition layer ranges from 250 nm to 350 nm. The quality of the obtained light-emitting diode is good.

[0059] Exemplarily, the thickness of the first u-AlGaInP layer ranges from 50 nm to 90 nm.

[0060] Optionally, the active layer is configured to include a plurality of AlGaInP well layers and AlGaInP barrier layers that are alternately grown in a periodic manner, and Al compositions in the AlGaInP well layers and the AlGaInP barrier layers are different.

[0061] For example, the overall thickness of the active layer may range from 150 nm to 200 nm.

[0062] Optionally, the thickness of the second u-AlGaInP layer ranges from 40 nm to 90 um.

[0063] Optionally, the thickness of the n-AlInP confinement layer ranges from 200 nm to 500 nm. The quality of the obtained light-emitting diode is good.

[0064] For example, the thickness of the n-AlGaInP window layer ranges from 0.4 μm to 0.8 μm, which can provide sufficient light-emitting space.

[0065] Optionally, the thickness of the n-AlGaInP current spreading layer ranges from 1 μm to 2 μm. The quality of the obtained light emitting diode is good.

[0066] For example, the thickness of the n-AlGaInP window layer ranges from 1 μm to 2 μm. The quality of the obtained light-emitting diode is good.

[0067] Optionally, the material of the passivation layer 40 is Si x N. Si x N has good high dielectric constant and insulation properties, which effectively prevents the possibility of leakage from the electrode 30 and the pn junction, ensures the stable use of the light-emitting diode, effectively reduces the possibility of leakage, and improves the reliability of the light-emitting diode.

[0068] Optionally, the material of the passivation layer 40 is Si x Under the premise of N, the thickness of the passivation layer 40 may range from 300 nm to 500 nm.

[0069] When the thickness of the passivation layer 40 is within the above range, pn junction leakage and the possibility of contact between the p-electrode and the n-GaAs ohmic contact layer can be more effectively avoided, thereby improving the operating stability of the light emitting diode.

[0070] Figure 4 FIG. 1 is a flow chart of a method for preparing a light emitting diode according to an embodiment of the present disclosure. Figure 4 As shown, the preparation method comprises:

[0071] Step 101: Provide a substrate.

[0072] Step 102: forming an epitaxial layer on a substrate.

[0073] Step 103: forming electrodes on the epitaxial layer.

[0074] The electrode includes a first metal layer and a second metal layer sequentially stacked on the epitaxial layer, and the first metal layer includes Au metal.

[0075] Step 104: forming a passivation layer on the surface of the epitaxial layer away from the substrate and the surface of the electrode, and etching the passivation layer and the second metal layer.

[0076] The surface of the passivation layer is etched to form a through hole exposing the second metal layer, and the surface of the second metal layer is etched to form a countersunk hole, and the through hole is connected to the countersunk hole.

[0077] The electrode of the light-emitting diode prepared by the preparation method provided by the embodiment of the present disclosure includes a first metal layer and a second metal layer sequentially stacked on the epitaxial layer, wherein the first metal layer contains Au metal, and the second metal layer does not contain Au metal. The second metal layer is stacked on the first metal layer, so that the second metal layer can be electrically connected to the Au metal in the first metal layer. The passivation layer has a through hole exposing the second metal layer, and the second metal layer has a countersunk hole connected to the through hole, that is, the hole structure opened on the passivation layer only extends to the second metal layer and does not penetrate into the first metal layer, thereby avoiding the Au metal in the electrode from being exposed through the hole structure. In this way, after the solder block is made, a base film will not be formed on the surface of the Au, and a high voltage will be formed at the contact surface between the solder block and the Au, thereby improving the yield of the light-emitting diode.

[0078] In step 101, the substrate is a sapphire substrate, a silicon substrate, or a silicon carbide substrate. The substrate can be a flat substrate or a patterned substrate.

[0079] As an example, in the embodiments of the present disclosure, the substrate is a sapphire substrate. Sapphire substrate is a commonly used substrate with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a sapphire flat sheet substrate.

[0080] The sapphire substrate may be pre-treated by placing the sapphire substrate in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking the sapphire substrate for 12 to 18 minutes. For example, in the embodiment of the present disclosure, the sapphire substrate is baked for 15 minutes.

[0081] Specifically, the baking temperature may be 1000° C. to 1200° C., and the pressure in the MOCVD reaction chamber during baking may be 100 mbar to 200 mbar.

[0082] Growing the epitaxial layer in step 102 may include: sequentially forming a p-GaP ohmic contact layer, a p-AlInP confinement layer, an AlInP transition layer, a first u-AlGaInP layer, an active layer, a second u-AlGaInP layer, an n-AlInP confinement layer, an n-AlGaInP current blocking layer, an n-AlGaInP window layer, and an n-GaAs ohmic contact layer on a sapphire substrate by MOCVD technology.

[0083] Optionally, the p-GaP ohmic contact layer has a thickness ranging from 5 μm to 8 μm.

[0084] The thickness of the p-GaP ohmic contact layer can meet the requirements for preparing a p-electrode on the p-GaP ohmic contact layer, and the overall quality of the p-GaP ohmic contact layer with a thickness within this range is good, which can ensure the stable preparation and connection of the p-electrode and the luminous efficiency of the final red light-emitting diode.

[0085] Optionally, the thickness of the p-AlInP confinement layer ranges from 280 nm to 400 nm. The quality of the obtained light-emitting diode is good.

[0086] Optionally, the thickness of the AlInP transition layer ranges from 250 nm to 350 nm. The quality of the obtained light-emitting diode is good.

[0087] Exemplarily, the thickness of the first u-AlGaInP layer ranges from 50 nm to 90 nm.

[0088] Optionally, the active layer is configured to include a plurality of AlGaInP well layers and AlGaInP barrier layers that are alternately grown in a periodic manner, and Al compositions in the AlGaInP well layers and the AlGaInP barrier layers are different.

[0089] For example, the overall thickness of the active layer may range from 150 nm to 200 nm.

[0090] Optionally, the thickness of the second u-AlGaInP layer ranges from 40 nm to 90 um.

[0091] Optionally, the thickness of the n-AlInP confinement layer ranges from 200 nm to 500 nm. The quality of the obtained light-emitting diode is good.

[0092] For example, the thickness of the n-AlGaInP window layer ranges from 0.4 μm to 0.8 μm, which can provide sufficient light-emitting space.

[0093] Optionally, the thickness of the n-AlGaInP current spreading layer ranges from 1 μm to 2 μm. The quality of the obtained light emitting diode is good.

[0094] For example, the thickness of the n-AlGaInP window layer ranges from 1 μm to 2 μm. The quality of the obtained light-emitting diode is good.

[0095] In step 102, the growth method of each layer can be as follows:

[0096] Exemplarily, the growth conditions of the GaInP layer include: a growth temperature of 650° C. to 670° C., a thickness of 150-300 nm, a V / III ratio of 20-30, and a growth rate of 0.5-0.8 nm / s.

[0097] Optionally, the growth conditions of the n-GaAs ohmic contact layer include: growth temperature of 650° C. to 670° C., thickness of 150-300 nm, V / III of 20-30, and growth rate of 0.5-0.8 nm / s.

[0098] Optionally, the growth conditions of the n-AlGaInP current spreading layer and the n-AlGaInP ohmic contact layer include: growth temperature 670-680 degrees, thickness 3-3.5um, V / III 40-50, growth rate 1.2-1.7nm / s, and carrier concentration 1-2e18.

[0099] Optionally, the n-AlInP confinement layer growth conditions include: growth temperature 670° C. to 680° C., thickness 250-350 nm, V / III 40-50, growth rate 1.2-1.7 nm / s, and carrier concentration 1-2e18.

[0100] Optionally, the growth conditions of the first u-AlGaInP layer include: growth temperature 670° C. to 680° C., thickness 250-350 nm, V / III 40-50, growth rate 1.2-1.7 nm / s, and carrier concentration 1-2e18.

[0101] Optionally, the growth conditions of the AlGaInP well layer and the AlGaInP barrier layer in the active layer include: growth temperature 650-660 degrees, thickness 20-22 nm, V / III ratio 40-50, and growth rate 1-2 nm / s, which can produce an active layer of good quality.

[0102] Optionally, the growth conditions of the second u-AlGaInP layer include: growth temperature 670° C. to 680° C., thickness 250-350 nm, V / III 40-50, growth rate 1.2-1.7 nm / s, and carrier concentration 1-2e18.

[0103] Optionally, the growth conditions of the AlInP transition layer and the p-AlInP confinement layer include: growth temperature 670-680 degrees, thickness 350-450 nm, V / III 40-50, growth rate 1.2-1.7 nm / s, and carrier concentration 1-2e18.

[0104] Optionally, before forming the silicon oxide bonding layer on the p-GaP ohmic contact layer, the method for preparing the flip-chip red light emitting diode chip further comprises: performing a wet roughening treatment on the surface of the p-GaP ohmic contact layer.

[0105] The diffuse reflection at the surface of the p-GaP ohmic contact layer can be reduced, and the connection stability between the p-GaP ohmic contact layer and the silicon oxide bonding layer can be improved.

[0106] The step 103 of forming an electrode on the epitaxial layer includes the following steps:

[0107] In the first step, a groove is formed on the n-GaAs ohmic contact layer to expose the p-GaP ohmic contact layer.

[0108] In the second step, electrodes are formed on the surface of the n-GaAs ohmic contact layer and in the grooves respectively.

[0109] An n-electrode is formed on the surface of the n-GaAs ohmic contact layer, and a p-electrode is formed in the groove.

[0110] Illustratively, the second metal layer includes a first Ti layer, a Pt layer, and a second Ti layer stacked in sequence, and the through hole exposes the surface of the Pt layer.

[0111] Exemplarily, the first metal layer includes a first Au layer, an AuGeNi alloy layer, and a second Au layer stacked in sequence.

[0112] Exemplarily, the first metal layer includes a first Au layer, an AuBe alloy layer, and a second Au layer stacked in sequence.

[0113] The forming of the passivation layer in step 104 may include:

[0114] In the first step, a passivation layer is formed on the surface of the p-GaP ohmic contact layer exposed by the groove, the surface of the n-GaAs ohmic contact layer, the surface of the n-electrode and the surface of the p-electrode.

[0115] In the second step, the passivation layer and the second metal layer are dry-etched, and the chlorine in the dry-etching gas is replaced by oxygen; or the chlorine in the dry-etching gas is removed.

[0116] In one implementation, the dry etching gas includes carbon tetrafluoride and argon.

[0117] The volume percentage of carbon tetrafluoride ranges from 50% to 70%, and the volume percentage of argon ranges from 30% to 50%.

[0118] Compared with the related technology that uses carbon tetrafluoride, chlorine and argon as dry etching gases, chlorine is removed, which helps to improve the etching resistance of the Pt layer, so that the Pt layer is exposed in the etched countersunk hole instead of exposing the Au under the Pt layer, which can effectively prevent Au from reacting with chlorine in the etching gas to form compounds.

[0119] In another implementation, the dry etching gas includes carbon tetrafluoride, oxygen, and argon.

[0120] The volume percentage of carbon tetrafluoride ranges from 50% to 70%, the volume percentage of oxygen ranges from 10% to 30%, and the volume percentage of argon ranges from 5% to 40%.

[0121] Compared with the related art using carbon tetrafluoride, chlorine and argon as dry etching gases, oxygen is used to replace chlorine, and the volume percentage of oxygen is the same as the volume percentage of the replaced chlorine, which can ensure good etching morphology.

[0122] After forming the passivation layer and before making the vapor-deposited solder joint block, the preparation method further includes: cleaning the light-emitting diode by spraying in a spin dryer, and removing the water on the light-emitting diode by spin drying.

[0123] Compared with the cleaning process of immersion cleaning in a water tank in related technologies, the cleaning method of directly using spray water washing and drying in a spin dryer can further avoid long-term contact between Au in the through hole and impurity ions in the water tank, and allow Au to complex with impurity ions in the water.

[0124] Finally, two solder joints are made on the surface of the passivation layer by evaporation, and the two solder joints are connected to the two electrodes through two through holes respectively.

[0125] It should be noted that in the embodiments of the present disclosure, a Veeco K 465i or C4 or RB MOCVD (Metal Organic Chemical Vapor Deposition) device is used to grow the epitaxial layer of the light-emitting diode. High-purity H2 (hydrogen) or high-purity N2 (nitrogen) or a mixture of high-purity H2 and high-purity N2 is used as the carrier gas, high-purity NH3 is used as the N source, trimethylgallium (TMGa) and triethylgallium (TEGa) are used as the gallium source, trimethylindium (TMIn) is used as the indium source, silane (SiH4) is used as the N-dopant, trimethylaluminum (TMAl) is used as the aluminum source, and bis(cyclopentadienyl)magnesium (CP2Mg) is used as the P-dopant.

[0126] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A light emitting diode, characterized in that: The light-emitting diode comprises: a substrate (10), an epitaxial layer (20), an electrode (30), a passivation layer (40) and a solder joint block (50), wherein the epitaxial layer (20) is located on the substrate (10), the electrode (30) is located on a surface of the epitaxial layer (20) away from the substrate (10), and the passivation layer (40) is located on a surface of the epitaxial layer (20) away from the substrate (10) and covers a portion of the surface of the electrode (30); The electrode (30) comprises a first metal layer (310) and a second metal layer (320) sequentially stacked on the epitaxial layer (20), the first metal layer (310) comprises Au metal, the second metal layer (320) does not comprise Au metal, the second metal layer (320) comprises a first Ti layer (321), a Pt layer (322) and a second Ti layer (323) stacked sequentially, the passivation layer (40) comprises a through hole (41) exposing the surface of the second metal layer (320), the surface of the second metal layer (320) comprises a countersunk hole (31), the through hole (41) is connected to the countersunk hole (31), and the bottom of the countersunk hole (31) is located in the Pt layer (322); The soldering point block (50) is adhered to the surface of the passivation layer (40) away from the substrate (10) and is connected to the second metal layer (320) through the through hole (41) and the countersunk hole (31) in sequence.

2. The light emitting diode according to claim 1, characterized in that The thickness of the first Ti layer (321) and the second Ti layer (323) are both in the range of 100 angstroms to 400 angstroms, and the thickness of the Pt layer (322) is in the range of 1000 angstroms to 3000 angstroms.

3. The light emitting diode according to claim 1, characterized in that The first metal layer (310) comprises a first Au layer (311), an AuGeNi alloy layer (312), and a second Au layer (313) stacked in sequence; or, The first metal layer (310) comprises a first Au layer (311), an AuBe alloy layer (314), and a second Au layer (313) stacked in sequence.

4. The light emitting diode according to claim 3, characterized in that The thickness of the first Au layer (311) ranges from 100 angstroms to 400 angstroms, and the thickness of the second Au layer (313) ranges from 1000 angstroms to 4500 angstroms; The thickness of the AuGeNi alloy layer (312) ranges from 1000 angstroms to 3000 angstroms, or the thickness of the AuBe alloy layer (314) ranges from 1000 angstroms to 2000 angstroms.

5. The light emitting diode according to any one of claims 1 to 4, characterized in that: The passivation layer (40) is Si x N layer, the thickness of the passivation layer (40) ranges from 300nm to 500nm.

6. A method for preparing a light emitting diode, characterized in that: The preparation method comprises: providing a substrate; forming an epitaxial layer on the substrate; forming an electrode on the epitaxial layer, the electrode comprising a first metal layer and a second metal layer sequentially stacked on the epitaxial layer, the first metal layer comprising Au metal, the second metal layer not comprising Au metal, and the second metal layer comprising a first Ti layer, a Pt layer, and a second Ti layer sequentially stacked; forming a passivation layer on a surface of the epitaxial layer away from the substrate and a surface of the electrode, etching the passivation layer and the second metal layer, forming a through hole on the surface of the passivation layer to expose the second metal layer, and forming a countersunk hole on the surface of the second metal layer, wherein the through hole is connected to the countersunk hole, and the bottom of the countersunk hole is located in the Pt layer; A soldering point block is made on a surface of the passivation layer away from the substrate, and the soldering point block is connected to the second metal layer through the through hole and the countersunk hole in sequence.

7. The preparation method according to claim 6, characterized in that The etching of the passivation layer and the second metal layer comprises: The passivation layer and the second metal layer are dry-etched, and the dry etching gas used in the dry etching includes oxygen.

8. The preparation method according to claim 7, characterized in that The dry etching gas includes carbon tetrafluoride, oxygen and argon, the volume percentage of carbon tetrafluoride ranges from 50% to 70%, the volume percentage of oxygen ranges from 10% to 30%, and the volume percentage of argon ranges from 5% to 40%.

9. The preparation method according to any one of claims 6 to 8, characterized in that After etching the passivation layer and the second metal layer, the method further includes: The light emitting diodes in the process of production are placed in a spin dryer, and the light emitting diodes in the process of production are cleaned by a spraying method, and the water on the light emitting diodes in the process of production are removed by a spin drying method.

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