Driving circuit arrangement and driving method for totem-pole power factor correction converter

Abstract

The application relates to a driving circuit device for a totem-pole power factor correction converter (PFC), which comprises a controller configured to control an initial driving level of a switching tube of the converter; a current judging circuit configured to judge whether an inductance current of the converter is zero-crossing; a selector configured to compare a power supply voltage of the converter with 0, and based on a result of the comparison, select one of an output level of the current judging circuit and a preset logic level as an intermediate control level to output; and an operator configured to logically operate the intermediate control level with the initial driving level, and generate a target driving level for driving the switching tube. By adopting the driving circuit device for the totem-pole power factor correction converter according to the application, an adverse state of the inductance current zero-crossing reversal of the PFC converter in a DCM mode can be avoided, additional loss caused by the adverse state is eliminated, and the power factor is improved.

Description

Technical Field

[0001] This invention relates to the field of totem-pole power factor correction converters, and more specifically, to a drive circuit device for a totem-pole power factor correction converter, a totem-pole power factor correction converter having the drive circuit device, and a drive method for a totem-pole power factor correction converter. Background Technology

[0002] In recent years, new semiconductor materials, represented by silicon carbide (SiC) and gallium nitride (GaN), have emerged. Compared with traditional semiconductor material silicon, these new semiconductor materials have many advantages in terms of thermal and electrical properties, and are therefore widely used in power switches as third-generation semiconductor devices. These third-generation semiconductor devices using silicon carbide (SiC) or gallium nitride (GaN) belong to wide-bandgap semiconductor devices (such as SiC MOSFETs or GaN FETs). They have many advantages over Si switches, one of which is that their body diode (or equivalent body diode) has fast reverse recovery (for SiC MOSFETs) or no reverse recovery (for GaN FETs). This characteristic provides the premise for the widespread application of totem-pole power factor correction (PFC) converters with fixed switching frequency continuous conduction mode (CCM).

[0003] Totem-pole PFC converters with fixed switching frequency (CCM) are true bridgeless PFC topologies. They are highly efficient, simple to control, and beneficial for EMI (Electromagnetic Interference) filter design. During operation, totem-pole PFC converters utilize wide-bandgap semiconductor devices (such as SiC MOSFETs or GaN FETs) operating at high frequencies (tens of kHz to hundreds of kHz) and diodes or switching transistors operating at power frequencies (50Hz / 60Hz), along with inductors, capacitors, and resistors. PFC converters used in high-power applications typically operate in a fixed-frequency continuous conduction mode (CCM), where the current flowing through the inductor is continuous. However, under light load conditions, in the region near the zero-crossing point of the input voltage, the PFC converter operates in discontinuous conduction mode (DCM). As the load decreases further, this region gradually expands until it completely covers the entire power frequency cycle (see J. Sebastian, J.A. Cobos, J.M. Lopera, “The determination of the boundaries between continuous and discontinuous conduction modes in PWM DC-to-DC converters used as power factor preregulators”, IEEE Trans. On Power Electronics, vol.10, no.5, Sept.1995.). Ideally, in DCM mode, the current flowing through the inductor reaches zero and remains zero for a period of time before increasing again, resulting in a discontinuous current flow. PFC converters also have a critical mode between CCM and DCM modes, where the current flowing through the inductor reaches zero and then immediately begins to increase.

[0004] When the converter enters DCM mode, since the drive voltages of the two high-frequency switching transistors in the totem-pole PFC are usually designed to be complementary (ignoring dead time), when the inductor current drops to zero, the drive voltage of the freewheeling switch still exists, causing it to continue to conduct, resulting in the inductor current reversing, causing additional losses and reducing the power factor (PF) value. Summary of the Invention

[0005] The purpose of this invention is to provide a driving circuit device for a totem-pole power factor correction converter, which solves the aforementioned problems in the prior art.

[0006] To achieve the above objectives, the driving circuit device for a totem-pole power factor correction converter according to the present invention includes: a controller configured to control the initial drive level of the converter's switching transistor; a current determination circuit configured to determine whether the inductor current of the converter crosses zero; a selector configured to compare the converter's power supply voltage with 0, and based on the comparison result, select one of the output level of the current determination circuit and a preset logic level as an intermediate control level for output; and an arithmetic unit configured to perform a logical operation on the intermediate control level and the initial drive level to generate a target drive level for driving the switching transistor. In one embodiment of the present invention, the preset logic level is a logic high level, and the logical operation is a logical AND operation.

[0007] By employing the drive circuit device for a totem-pole power factor correction converter according to the present invention, the unfavorable state of inductor current reversal at zero crossing in DCM mode of the PFC converter can be avoided, the additional losses caused thereby can be eliminated, and the power factor can be improved.

[0008] In one embodiment of the present invention, the current determination circuit includes a first comparator and a second comparator. The first comparator is configured to change its output level from logic high to logic low in response to the inductor current crossing zero from a positive to a negative direction, and the second comparator is configured to change its output level from logic high to logic low in response to the inductor current crossing zero from a negative to a positive direction. This achieves the determination of the inductor current in a simple manner, enabling timely and accurate determination of the zero-crossing time and direction of the inductor current.

[0009] In one embodiment of the present invention, the selector includes a first selection switch and a second selection switch, and the intermediate control level includes a first intermediate control level output by the first selection switch and a second intermediate control level output by the second selection switch. This achieves the generation of the intermediate control level in a very simple and low-cost manner.

[0010] In one embodiment of the invention, a first selection switch is connected to a first comparator and configured to: output a preset logic level as a first intermediate control level in response to the converter's power supply voltage being less than 0, or output the output level of the first comparator as the first intermediate control level in response to the converter's power supply voltage being not less than 0. A second selection switch is connected to a second comparator and outputs a preset logic level as a second intermediate control level when the converter's power supply voltage is not less than 0, or outputs the output level of the second comparator as the second intermediate control level in response to the converter's power supply voltage being less than 0. Here, the preset logic level is, for example, a logic high level. The generation of the intermediate control level is described in detail here. It can be seen that the generation method of the intermediate control level is very simple, thus greatly reducing costs.

[0011] In one embodiment of the present invention, the switching transistors include at least a first switching transistor and a second switching transistor connected to each other, and the initial drive level output by the controller includes at least a first initial drive level for controlling the first switching transistor and a second initial drive level for controlling the second switching transistor. This is a simple implementation of a high-frequency half-bridge (composed of a first switching transistor and a second switching transistor) of a totem-pole power factor correction converter.

[0012] In one embodiment of the present invention, the arithmetic unit includes a first AND gate and a second AND gate. The first AND gate is configured to perform an AND operation on a first intermediate control level and a first initial drive level, and the second AND gate is configured to perform an AND operation on a second intermediate control level and a second initial drive level. This achieves adjustment of the initial drive level of the relevant switching transistor in a simple manner.

[0013] In one embodiment of the present invention, the target driving level includes a first target driving level output by a first AND gate and a second target driving level output by a second AND gate. The first target driving level is configured to drive a first switching transistor, and the second target driving level is configured to drive a second switching transistor.

[0014] In one embodiment of the present invention, the first switching transistor includes a plurality of first switching transistors connected in parallel, and the second switching transistor includes a plurality of second switching transistors connected in parallel. A simple extension of the switching transistors is made here, so that the driving circuit device of this application can also be applied to the case of multiple switching transistors connected in parallel.

[0015] In one embodiment of the present invention, multiple half-bridges, each composed of a first switching transistor and a second switching transistor, are connected in parallel with each other in an alternating manner. Each half-bridge is connected in parallel with an inductor between itself and a power supply. This provides a simple extension to the high-frequency half-bridge design, allowing the driving circuit device described in this application to also be applied to situations where multiple high-frequency half-bridges are connected in parallel with an alternating manner.

[0016] According to another aspect, the present invention relates to a totem-pole power factor correction converter including the aforementioned drive circuit device. The aspects and advantages described above with respect to the drive circuit device also apply accordingly to the totem-pole power factor correction converter according to the present invention, and will not be repeated here.

[0017] According to another aspect, the present invention relates to a driving method for a totem-pole power factor correction converter, comprising the following steps: generating an initial driving level for a switching transistor of the converter; determining whether the inductor current of the converter has crossed zero; generating a corresponding output level based on whether the inductor current crosses zero from positive to negative or from negative to positive; comparing the power supply voltage of the converter with 0, and based on the comparison result, selecting one of the output level and a preset logic level as an intermediate control level for output; performing a logical operation between the intermediate control level and the initial driving level to generate a target driving level for driving the switching transistor. In one embodiment of the present invention, the preset logic level is a logic high level, and the logical operation is a logical AND operation. The various aspects and advantages described above regarding the driving circuit device are also applicable to the driving method according to the present invention, and will not be repeated here. Attached Figure Description

[0018] Other advantages and designs of the present invention will now be described in detail with reference to the accompanying drawings, wherein:

[0019] Figure 1 This schematically illustrates a circuit topology for a totem-pole power factor correction converter.

[0020] Figure 2 This schematically illustrates another circuit topology for a totem-pole power factor correction converter;

[0021] Figure 3 and Figure 4 The diagram schematically illustrates the current flow of the converter in two phases under the condition of a positive half-wave of the input AC power supply voltage;

[0022] Figure 5 The reverse flow of inductor current in the converter is schematically shown in DCM mode;

[0023] Figure 6 Is Figure 5 The diagram shows the timing correspondence between the initial drive level of the switching transistor and the inductor current of the converter under the following conditions;

[0024] Figure 7 The topology of the drive circuit arrangement according to this application for the converter is schematically shown;

[0025] Figure 8 yes Figure 7A schematic diagram showing the timing correspondence between the drive level of the switching transistor and the inductor current in CCM mode under the positive half-wave condition of the input AC power supply voltage.

[0026] Figure 9 yes Figure 7 A schematic diagram showing the timing correspondence between the drive level of the switching transistor and the inductor current in DCM mode under the positive half-wave condition of the input AC power supply voltage.

[0027] Figure 10 schematically shown Figure 1 The circuit topology shown can be adopted Figure 7 An extended scheme of the drive circuit device shown is provided, wherein every two switching transistors are connected in parallel; and

[0028] Figure 11 schematically shown Figure 1 The circuit topology shown can be adopted Figure 7 Another extended scheme of the drive circuit device shown is in which two sets of switching transistors are connected in parallel in an alternating manner. Detailed Implementation

[0029] Unless otherwise specified, corresponding numbers and symbols in the different figures generally refer to corresponding areas. The figures are drawn to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the figures do not necessarily indicate the termination of the feature range.

[0030] In the following description, various specific details are shown to provide a thorough understanding of various examples of embodiments according to the description. Embodiments may be obtained without one or more specific details, or by utilizing other methods, components, materials, etc. In other instances, known structures, materials, or operations are not shown or described in detail so as not to obscure various aspects of the embodiments.

[0031] References to "an embodiment" or "an implementation" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment," "in one embodiment," etc., that may appear in various aspects of this specification do not necessarily refer precisely to the same embodiment. Furthermore, specific configurations, structures, or features may be combined in any suitable manner in one or more embodiments.

[0032] The title / reference numerals used herein are for readability purposes only and do not limit the scope of protection or the scope of the embodiments. Identical or similar elements are identified using the same reference numerals.

[0033] The problem this disclosure aims to solve is to prevent inductor current reversal in a PFC converter in DCM mode, thereby eliminating the additional losses caused by it. To this end, this disclosure specifies that the drive voltage applied to the gate of the freewheeling switch is adjusted so that the freewheeling switch is turned off in time when the inductor current crosses zero, thereby preventing the inductor current of the PFC converter from reversing and flowing through the freewheeling switch, thus reducing the additional losses of the PFC converter and improving its power factor.

[0034] First refer to Figure 1 This schematically illustrates a circuit topology for a totem-pole power factor correction (PFC) converter. For example... Figure 1 As shown, this circuit topology exemplarily includes an AC power supply, an inductor L, two vertically connected totem-pole shaped high-frequency switching transistors (MOS, Metal Oxide Semiconductor), namely the first switching transistor Q1 and the second switching transistor Q2, two vertically connected diodes D1 and D2, a capacitor C, and a resistor R. The switching transistors here can be SiC MOS transistors, GaN FETs, or other switching transistors with good reverse recovery performance. Here, the input voltage V... ac It is a single-phase AC voltage. The first switch Q1 and the second switch Q2 are wide-bandgap semiconductor devices, such as SiC MOSFETs or GaN FETs, which operate at high frequencies of tens or even hundreds of kHz. Therefore, the first switch Q1 and the second switch Q2 form a high-frequency half-bridge. Diodes D1 and D2 operate at the power frequency of 50Hz / 60Hz, thus forming a low-frequency half-bridge. Figure 1 The diagram shows a typical circuit topology for a totem-pole power factor correction (PFC) converter. However, it is also possible to... Figure 1 Replace diodes D1 and D2 with switching transistors Q3 and Q4, which also operate at the power frequency, such as... Figure 2 Another circuit topology is shown in the diagram. Figure 2 The functions of switching transistors Q3 and Q4 in the middle are... Figure 1 Diodes D1 and D2 in the circuit are identical. As mentioned earlier, based on the inductor current, totem-pole PFC converters have three operating modes: CCM mode, DCM mode, and critical mode. Among these, CCM mode, with a fixed switching frequency, is the most commonly used. The following will use... Figure 1 The circuit topology and input voltage V shown are as follows. ac The positive half-wave, i.e., V ac Taking >0 as an example, combined with Figures 3 to 6 This paper introduces the problems that this application aims to solve in DCM mode.

[0035] Figure 6The diagram illustrates a first initial drive level S1 and a second initial drive level S2 applied to the gate G of the first switch Q1 and the second switch Q2, respectively, and an inductor current i flowing through the inductor L, as described in the prior art. L The timing correspondence is as follows: When the first initial drive level S1 and the second initial drive level S2 are logic high, the first switch Q1 and the second switch Q2 are turned on accordingly; when the first initial drive level S1 and the second initial drive level S2 are logic low, the first switch Q1 and the second switch Q2 are turned off accordingly. It should be noted that... Figure 6 The inductor current i flowing through inductor L shown in the figure L The measurement was taken at the aforementioned high frequency of the first switch Q1 and the second switch Q2, thus exhibiting an approximate sawtooth wave shape, similar to a measurement taken from a microscopic perspective within a very small time scale. However, at the aforementioned power frequency, it exhibits a shape consistent with the input voltage V. ac The essentially identical sine wave shape is analogous to a measurement taken from a macroscopic perspective over a relatively large time scale. As mentioned earlier, in traditional control schemes, the first initial drive level S1 and the second initial drive level S2 are designed to be largely complementary (ignoring dead time), such as... Figure 6 As shown, it can be generated by a controller or a DSP (Digital Signal Processor) according to a control algorithm.

[0036] See Figure 6 During time period 0 to t1, the first initial drive level S1 of the first switch Q1 is logic low, so the first switch Q1, acting as a freewheeling switch, is turned off. The second initial drive level S2 of the second switch Q2 is logic high, so the second switch Q2, acting as the main switch, is turned on. The current flow in this case is as follows: Figure 3 As shown. During time intervals t1 to t2, the first initial drive level S1 is logic high, and the second initial drive level S2 is logic low. Therefore, the first switch Q1 is turned on, and the second switch Q2 is turned off. The current flow in this situation is as follows: Figure 4 As shown. It can be seen that, in Figure 3 and Figure 4 Diode D2 is always conducting. It should be noted that... Figure 4 Inductor current i L The current flows through the body of the first switching transistor Q1, but not through its body diode (also called the parasitic diode). Figure 4 The diode located next to and in parallel with the first switch Q1 has a much higher forward voltage than the switch itself, so when the first switch Q1 is turned on, the inductor current i... LThe current preferentially flows through its body. During time intervals t2 to t3, the first initial drive level S1 remains logic high, and the second initial drive level S2 remains logic low. Therefore, the first switch Q1 remains on, and the second switch Q2 remains off. However, at time t2, the inductor current i... L The current begins to change from positive to negative at the zero point, i.e., it reverses direction. In this case, the current flow direction is as follows: Figure 5 As shown. Therefore, in V ac When the value is greater than 0, during the time period t2 to t3, due to the inductor current i flowing through inductor L L Conversely, the aforementioned problems of additional losses and a reduced power factor arise. Similarly, in V... ac The same problem occurs when the value is less than 0.

[0037] The characteristics of the switching transistor need to be explained: the transistor will turn on as long as the driving level applied to its gate G is greater than its threshold voltage; otherwise, it will turn off. When the transistor is on, the inductor current i flowing through it... L It can flow from the drain (D) to the source (S), such as Figure 3 The water flows downward through the second switch Q2 and Figure 5 The current flows from top to bottom through the first switching transistor Q1, but it can also flow from the source S to the drain D, as shown below. Figure 4 The current flows from bottom to top through the first switching transistor Q1, and the specific direction of the flow depends on which of the source (S) and drain (D) voltages is higher. In the circuit topology of this application, it specifically depends on the current flowing through the inductor. At the input voltage V... ac The negative half-wave, i.e., V ac When the voltage is less than 0, the first switching transistor Q1 acts as the main switch, the second switching transistor Q2 acts as the freewheeling switch, and diode D1 is always conducting. The specific working process is the same as when V... ac The case is similar to that of >0, or more precisely, symmetrical to it.

[0038] To address the issue of inductor current i during time period t2 to t3 L The aforementioned problems, which arise in the opposite direction, are addressed in existing technologies with a crude, one-size-fits-all solution. Specifically, after the PFC converter enters DCM mode, the drive voltage of the freewheeling switch is set to zero, effectively cutting it off. However, to ensure sufficient margin, the freewheeling switch is switched when the load on the PFC converter reaches, for example, 30% to 40% of its rated load, without considering when the current flowing through the inductor reverses; that is, the inductor current is not measured. For example, in... Figure 6 At some point between t1 and t2, the initial drive level S1 of the freewheeling switch, i.e., the first switch Q1, is switched from logic high to logic low. Therefore, the first switch Q1 is turned off, and the inductor current i... LThe current cannot flow through the body of the first switching transistor Q1, while the inductor current i L At this point, the current still tends to continue flowing in the original direction, so it has to find a new path and flow through the body diode of the first switching transistor Q1. The direction of current flow at this time is, for example, referring to... Figure 4 As mentioned earlier, the forward voltage of the body diode of the first switching transistor Q1 is much greater than the forward voltage of the transistor itself, meaning the voltage drop across the body diode is larger. Therefore, the inductor current i L The body diode flowing through the freewheeling switch increases the loss of the freewheeling switch, thus significantly reducing the efficiency of the PFC converter.

[0039] To address the aforementioned problems of reverse inductor current and low efficiency of PFC converters, this application proposes a simple and easy-to-implement solution, see [link to relevant documentation]. Figure 7 The diagrams shown all represent logical operations. The key to this solution is ensuring the freewheeling switch is turned off promptly, which requires adjusting the drive voltage applied to its gate G. Next, we will combine... Figures 7 to 9 The solution described in this application is explained in detail.

[0040] See Figure 7 The drive circuit device for a totem-pole power factor correction converter according to this application includes a controller 7, a current judgment circuit E, a selector A, and an arithmetic unit K. The controller 7 is, for example, a processor or DSP (or any device capable of performing the same function), which is used to control or generate the initial drive level of the converter's switching transistors. Here, the switching transistors include at least, for example... Figures 1 to 5 The first switch Q1 and the second switch Q2 shown are interconnected and are both wide-bandgap semiconductor devices (such as SiC MOSFETs or GaN FETs) operating at high frequencies (tens of kHz to hundreds of kHz). In this case, the initial drive level output by the controller 7 includes at least a first initial drive level S1 for controlling the first switch Q1 and a second initial drive level S2 for controlling the second switch Q2. It should be noted here that in Figure 7 In the embodiment of the present invention, the first initial drive level S1 and the second initial drive level S2 are not directly applied to the gates of the first switch Q1 and the second switch Q2 respectively, but are only used as initial drive levels to control the first switch Q1 and the second switch Q2. The drive level directly applied to the gates of the first switch Q1 and the second switch Q2 is actually the target drive level, as will be described in detail below.

[0041] In one implementation, the current determination circuit E is used to determine the inductor current i of the converter. LWhether it crosses zero. For this purpose, the current determination circuit E includes, for example, a first comparator 1 and a second comparator 2 (or any device capable of performing the same current determination function). Responding to the inductor current i L When the inductor current i crosses zero from positive to negative, the output level of the first comparator 1 changes from logic high (1) to logic low (0). In other words, when the inductor current i... L Always greater than zero, i L When the current is greater than 0, the output of the first comparator 1 is 1, while when the inductor current i L Decrease to less than or equal to zero, i L When <= 0, the output of the first comparator 1 is 0. This is in response to the inductor current i. L When the inductor current i crosses zero from negative to positive, the output level of the second comparator 2 changes from logic high (1) to logic low (0). In other words, when the inductor current i... L i is always less than zero L When the current is less than 0, the output of the second comparator 2 is 1, while when the inductor current i L Increase to greater than or equal to zero, i L When >= 0, the output of the second comparator 2 is 0.

[0042] In one implementation, selector A is connected to current determination circuit E, used to determine the current based on the converter's power supply voltage V. ac The comparison result with 0 selects either the output level of the current judgment circuit E or the logic high level 1, and outputs this as an intermediate control level. For this purpose, selector A includes, for example, a third comparator (not shown) for adjusting the power supply voltage V of the converter. ac Compare with 0. Specifically, selector A may also include, for example, a first selection switch 3 and a second selection switch 4 (or any device capable of performing the same level selection function), and the intermediate control level includes the first intermediate control level L output by the first selection switch 3. i_S1 and the second intermediate control level L output by the second selection switch 4 i_S2 In some implementations, the first selection switch 3 is connected to the first comparator 1, and the converter's power supply voltage V... ac V is less than 0 ac When <0, the output preset logic level is used as the first intermediate control level L. i_S1 Otherwise, at the power supply voltage V ac V is greater than or equal to 0 ac When >= 0, the output level of the first comparator 1 is used as the first intermediate control level L. i_S1 The output is then provided. Accordingly, for example, it is feasible to connect the second selection switch 4 to the second comparator 2, and to the converter's power supply voltage V. ac Not less than 0, i.e., V ac When >= 0, output a preset logic level as the second intermediate control level L.i_S2 Otherwise, at the power supply voltage V ac V is less than 0 ac When <0, the output level of the second comparator 2 is used as the second intermediate control level L. i_S2 The output is then provided. Here, the preset logic level can be, for example, a logic high level 1. In one embodiment of the invention, the preset logic level can also be a logic low level 0, and this logic low level 0 can be inverted using, for example, an inverter, to finally obtain a logic high level 1.

[0043] In one embodiment, the arithmetic unit K is connected to the selector A and is used to perform a logical operation between the intermediate control level and the initial drive level to generate a target drive level for driving the switching transistor. In one embodiment of the invention, the logical operation is, for example, a logical AND operation, or any other operation that ultimately yields a logical AND result after several steps. For example, the arithmetic unit K includes a first AND gate 5 and a second AND gate 6 (or any device capable of performing the same AND function), the first AND gate 5 converting the first intermediate control level L... i_S1 ANDed with the first initial drive level S1, the second AND gate 6 converts the second intermediate control level L... i_S2 The first target drive level S1' is ANDed with the second initial drive level S2. Thus, the target drive level includes the first target drive level S1' output by the first AND gate 5 and the second target drive level S2' output by the second AND gate 6. The first target drive level S1' is applied to the gate of the first switch Q1 and is used to drive the first switch Q1. The second target drive level S2' is applied to the gate of the second switch Q1 and is used to drive the second switch Q2.

[0044] According to another aspect, the present invention also relates to a driving method for a totem-pole power factor correction converter, which is implemented using a driving circuit arrangement according to the foregoing aspects. Reference will be made below. Figures 7 to 9 The working principle of the driving circuit device will be described in detail in conjunction with the driving method of the present invention.

[0045] First, the controller 7, such as a processor or DSP, generates initial drive levels S1 and S2 for the first switch Q1 and the second switch Q2 of the PFC converter, respectively. Then, the inductor current i flowing through the inductor L of the PFC converter is detected. L The current detection circuit E is used to determine the inductor current i of the converter. L Does it cross zero? This is used to detect the inductor current i. L At this time, various detection methods can be used, such as current transformers, resistor shunts, and Hall effect devices.

[0046] For example in Figure 8In the CCM mode shown, during the positive half-wave of the AC power supply voltage, i.e., V... ac When the inductor current i is greater than or equal to 0, the inductor current i L Always greater than zero, i L >0, meaning the inductor current i L It never exceeds zero. Therefore, the output of the first comparator 1 is 1, and the output of the first selection switch 3 is the same as the output of the first comparator 1 being 1, which is the first intermediate control level L. i_S1 =1, after performing an AND operation using the first AND gate 5 and the first initial drive level S1, the output of the first AND gate 5 remains the first initial drive level S1, that is, the first target drive level S1' = S1 used to drive the first switch Q1, which is the same as the first initial drive level S1. Meanwhile, according to Figure 7 As shown, because V ac When the value is greater than or equal to 0, the output of the second selection switch 4 is 1, which is the second intermediate control level L. i_S2 =1, after performing an AND operation using the second AND gate 6 and the second initial drive level S2, the output of the second AND gate 6 remains the second initial drive level S2, that is, the second target drive level S2' = S2 used to drive the second switch transistor Q2 as the main switch, which is the same as the second initial drive level S2, such as Figure 8 As shown.

[0047] And in Figure 9 In the DCM mode shown, during the positive half-wave of the AC power supply voltage, i.e., V... ac When the current is greater than or equal to 0, the first switching transistor Q1 acts as a freewheeling switch. Therefore, the drive voltage of Q1 needs to be adjusted to ensure it turns off promptly when the inductor current crosses zero. Specifically, the inductor current i is detected... L At time t2, the signal begins to cross from positive to negative zero, causing the output of the first comparator 1 to switch from 1 to 0. At this time, the output of the first selection switch 3 is the same as the output of the first comparator 1, i.e., the first intermediate control level L. i_S1 It also switches from 1 to 0. The first AND gate 5 switches the first intermediate control level L. i_S1 A bitwise AND operation is performed with the initial drive level S1, and the output S1' naturally switches from 1 to 0. Therefore, the drive voltage of the first switch Q1 is switched from the initial S1 = 1 to the first target drive level S1' = 0. Consequently, the first switch Q1 acts as a freewheeling switch in the inductor current i L The zero-crossing time t2 is promptly turned off. This avoids reverse current flow caused by the continued conduction of the first switching transistor Q1, which acts as a freewheeling switch. Meanwhile, according to... Figure 7 As shown, because V ac When the value is greater than or equal to 0, the output of the second selection switch 4 is 1, which is the second intermediate control level L. i_S2=1, after performing an AND operation using the second AND gate 6 and the second initial drive level S2, the output of the second AND gate 6 remains the second initial drive level S2, that is, the second target drive level S2' = S2 used to drive the second switch transistor Q2 as the main switch, which is the same as the second initial drive level S2, such as Figure 9 As shown. The above state continues from t2 to t3, that is, until the start of the next cycle.

[0048] In the negative half-wave of the AC power supply voltage, i.e., V ac When the current is less than 0, the second switch Q2 acts as a freewheeling switch. The drive voltage of Q2 needs to be adjusted to ensure it turns off promptly when the inductor current crosses zero. In this case, the first switch Q1 acts as the main switch, and its first target drive level S1' = S1, meaning it remains the same as the first initial drive level S1. In this situation, the inductor current i needs to be adjusted. L When the signal crosses zero from negative to positive, the second initial drive level S2 is adjusted in a timely manner, and the operation process is similar to that described above.

[0049] As can be seen from the above, by adopting the solution of this application, the reverse inductor current of the PFC converter in DCM mode is effectively avoided, the additional losses caused by it are eliminated, the power factor is improved, and the reverse inductor current i is prevented. L The body diode through which the freewheeling switch is connected further avoids increased losses in the freewheeling switch, significantly improving the efficiency of the PFC converter. Moreover, the topology of the driving circuit device in this application is relatively simple and easy to implement, requiring only a small number of comparators and selection switches or similar functional devices, resulting in very low cost.

[0050] The above-described solution in this application can be applied not only to Figure 1 and Figure 2 This circuit topology can be applied to any suitable extended circuit topology, for example, where the first switch Q1 comprises multiple first switches Q1 connected in parallel, and the second switch Q2 comprises multiple second switches Q2 connected in parallel, i.e., multiple first switches Q1 are connected in parallel and multiple second switches Q2 are connected in parallel. For example, in... Figure 10 In the circuit topology shown, the first switch Q1 and another first switch Q1y are connected in parallel, and the second switch Q2 and another second switch Q2y are connected in parallel. The above solution of this application can also be applied to another extended circuit topology, wherein a high-frequency half-bridge is formed by the first switch Q1 and the second switch Q2, and multiple high-frequency half-bridges are connected in parallel with each other in an alternating manner; that is, multiple high-frequency half-bridges are connected in parallel, and an inductor is connected between the middle of each high-frequency half-bridge (i.e., the point between two high-frequency switches on the same high-frequency half-bridge) and the power supply. For example, in... Figure 11In this circuit, a high-frequency half-bridge is formed by a first switching transistor Q1 and a second switching transistor Q2. An inductor L is connected at a certain point between the first switching transistor Q1 and the second switching transistor Q2, and the other end of the inductor L is connected to the power supply. Another high-frequency half-bridge is formed by another first switching transistor Q1x and another second switching transistor Q2x. These two high-frequency half-bridges are connected in parallel. Another inductor Lx is connected at a certain point between another first switching transistor Q1x and another second switching transistor Q2x, and the other end of the inductor Lx is connected to the power supply.

[0051] Furthermore, this application also relates to a totem-pole power factor correction converter having a drive circuit arrangement according to the foregoing aspects. The aspects and advantages described above regarding the drive circuit arrangement also apply accordingly to the totem-pole power factor correction converter according to the present invention, and will not be repeated here.

[0052] From the teachings given in the foregoing description and related drawings, many modifications and other embodiments of the present disclosure will become apparent to those skilled in the art. Therefore, it is to be understood that embodiments of the present disclosure are not limited to the specific embodiments disclosed, and modifications and other embodiments are intended to be included within the scope of this disclosure. Furthermore, although the foregoing description and related drawings have described exemplary embodiments in the context of certain example combinations of components and / or functions, it should be appreciated that different combinations of components and / or functions may be provided by alternative embodiments without departing from the scope of this disclosure. In this regard, for example, other combinations of components and / or functions that differ from those explicitly described above are also contemplated within the scope of this disclosure. Although specific terms are used herein, they are used in a general and descriptive sense only and are not intended to be limiting.

Claims

1. A drive circuit device for a totem-pole power factor correction converter, comprising: The controller (7) is configured to control the initial drive level of the switching transistor of the converter; The current determination circuit (E) is configured to determine the inductor current (i) of the converter. L Does it cross zero? Selector (A) is configured to respond to the power supply voltage (V) of the converter. ac Compare 0 with 0; as well as Based on the comparison results, one of the output level of the current judgment circuit (E) and the preset logic level is selected as the intermediate control level for output; as well as The arithmetic unit (K) is configured to perform a logical operation between the intermediate control level and the initial drive level to generate a target drive level for driving the switching transistor.

2. The driving circuit device according to claim 1, wherein, The current determination circuit (E) includes a first comparator (1) and a second comparator (2), wherein the first comparator (1) is configured to respond to the inductor current (i L The output level changes from logic high to logic low due to a positive to negative zero crossing, and the second comparator (2) is configured to respond to the inductor current (i L The output level changes from logic high to logic low when the signal crosses zero from negative to positive.

3. The driving circuit device according to claim 2, wherein, The selector (A) includes a first selection switch (3) and a second selection switch (4), and the intermediate control level includes a first intermediate control level (L) output by the first selection switch (3). i_S1 ) and the second intermediate control level (L) output by the second selection switch (4). i_S2 ).

4. The driving circuit device according to claim 3, wherein, The first selection switch (3) is connected to the first comparator (1) and is configured as follows: In response to the power supply voltage (V) of the converter ac If the value is less than 0, the preset logic level is output as the first intermediate control level (L). i_S1 ),or In response to the power supply voltage (V) of the converter ac The output level of the first comparator (1) is not less than 0 and is used as the first intermediate control level (L). i_S1 Output it.

5. The driving circuit device according to claim 3, wherein, The second selection switch (4) is connected to the second comparator (2) and is configured to: In response to the power supply voltage (V) of the converter ac The preset logic level is output as the second intermediate control level (L) when it is not less than 0. i_S2 ),or In response to the power supply voltage (V) of the converter ac If the value is less than 0, the output level of the second comparator (2) is used as the second intermediate control level (L). i_S2 Output it.

6. The driving circuit device according to claim 3, wherein, The switching transistors include at least a first switching transistor (Q1) and a second switching transistor (Q2) connected to each other, and the initial drive level output by the controller (7) includes at least a first initial drive level (S1) for participating in the control of the first switching transistor (Q1) and a second initial drive level (S2) for participating in the control of the second switching transistor (Q2).

7. The driving circuit device according to claim 6, wherein, The arithmetic unit (K) includes a first AND gate (5) and a second AND gate (6), wherein the first AND gate (5) is configured to convert the first intermediate control level (L) into a value. i_S1 The second AND gate (6) is configured to AND the second intermediate control level (L) with the first initial drive level (S1), and the second AND gate (6) is configured to AND the second intermediate control level (L) with the first initial drive level (S1). i_S2 The second initial drive level (S2) is ANDed with the first initial drive level (S2).

8. The driving circuit device according to claim 7, wherein, The target drive level includes a first target drive level (S1') output by the first AND gate (5) and a second target drive level (S2') output by the second AND gate (6). The first target drive level (S1') is configured to drive the first switch (Q1), and the second target drive level (S2') is configured to drive the second switch (Q2).

9. The drive circuit device according to any one of claims 6 to 8, wherein, The first switch (Q1) includes a plurality of first switch transistors (Q1) connected in parallel with each other, and the second switch transistor (Q2) includes a plurality of second switch transistors (Q2) connected in parallel with each other.

10. The drive circuit device according to any one of claims 6 to 8, wherein, Multiple half-bridges, each consisting of the first switch (Q1) and the second switch (Q2), are connected in parallel with each other in an alternating manner. Each half-bridge is connected in parallel with an inductor between itself and the power supply.

11. The drive circuit device according to any one of claims 6 to 8, wherein, The preset logic level is a logic high level, and the logic operation is a logical AND operation.

12. A totem-pole power factor correction converter, comprising a drive circuit device according to any one of the preceding claims.

13. A driving method for a totem-pole power factor correction converter, implemented using a driving circuit device according to any one of the preceding claims, comprising the following steps: Generate the initial drive level for the switching transistors of the converter; Determine the inductor current (i) of the converter L Does it cross zero? According to the inductor current (i) L The output level is generated by whether it is a positive zero-crossing or a negative zero-crossing. The power supply voltage (V) of the converter ac The output level is compared with 0, and based on the comparison result, one of the output level and the preset logic level is selected as the intermediate control level for output; as well as The intermediate control level and the initial drive level are logically operated to generate a target drive level for driving the switching transistor.

14. The driving method according to claim 13, wherein, The preset logic level is a logic high level, and the logic operation is a logical AND operation.

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