Wired transmitter with overvoltage protection

Abstract

This application discloses a wired transmitter with overvoltage protection, comprising a digital-to-analog converter (DAC) and a line driver. The DAC generates a plurality of first output signals based on a digital code, wherein a first circuit in the DAC operates in a first voltage domain, a second circuit in the DAC operates in a second voltage domain, and the upper limit of the first voltage domain is lower than the upper limit of the second voltage domain. The line driver operates in the second voltage domain and generates a plurality of second output signals based on the first output signals, wherein each of the DAC and the line driver is implemented via a plurality of transistors corresponding to the first voltage domain.

Description

Technical Field

[0001] This application relates to wired transmitters, and more specifically to a wired transmitter with overvoltage protection, which can be implemented by a transistor with relatively low withstand voltage. Background Technology

[0002] As manufacturing processes advance, transistors are becoming smaller, leading to lower voltage ratings. However, in current Ethernet applications, transmitters still need to transmit signals at high voltage levels. If low-voltage transistors are used directly to implement the transmitter, these transistors would be subjected to excessive voltage, causing damage and reducing transmitter reliability. Summary of the Invention

[0003] This application provides a wired transmitter with overvoltage protection, which can be implemented by a transistor with relatively low withstand voltage, to improve the shortcomings of the prior art.

[0004] This application provides a wired transmitter, including a digital-to-analog converter (DAC) and a line driver. The DAC generates a plurality of first output signals based on a digital code, wherein a first circuit in the DAC operates in a first voltage domain, a second circuit in the DAC operates in a second voltage domain, and the upper limit of the first voltage domain is lower than the upper limit of the second voltage domain. The line driver operates in the second voltage domain and generates a plurality of second output signals based on the first output signals, wherein each of the DAC and the line driver is implemented via a plurality of transistors corresponding to the first voltage domain.

[0005] The features, implementation, and effects of this application are described in detail below with reference to the accompanying drawings, using preferred embodiments. Attached Figure Description

[0006] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0007] Figure 1 A schematic diagram of a wired transmitter provided in an embodiment of this application;

[0008] Figure 2A Provided for the embodiments of this application Figure 1 A schematic diagram of a digital-to-analog converter in a computer.

[0009] Figure 2B Provided for the embodiments of this application Figure 2A A schematic diagram of the buffer in the circuit;

[0010] Figure 3A Provided for the embodiments of this application Figure 1 A schematic diagram of the line driver in the diagram; and

[0011] Figure 3B Provided for the embodiments of this application Figure 3A A schematic diagram of the amplifier circuit in the image.

[0012] [Symbol Explanation]

[0013] 100: Wired transmitter

[0014] 110: Digital-to-Analog Converter

[0015] 120: Line driver

[0016] 205: Signal Generation Circuit

[0017] 210: Bias voltage generation circuit

[0018] 220: Protection Circuit

[0019] 230: Buffer

[0020] 240[1]~240

[64] : Current source circuit

[0021] 310, 315: Amplifier circuits

[0022] 310-1: Common Source Circuit

[0023] 310-2: Common Gate Circuit

[0024] 310-3: Series Circuit

[0025] DIN: Numeric Code

[0026] N11, N12: Nodes

[0027] NM1~NM25: N-type transistors

[0028] NP: Power Node

[0029] PM1~PM19: P-type transistors

[0030] R1~R9: Resistors

[0031] S1~S64, S1B~S64B: Bits

[0032] SS1~SS4: Signals

[0033] V1, V2: Voltage

[0034] VB, VB1~VB5: Bias voltage

[0035] VD: Preset voltage

[0036] VDD: Supply voltage

[0037] VF: Feedback signal

[0038] VO1, VO2, VOP, VON: Output signals

[0039] VP: Power supply voltage

[0040] VREF: Reference Voltage

[0041] VS1~VS4: Switching voltage Detailed Implementation

[0042] All terms used herein have their common meanings. The definitions of the above terms in commonly used dictionaries, and any examples of the use of any term discussed herein, are merely illustrative and should not be construed as limiting the scope or meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0043] As used herein, “coupled” or “connected” can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or acting on each other. As used herein, the term “circuit” can be a device consisting of at least one transistor and / or at least one active or passive component connected in a certain manner to process signals.

[0044] Figure 1 This is a schematic diagram of a wired transmitter 100 provided in an embodiment of this application. In some embodiments, the wired transmitter 100 may be implemented with a low-voltage transistor and has several overvoltage protection mechanisms for transmitting data signals with higher bit levels (e.g., data signals transmitted via an Ethernet network).

[0045] The wired transmitter 100 includes a digital-to-analog converter 110 and a line driver 120. The digital-to-analog converter 110 generates multiple output signals VO1 and VO2 according to the digital code DIN. In some embodiments, a portion of the circuitry in the digital-to-analog converter 110 (hereinafter referred to as the first circuitry) operates in a first voltage domain, and a portion of the circuitry in the digital-to-analog converter 110 (hereinafter referred to as the second circuitry) operates in a second voltage domain, with the upper limit of the first voltage domain being lower than the upper limit of the second voltage domain. For example, the upper limit of the first voltage domain is approximately 1.8 volts, and the lower limit of the first voltage domain is approximately 0 volts. The upper limit of the second voltage domain is approximately 3.3 volts, and the lower limit of the second voltage domain is approximately 0 volts. The above values ​​regarding the upper and lower limits of the first and second voltage domains are for reference only and are not intended to limit the scope of this application.

[0046] The line driver 120 operates in a second voltage domain and generates multiple output signals VOP and VON based on multiple output signals VO1 and VO2. In some embodiments, the multiple output signals VOP and VON may be data signals transmitted via an Ethernet network. In some embodiments, each of the digital-to-analog converter 110 and the line driver 120 may be implemented by a plurality of transistors corresponding to the first voltage domain. In other words, the digital-to-analog converter 110 and the line driver 120 may be implemented by low-voltage transistors (e.g., the highest voltage they can withstand is the same as the upper limit of the first voltage domain) and may operate in a second voltage domain with a higher upper limit. Thus, the wired transmitter 100 can be implemented using low-voltage transistors and is suitable for high-voltage applications.

[0047] In some embodiments, the wired transmitter 100 can selectively operate in a first mode (or power-saving mode) and a second mode (or normal mode, transmission mode, etc.). In the first mode, the digital-to-analog converter 110 and the line driver 120 can be turned off and not generate multiple output signals VOP and VON. In the second mode, the digital-to-analog converter 110 and the line driver 120 can operate normally and generate multiple output signals VOP and VON. In the first mode and / or the second mode, the overvoltage protection mechanism in the digital-to-analog converter 110 and the line driver 120 can ensure that the aforementioned low-voltage transistors are not damaged, thereby improving overall lifespan and reliability. On the other hand, in the first mode, the overvoltage protection mechanism can further reduce the leakage current in the digital-to-analog converter 110 and the line driver 120, thereby reducing overall power consumption. Detailed configuration methods here will be described later with reference to the various embodiments.

[0048] Figure 2A Provided for the embodiments of this application Figure 1 A schematic diagram of the digital-to-analog converter 110 is shown. In some embodiments, the digital-to-analog converter 110 may be a current-type digital-to-analog converter. The digital-to-analog converter 110 includes a signal generation circuit 205, a bias generation circuit 210, a protection circuit 220, a buffer 230, multiple current source circuits 240[1] to 240

[64] , and multiple resistors R1 to R4. In some embodiments, the aforementioned first circuit (i.e., the circuit operating in the first voltage domain) includes the signal generation circuit 205 and the bias generation circuit 210, and the aforementioned second circuit (i.e., the circuit operating in the second voltage domain) may include the buffer 230, multiple current source circuits 240[1] to 240

[64] , and multiple resistors R1 to R4. In some embodiments, the second circuit transmits a preset voltage VD to the power node NP in the first mode to provide overvoltage protection for the digital-to-analog converter 110, wherein the digital-to-analog converter 110 is level-driven via the power node NP in the second mode.

[0049] In detail, signal generation circuit 205 generates multiple bits S1 to S64 of the digital code DIN, and generates multiple bits S1B to S64B, wherein one corresponding bit among S1 to S64 is opposite to one corresponding bit among S1B to S64B. For example, when bit S1 has a logic value of 1, bit S1B has a logic value of 0. Or, when bit S1 has a logic value of 0, bit S1B has a logic value of 1. And so on, when bit S64 has a logic value of 1 (or logic value of 0), bit S64B has a logic value of 0 (or logic value of 1). In some embodiments, signal generation circuit 205 may include a codec and several inverters. Bias generation circuit 210 generates a bias voltage VB. In some embodiments, bias generation circuit 210 may be, but is not limited to, a low-dropout regulator. As mentioned above, signal generation circuit 205 and bias generation circuit 210 may be a first circuit operating in a first voltage domain. In other words, the upper limit of the level of each of the multiple bits S1 to S64, the multiple bits S1B to S64B, and the bias voltage VB is the same as the upper limit of the first voltage domain (e.g., 1.8 volts as mentioned above).

[0050] Protection circuit 220 selectively transmits a preset voltage VD to power node NP based on switching voltage VS1, wherein the level of preset voltage VD is the same as the upper limit of the first voltage domain. For example, protection circuit 220 includes a P-type transistor PM1, which can be selectively turned on based on switching voltage VS1 to transmit the preset voltage VD to power node NP. Specifically, a first terminal (e.g., the source) of P-type transistor PM1 receives the preset voltage VD, a second terminal (e.g., the drain) of P-type transistor PM1 is coupled to power node NP, and a control terminal (e.g., the gate) of P-type transistor PM1 receives switching voltage VS1.

[0051] In some embodiments, the switching voltage VS1 originates from a quasi-shifter (not shown), which outputs a switching voltage VS1 with a first quasi-level (e.g., the same as the lower limit of the second voltage domain (e.g., 0 volts)) in a first mode and a switching voltage VS1 with a second quasi-level (e.g., the same as the upper limit of the second voltage domain (e.g., 3.3 volts)) in a second mode. Thus, when operating in the first mode, the P-type transistor PM1 turns on in response to the switching voltage VS1 with the first quasi-level, transmitting the preset voltage VD to the power node NP. Alternatively, when operating in the second mode, the P-type transistor PM1 does not turn on in response to the switching voltage VS1 with the second quasi-level, so as not to transmit the preset voltage VD to the power node NP. In some embodiments, the preset voltage VD originates from a low-dropout regulator (not shown), which can generate a preset voltage VD with a level equal to the upper limit of the first voltage domain (e.g., 1.8 volts).

[0052] Buffer 230 generates a power supply voltage VP based on multiple output signals VO1 and VO2 and a reference voltage VREF, and transmits this power supply voltage VP to power node NP. In some embodiments, the reference voltage VREF may be set to half the upper limit of the second voltage domain. For example, as previously described, the upper limit of the second voltage domain may be approximately 3.3 volts, and the reference voltage VREF may be approximately 1.65 (i.e., 3.3 / 2) volts. In some embodiments, the level of power node NP is determined by a preset voltage VD in a first mode and by the power supply voltage VP in a second mode. For example, in the second mode, P-type transistor PM1 is not turned on and the preset voltage VD is not transmitted to power node NP. Under this condition, the level of power node NP is the same as the power supply voltage VP. Alternatively, in the first mode, buffer 230 may be turned off (as described later). Figure 2B (as described above) without generating a power supply voltage VP, and the P-type transistor PM1 is turned on to transfer a preset voltage VD to the power node NP. Under this condition, the level of the power node NP is the same as the preset voltage VD.

[0053] Multiple current source circuits 240[1] to 240

[64] are selectively turned on according to the digital code DIN and biased by a bias voltage VB to generate multiple output signals VO1 and VO2 via multiple nodes N11 and N12. In detail, each of the multiple current source circuits 240[1] to 240

[64] includes several N-type transistors, and these N-type transistors have the same arrangement in each current source circuit 240[1] to 240

[64] . Taking current source circuit 240[1] as an example, current source circuit 240[1] includes several N-type transistors NM1 to NM5. The first terminal (e.g., the drain) of N-type transistor NM1 is coupled to the second terminal (e.g., the source) of multiple N-type transistors NM2 and NM3, the second terminal of N-type transistor NM1 is coupled to ground, and the control terminal (e.g., the gate) of N-type transistor NM1 receives the bias voltage VB. The first terminal of N-type transistor NM2 is coupled to the second terminal of N-type transistor NM4, and the control terminal of N-type transistor NM2 receives bit S1. The first terminal of N-type transistor NM3 is coupled to the second terminal of N-type transistor NM5, and the control terminal of N-type transistor NM3 receives bit S1B. The first terminal of N-type transistor NM4 is coupled to node N11, and the first terminal of N-type transistor NM4 is coupled to node N12, and the control terminals of the plurality of N-type transistors NM4 and NM5 receive a preset voltage VD.

[0054] With the above configuration, N-type transistor NM1 can generate a current by being biased by bias voltage VB. Multiple N-type transistors NM2 and NM3 can be selectively turned on according to bits S1 and S1B to determine the current flow to one of nodes N11 and N12. Multiple N-type transistors NM4 and NM5 can be coupled between multiple N-type transistors NM2 and NM3 and multiple resistors R1 and R2, and biased according to a preset voltage VD to provide overvoltage protection for multiple N-type transistors NM1 to NM3. By analogy, the configuration and related operation of the multiple N-type transistors in the remaining current source circuits 240[2] to 240

[64] should be understood, so they will not be repeated here. In other embodiments, multiple current source circuits 240[1] to 240

[64] can share transistors NM4 and NM5. For example, Figure 2A Only one set of transistors NM4 and NM5 can be set, and other transistors (e.g., multiple N-type transistors NM1 to NM3) in multiple current source circuits 240[1] to 240

[64] can be connected to the set of transistors NM4 and NM5.

[0055] Resistor R1 is coupled between power node NP and node N11 to convert the current flowing through node N11 into an output signal VO1. Resistor R2 is coupled between power node NP and node N12 to convert the current flowing through node N12 into an output signal VO2. Multiple resistors R3 and R4 are coupled between nodes N11 and N12 to generate a feedback signal VF based on the multiple output signals VO1 and VO2, and transmit the feedback signal VF to buffer 230, so that buffer 230 can generate a power supply voltage VP based on the multiple output signals VO1 and VO2.

[0056] As previously stated, the wired transmitter 100 operates normally when operating in the second mode. In some embodiments, the levels of the multiple output signals VO1 and VO2 in the second mode can be a maximum of approximately 2.15 volts and a minimum of approximately 1.15 volts. The multiple N-type transistors NM4 and NM5 can withstand the voltage swing introduced by the multiple output signals VO1 and VO2 to provide overvoltage protection for the multiple N-type transistors NM1 to NM3. In the first mode, the digital-to-analog converter 110 is turned off and does not generate multiple output signals VOP and VON. Under this condition, the protection circuit 220 can be turned on to set the level of the power node NP to a preset voltage VD, so that the levels of the multiple output signals VOP and VON are the same as the preset voltage VD. In this way, overvoltage protection can be provided for the multiple current source circuits 240[1] to 240

[64] , thereby ensuring that the multiple N-type transistors NM1 to NM5 do not experience overvoltage.

[0057] On the other hand, in some embodiments, each of the multiple current source circuits 240[1] to 240

[64] is implemented with several N-type transistors. In this way, the signal generation circuit 205 can operate in a first voltage domain with a lower upper limit, thereby reducing the difficulty of implementing high-voltage applications with transistors having low voltage tolerance.

[0058] Figure 2B Provided for the embodiments of this application Figure 2A A schematic diagram of buffer 230. In some embodiments, the input terminal of buffer 230 that receives the reference voltage VREF (e.g., is...) Figure 2A The positive input terminal of the buffer 230 is also switched to receive a preset voltage VD in the first mode to provide overvoltage protection for the buffer 230.

[0059] Specifically, the buffer 230 includes multiple N-type transistors NM6 to NM10 and multiple P-type transistors PM2 to PM5. The first terminal of N-type transistor NM6 is coupled to the second terminals of multiple N-type transistors NM7 and NM8, the second terminal of N-type transistor NM6 is coupled to ground, and the control terminal of N-type transistor NM6 receives a bias voltage VB. The first terminal of N-type transistor NM7 is coupled to the second terminal of N-type transistor NM9, and the control terminal of N-type transistor NM7 (equivalent to...) Figure 2A The negative input of the buffer 230 is coupled to Figure 2A The node between multiple resistors R3 to R4 is used to receive the feedback signal VF. The first terminal of N-type transistor NM8 is coupled to the second terminal of N-type transistor NM10, and the control terminal of N-type transistor NM8 (equivalent to...) Figure 2A The positive input terminal of buffer 230 receives a reference voltage VREF. The first terminal of N-type transistor NM9 is coupled to the second terminal of P-type transistor PM2, the first terminal of N-type transistor NM10 is coupled to the second terminal of P-type transistor PM3, and the control terminals of the plurality of N-type transistors NM9 and NM10 receive a switching voltage VS2. In some embodiments, the switching voltage VS2 comes from a one-bit quasi-shifter (not shown), which can output a switching voltage VS2 with a level equal to the upper limit of a first voltage domain (e.g., 1.8 volts) in a first mode, and can output a switching voltage VS2 with a level equal to the upper limit of a second voltage domain (e.g., 3.3 volts) in a second mode.

[0060] The first terminals of multiple P-type transistors PM2 to PM4 receive a supply voltage VDD (which may be the same as the upper limit of the second voltage domain), and the second terminal of P-type transistor PM2 is coupled to the control terminal to form a diode-connected configuration, generating a voltage V1. The control terminal of P-type transistor PM3 receives voltage V1, and the second terminal of P-type transistor PM3 generates voltage V2. The second terminal of P-type transistor PM4 outputs a power supply voltage VP, and the control terminal of P-type transistor PM4 receives voltage V2. The first terminal of P-type transistor PM5 receives a preset voltage VD, and the second terminal of P-type transistor PM5 is coupled to the control terminal of N-type transistor NM8, and the control terminal of P-type transistor PM5 receives a switching voltage VS3. In some embodiments, the switching voltage VS3 comes from a one-bit quasi-shifter (not shown), which can output a switching voltage VS3 with a level the same as the lower limit of the first or second voltage domain (e.g., 0 volts) in a first mode, and can output a switching voltage VS3 with a level the same as the upper limit of the first voltage domain (e.g., 1.8 volts) in a second mode.

[0061] With the above configuration, N-type transistor NM6 can generate a current by being biased by bias voltage VB, thereby driving multiple N-type transistors NM7 and NM8. As mentioned earlier, in the second mode, the level of the reference voltage VREF is approximately 1.65 volts, and the level of the switching signal VS2 is the same as the upper limit of the second voltage domain (e.g., 3.3 volts). Under this condition, multiple N-type transistors NM9 and NM10 can be turned on to withstand excess voltage, ensuring that all transistors in the buffer 230 do not experience overvoltage. In addition, in the first mode, the node (not shown) of the output reference voltage VREF is switched to a high impedance state (equivalent to stopping the output reference voltage VREF) without affecting the level of N-type transistor NM8, the level of the switching signal VS2 is switched to the same as the upper limit of the first voltage domain (e.g., 1.8 volts), and P-type transistor PM5 is turned on to transmit the preset voltage VD to N-type transistor NM8. Under these conditions, the voltages at the control terminals of the multiple N-type transistors NM8, NM9, and NM10 are all the same as the upper limit of the first voltage domain, thereby ensuring that none of the transistors in the buffer 230 experience overvoltage. In other words, the multiple N-type transistors NM9 and NM10 and the P-type transistor PM5 can provide overvoltage protection for the buffer 230 in different modes.

[0062] Figure 3A Provided for the embodiments of this application Figure 1A schematic diagram of the line driver 120 is shown. The line driver 120 includes multiple amplifier circuits 310 and 315, multiple resistors R5 to R8, multiple N-type transistors NM11 and NM12, and multiple P-type transistors PM6 to PM8. The multiple amplifier circuits 310 and 315 generate multiple output signals VOP and VON based on multiple output signals VO1 and VO2.

[0063] Amplifier circuit 310 receives output signal VO1 at its positive input terminal and generates output signal VOP at one output terminal. A first terminal of resistor R5 is coupled to another output terminal of amplifier circuit 310, and a second terminal of resistor R5 and a first terminal of resistor R6 are coupled to the negative input terminal of amplifier circuit 310. A second terminal of resistor R6 is coupled to a first terminal of N-type transistor NM11. A second terminal of N-type transistor NM11 is coupled to a first terminal of P-type transistor PM6, and the control terminal of N-type transistor NM11 receives switching voltage VS2. A second terminal of P-type transistor PM6 receives reference voltage VREF, and the control terminal of P-type transistor PM6 receives switching voltage VS4. In some embodiments, switching voltage VS4 originates from a one-bit quasi-shifter (not shown), which can output a switching voltage VS4 having a level equal to the lower limit (e.g., 0 volts) of the first or second voltage domain in a first mode, and can output a switching voltage VS4 having a level equal to the upper limit (e.g., 1.8 volts) of the first voltage domain in a second mode. The first terminal of the P-type transistor PM8 receives a preset voltage VD, the second terminal of the P-type transistor PM8 receives a reference voltage VREF, and the control terminal of the P-type transistor PM8 receives a switching voltage VS3.

[0064] As previously described, in the second mode, the level of switching voltage VS2 is the same as the upper limit of the second voltage domain, the level of switching voltage VS3 is the same as the lower limit of either the first or second voltage domain, and the level of switching voltage VS4 is the same as the upper limit of the first voltage domain. Under these conditions, both N-type transistor NM11 and P-type transistor PM6 are turned on, P-type transistor PM8 is not turned on, and neither N-type transistor NM11 nor the multiple P-type transistors PM6 and PM8 will experience overvoltage. N-type transistor NM11 and P-type transistor PM6 can transfer the reference voltage VREF (which is 1.65 volts in the second mode) to multiple resistors R5 and R6. Thus, multiple resistors R5 and R6 can be used to set the gain of amplifier circuit 310. For example, if the resistance ratio of resistors R5 and R6 is 6:4, the gain of amplifier circuit 310 can be set to 2.5 accordingly.

[0065] Alternatively, as previously stated, in the first mode, the level of switching voltage VS2 is the same as the upper limit of the first voltage domain, and the levels of multiple switching voltages VS3 and VS4 are the same as the lower limit of the first or second voltage domain. Under this condition, N-type transistor NM11 and P-type transistor PM6 are both off, P-type transistor PM8 is on, and neither N-type transistor NM11 nor multiple P-type transistors PM6 and PM8 will experience overvoltage. As previously stated, since the node of the output reference voltage VREF presents high impedance in the first mode (equivalent to stopping the reference voltage VREF), the level of the second terminal of P-type transistor PM6 will be determined by the preset voltage VD transmitted from P-type transistor PM6. Since N-type transistor NM11 and P-type transistor PM6 are off in the second mode, the output impedance of amplifier circuit 310 can be increased (e.g., the impedance coupled to the output terminal of resistor R5), thereby reducing leakage current in the circuit.

[0066] The setup and operation of amplifier circuit 315, N-type transistor NM12, P-type transistor PM7 and multiple resistors R7 to R8 are the same as those of amplifier circuit 310, N-type transistor NM11, P-type transistor PM6 and multiple resistors R5 to R6, so they will not be repeated here.

[0067] Figure 3B Provided for the embodiments of this application Figure 3A A schematic diagram of amplifier circuit 310 is shown. In some embodiments, Figure 3B The circuit shown can also be used to implement... Figure 3A The amplifier circuit 315 is described above. In this example, the amplifier circuit 310 may be a folded common-source common-gate amplifier to generate an output signal VOP with a high voltage swing. The amplifier circuit 310 includes a common-source circuit 310-1, a common-gate circuit 310-2, and a cascaded circuit 310-3. The common-source circuit 310-1 generates signals SS1 and SS2 based on the output signal VO1. The common-gate circuit 310-2 generates signals SS3 and SS4 based on signals SS1 and SS2. The cascaded circuit 310-3 generates the output signal VOP based on signals SS3 and SS4. In some embodiments, each of the common-source circuit 310-1, the common-gate circuit 310-2, and the cascaded circuit 310-3 includes several transistors to withstand excess voltage to provide overvoltage protection for other transistors in the corresponding circuit.

[0068] In detail, the common-source circuit 310-1 includes multiple N-type transistors NM13 to NM17. The first terminal of N-type transistor NM13 is coupled to the second terminals of multiple N-type transistors NM14 and NM15, the second terminal of NM13 is coupled to ground, and the control terminal of NM13 receives a bias voltage VB1. The first terminal of NM14 is coupled to the second terminal of NM16, and the control terminal of NM13 receives an output signal VO1. The first terminal of NM15 is coupled to the second terminal of NM17, and the control terminal of NM15 is coupled to... Figure 3A The node between multiple resistors R5 and R6. The first terminals of multiple N-type transistors NM16 and NM17 generate signals SS1 and SS2 respectively, and the control terminals of multiple N-type transistors NM16 and NM17 receive bias voltage VS2.

[0069] The common-gate circuit 310-2 includes multiple N-type transistors NM18 to NM21 and multiple P-type transistors PM9 to PM15. The first terminals of the multiple P-type transistors PM9 and PM10 receive the supply voltage VDD. The second terminal of P-type transistor PM9 receives signal SS2 and is coupled to the first terminal of P-type transistor PM11. The control terminals of the multiple P-type transistors PM9 and PM10 receive a bias voltage VB5. The second terminal of P-type transistor PM10 receives signal SS1 and is coupled to the first terminal of P-type transistor PM12. The second terminal of P-type transistor PM11 is coupled to the first terminal of P-type transistor PM13. The control terminals of the multiple P-type transistors PM11 and PM12 receive a bias voltage VB4. The second terminal of P-type transistor PM12 is coupled to the first terminal of P-type transistor PM14 and the first terminal of N-type transistor NM21, generating signal SS3. The second terminal of P-type transistor PM13 is coupled to the first terminal and control terminal of N-type transistor NM18, and the second terminal of N-type transistor NM18 is coupled to ground. The second terminal of P-type transistor PM14 is coupled to the first terminal of P-type transistor PM15, and the control terminal of P-type transistor PM14 receives a bias voltage VB3. The second terminal of P-type transistor PM15 is coupled to the first terminal of N-type transistor NM19, and the control terminals of P-type transistor PM15 and N-type transistor NM21 receive a bias voltage VD. The second terminal of N-type transistor NM21 is coupled to the first terminal of N-type transistor NM20, and the control terminal of N-type transistor NM21 receives a preset voltage VD. The second terminal of N-type transistor NM20 is coupled to the first terminal of N-type transistor NM19 to generate signal SS4, and the control terminal of N-type transistor NM20 receives a bias voltage VB2. The control terminal of N-type transistor NM19 is coupled to the control terminal of N-type transistor NM18, and the second terminal of N-type transistor NM19 is coupled to ground.

[0070] The cascaded circuit 310-3 includes multiple N-type transistors NM22 to NM25, multiple P-type transistors PM9 to PM19, and resistor R9. The first terminals of the multiple P-type transistors PM16 and PM17 receive a supply voltage VDD. The second terminal of P-type transistor PM16 is coupled to the first terminal of P-type transistor PM18, and the second terminal of P-type transistor PM17 is coupled to the first terminal of P-type transistor PM19. The control terminals of the multiple P-type transistors PM16 and PM17 receive a signal SS3. The second terminal of P-type transistor PM18 is coupled to the first terminal of resistor R9 and the first terminal of N-type transistor NM22. The second terminal of P-type transistor PM19 is coupled to the second terminal of resistor R9 and the first terminal of N-type transistor NM23. The control terminals of the multiple P-type transistors PM18 and PM19 receive a preset voltage VD. The second terminal of resistor R9 is one output terminal of amplifier circuit 310 (which generates an output signal VOP), and the first terminal of resistor R9 is another output terminal of amplifier circuit 310 (which is coupled to...). Figure 3A (R5 in the circuit). The second terminal of N-type transistor NM22 is coupled to the first terminal of N-type transistor NM24, and the second terminal of N-type transistor NM23 is coupled to the first terminal of N-type transistor NM25. The control terminals of multiple N-type transistors NM22 and NM23 receive a preset voltage VD. The second terminals of multiple N-type transistors NM24 and NM25 are coupled to ground, and the control terminals of multiple N-type transistors NM24 and NM25 receive signal SS4.

[0071] like Figure 3B As shown, in this example, the multiple output terminals of amplifier circuit 310 are coupled to each other via resistor R9, wherein the resistance value of resistor R9 is the same as that of the amplifier circuit 310. Figure 3AThe values ​​of multiple resistors R5 and R6 are related. In one example, assuming the load (e.g., the impedance of the transmission line) to be driven by the output terminal generating the output signal VOP (i.e., the second terminal of resistor R9) has a resistance of R (e.g., 50 ohms, but not limited to 50 ohms), the resistance of resistor R9 can be set to n times R, the resistance of resistor R5 can be set to 0.6 * n times R, and the resistance of resistor R6 can be set to 0.4 * n times R. Under this condition, the current flowing through P-type transistors PM17, PM19, N-type transistor NM23, and N-type transistor NM25 (i.e., the current path in cascade circuit 310-3 related to the output terminal generating the output signal VOP) is n times the current flowing through P-type transistors PM16, PM18, N-type transistor NM22, and N-type transistor NM24 (i.e., the current path in cascade circuit 310-3 related to the output terminal coupled to resistor R5). Thus, better impedance matching can be achieved. In some embodiments, the size of P-type transistor PM17 can be n times the size of P-type transistor PM16, the size of P-type transistor PM19 can be n times the size of P-type transistor PM18, the size of N-type transistor NM23 can be n times the size of N-type transistor NM22, and the size of N-type transistor NM25 can be n times the size of N-type transistor NM24. In some embodiments, n can be any value greater than 1, that is, the resistance value of resistor R9 can be set to a complex multiple of the resistance value of the load to be driven by the output signal VOP. In some embodiments, n can be 20, but this application is not limited thereto.

[0072] On the other hand, since the first end of resistor R9 is coupled to Figure 3A The resistor R5 is further coupled to resistor R6, N-type transistor NM11, and P-type transistor PM6. As mentioned earlier, in the first mode, N-type transistor NM11 and P-type transistor PM6 will not conduct, making the equivalent impedance formed on the first terminal of resistor R9 higher, thereby increasing the output impedance. In this way, it is possible to prevent signals from being fed back from the load terminal (e.g., the load to be driven by the output signal VOP) to amplifier circuit 310, thereby reducing the leakage current of amplifier circuit 310.

[0073] In the first mode, the signal levels received by the control terminals of each of the multiple N-type transistors NM16, NM17, NM21, NM22, and NM23 and the multiple P-type transistors PM13, PM15, PM18, and PM19 are all the same as the upper limit of the first voltage domain (e.g., 1.8 volts). Accordingly, the multiple N-type transistors NM16, NM17, NM21, NM22, and NM23 and the multiple P-type transistors PM13, PM15, PM18, and PM19 can withstand excess voltage to provide overvoltage protection for the common-source circuit 310-1, the common-gate circuit 310-2, and the cascade circuit 310-3. This ensures that other transistors in the common-source circuit 310-1, the common-gate circuit 310-2, and the cascade circuit 310-3 do not experience overvoltage.

[0074] The voltage, current ratios, and / or size ratios mentioned above are for illustrative purposes only and are not intended to limit this application. It should be understood that in other applications, Figure 1 The digital-to-analog converter 110 and the line driver 120 can also be implemented by other types of circuits. Therefore, this application does not intend to... Figure 2B or Figure 3B The circuit setup shown is limited.

[0075] It should be noted that in the embodiments of this application, "multiple" refers to "two" and "more than two".

[0076] In summary, the wired transmitters in some embodiments of this application have multiple overvoltage protection mechanisms that can protect multiple transistors within the circuit under different operating modes (power-saving mode or transmit mode). This allows the wired transmitter to be implemented using transistors with lower withstand voltages manufactured using newer processes. Furthermore, in power-saving mode, some of the overvoltage mechanisms can also increase the output impedance, thereby mitigating leakage current issues.

[0077] The above provides a detailed description of the wired transmitter with overvoltage protection provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application; at the same time, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A wired transmitter, characterized by Comprising: a digital-to-analog converter generating a plurality of first output signals according to a digital code, wherein a first circuit in the digital-to-analog converter operates in a first voltage domain, a second circuit in the digital-to-analog converter operates in a second voltage domain, and an upper limit of the first voltage domain is lower than an upper limit of the second voltage domain; and a line driver operating in the second voltage domain and generating a plurality of second output signals according to the plurality of first output signals, wherein each of the digital-to-analog converter and the line driver is implemented via a plurality of transistors corresponding to the first voltage domain; the second circuit transmitting a preset voltage to a power supply node in a power saving mode to provide an overvoltage protection for the digital-to-analog converter, and the digital-to-analog converter being level driven via the power supply node in a normal mode. a level of the preset voltage is the same as the upper limit of the first voltage domain.

2. The wired transmitter of claim 1, wherein, the second circuit comprising:

3. The wired transmitter of claim 1, wherein, a first protection circuit selectively transmitting the preset voltage to the power supply node according to a first switching voltage; a buffer generating a power supply voltage according to the plurality of first output signals and a reference voltage, and transmitting the power supply voltage to the power supply node, wherein a level of the power supply node is determined by the preset voltage in the power saving mode and by the power supply voltage in the normal mode; a plurality of current source circuits selectively conducting according to the digital code and being biased via a bias voltage to generate the plurality of first output signals via a plurality of first nodes; a plurality of first resistors coupled between the plurality of first nodes and the power supply node; and a plurality of second resistors coupled between the plurality of first nodes. a level of the first switching voltage is the same as a lower limit of the second voltage domain in the power saving mode and is the same as the upper limit of the second voltage domain in the normal mode.

4. The wired transmitter of claim 3, wherein, each of the plurality of current source circuits comprising:

5. The wired transmitter of claim 3, wherein, a first transistor being biased via the bias voltage to generate a current; a plurality of second transistors selectively conducting via a first bit and a second bit of the digital code to determine a direction of the current to one of the plurality of first nodes, wherein the first bit is opposite to the second bit; and a plurality of third transistors coupled between the plurality of second transistors and the plurality of first resistors and being biased via the preset voltage to provide an overvoltage protection for the first transistor and the plurality of second transistors. an input of the buffer receiving the reference voltage receives the preset voltage in the power saving mode to provide an overvoltage protection for the buffer.

6. The wired transmitter of claim 3, wherein, the buffer comprising:

7. The wired transmitter of claim 3, wherein, a first transistor being biased via a bias voltage to generate a current; a second transistor coupled to a node between the plurality of second resistors; a third transistor coupled to the first transistor and being biased via the reference voltage; a fourth transistor being connected in a diode form and generating a first voltage; a fifth transistor being biased via the first voltage and generating a second voltage; ​ a plurality of sixth transistors respectively coupled between the second and fourth transistors and between the third and fifth transistors and biased by a second switching voltage; a seventh transistor for generating the power voltage according to the second voltage; and an eighth transistor selectively turned on according to a third switching voltage to transmit the preset voltage to the third transistor in the power saving mode to provide an overvoltage protection.

8. The wired transmitter of claim 7, wherein, The second switching voltage has a level same as an upper limit of the first voltage domain in the power saving mode and same as an upper limit of the second voltage domain in the normal mode.

9. The wired transmitter of claim 7, wherein, The third switching voltage has a level same as a lower limit of the first voltage domain in the power saving mode and same as a lower limit of the first voltage domain in the normal mode.

10. The wired transmitter of claim 1, wherein, The line driver comprises: a plurality of amplifier circuits for generating the plurality of second output signals according to the plurality of first output signals; a plurality of first resistors for setting a gain of a first amplifier circuit of the plurality of amplifier circuits; a plurality of second resistors for setting a gain of a second amplifier circuit of the plurality of amplifier circuits; a plurality of first transistors selectively turned off according to a plurality of first switching voltages to increase an output impedance of the first amplifier circuit in the power saving mode or turned on to transmit a reference voltage to the plurality of first resistors in the normal mode; a plurality of second transistors selectively turned off according to the plurality of first switching voltages to increase an output impedance of the second amplifier circuit in the power saving mode or turned on to transmit the reference voltage to the plurality of second resistors in the normal mode; and a third transistor selectively turned on according to a second switching voltage to transmit the preset voltage to the plurality of first transistors and the plurality of second transistors in the power saving mode.

11. The wired transmitter of claim 10, wherein, The plurality of first transistors comprises: a N-type transistor selectively turned on according to a first voltage of the plurality of first switching voltages; and a P-type transistor selectively turned on according to a second voltage of the plurality of first switching voltages.

12. The wired transmitter of claim 11, wherein, The second voltage has a level same as a lower limit of the first voltage domain in the power saving mode and same as an upper limit of the first voltage domain in the normal mode.

13. The wired transmitter of claim 10, wherein, The plurality of output terminals of the first amplifier circuit are coupled to each other via a third resistor, and each of the plurality of first resistors has a resistance value related to a resistance value of the third resistor.

14. The wired transmitter of claim 13, wherein, If a load to be driven by one of the plurality of second output signals outputted via the first amplifier circuit has a first resistance value, the third resistor has a resistance value multiple times of the first resistance value.

15. The wired transmitter of claim 10, wherein, The first amplifier circuit comprises: a common source circuit for generating a plurality of first signals according to one of the first output signals; a common gate circuit for generating a plurality of second signals according to the plurality of first signals; and a cascode circuit for generating one of the plurality of second output signals according to the plurality of second signals, wherein each of the common source circuit, the common gate circuit and the cascode circuit comprises a plurality of transistors, and the plurality of transistors are arranged to provide an overvoltage protection.

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