Printed circuit board

Abstract

The application provides a printed circuit board, comprising: a top layer and a bottom layer, the top layer and / or the bottom layer are provided with a wiring area, at least one sensitive signal line is arranged in the wiring area; a first copper foil and a second copper foil, the first copper foil is arranged on one side of the wiring area, and the second copper foil is arranged on the other side of the wiring area; one or more intermediate layers arranged between the top layer and the bottom layer, the intermediate layer is provided with a third copper foil; a plurality of first vias arranged on the first copper foil, the first via penetrates the first copper foil, and the first copper foil is connected with the third copper foil through the copper of the hole wall of the first via; a plurality of second vias arranged on the second copper foil, the second via penetrates the second copper foil, and the second copper foil is connected with the third copper foil through the copper of the hole wall of the second via. The application reduces the influence of peripheral electronic components on the sensitive signal line in the wiring area, and is beneficial to guarantee the normal use of the printed circuit board.

Description

Technical Field

[0001] This application relates to the field of printed circuit board technology, and more particularly to a printed circuit board. Background Technology

[0002] PCB (Printed Circuit Board) is a crucial component in the electronics industry. It serves as the support for electronic components, the carrier for interconnecting them, and an essential part of communication equipment.

[0003] As communication devices become more functional, printed circuit boards (PCBs) require more electronic components. These include various sensitive signal lines (such as RF signal lines and microphone signal lines) and various interference sources (such as clock lines, digital traces, crystal oscillator pin pads, CPU core power lines, and GPU power lines). Furthermore, with PCB sizes decreasing and density increasing, proximity of interference sources to sensitive signal lines can affect their functionality, and in severe cases, even disrupt normal product operation. For example, RF signal lines (a type of sensitive signal line) require ground copper foil, necessitating numerous vias. However, excessively dense vias can create a slotting effect. When power traces, digital traces, and other interference sources are close to the RF signal line, it can negatively impact parameters such as return loss (S11), voltage standing wave ratio (VSWR), error vector magnitude (EVM), and receiver sensitivity. Summary of the Invention

[0004] In order to overcome the above-mentioned defects in related technologies, the purpose of this application is to provide a printed circuit board that can reduce the impact of electronic components on sensitive signal lines and ensure the normal use of the printed circuit board.

[0005] This application provides a printed circuit board, comprising:

[0006] A top layer and a bottom layer, wherein a routing area is provided in the top layer and / or the bottom layer, and at least one sensitive signal line is provided in the routing area;

[0007] A first copper foil and a second copper foil, wherein the first copper foil is disposed on one side of the trace area and the second copper foil is disposed on the other side of the trace area;

[0008] One or more intermediate layers are disposed between the top layer and the bottom layer, and a third copper foil is disposed on the intermediate layers;

[0009] Multiple first vias are disposed on the first copper foil, the first vias penetrate the first copper foil, and the first copper foil is connected to the third copper foil through the copper of the hole wall of the first via;

[0010] Multiple second vias are disposed on the second copper foil, the second vias penetrate the second copper foil, and the second copper foil is connected to the third copper foil through the copper of the hole wall of the second via.

[0011] As described above, the printed circuit board may optionally include a plurality of first vias and a plurality of first through holes, and a plurality of second vias include a plurality of second laser holes and a plurality of second through holes.

[0012] Optionally, in the printed circuit board described above, the first through-hole and the second through-hole penetrate the printed circuit board, and the bottom layer, each of the intermediate layers and the top layer are electrically connected to the second through-hole through the first through-hole;

[0013] The first laser hole extends from the first copper foil to the third copper foil, and a first copper pillar is provided in the first laser hole. The first copper foil and the third copper foil are electrically connected through the first copper pillar.

[0014] The second laser hole extends from the second copper foil to the third copper foil, and a second copper pillar is provided inside the second laser hole. The second copper foil and the third copper foil are electrically connected through the second copper pillar.

[0015] As described above, in the printed circuit board, optionally, the arrangement direction of the plurality of first vias is the same as the routing direction of the sensitive signal line, and one or more first laser holes are provided between two adjacent first vias;

[0016] The arrangement direction of the second through holes is the same as the routing direction of the sensitive signal line, and one or more second laser holes are provided between two adjacent second through holes.

[0017] As described above, the printed circuit board may optionally have at least one first laser hole between two adjacent first through holes; and / or have at least one second laser hole between two adjacent second through holes.

[0018] As described above, the printed circuit board may optionally have at least two first laser holes between two adjacent first through holes, and the arrangement direction of the at least two first laser holes is perpendicular to the routing direction of the sensitive signal line.

[0019] At least two second laser holes are provided between two adjacent second through holes, and the arrangement direction of the at least two second laser holes is perpendicular to the routing direction of the sensitive signal line.

[0020] In the printed circuit board described above, optionally, two adjacent first laser holes are tangent to each other, or the distance between two adjacent first laser holes is less than or equal to 1.5 mm;

[0021] The two adjacent second laser holes are tangent to each other, or the distance between two adjacent second laser holes is less than or equal to 1.5 mm;

[0022] The adjacent first laser aperture is tangent to the first through hole, or the distance between the adjacent first laser aperture and the first through hole is less than or equal to 1.5 mm;

[0023] The adjacent second laser aperture is tangent to the second through hole, or the distance between the adjacent second laser aperture and the second through hole is less than or equal to 1.5 mm.

[0024] As described above, in the printed circuit board, optionally, the arrangement direction of the plurality of first vias is the same as the routing direction of the sensitive signal line, and one or more first laser holes are provided between two adjacent first vias;

[0025] And / or, the arrangement direction of several second vias is the same as the routing direction of the sensitive signal line, the second vias are disposed close to the edge of the printed circuit board, and the second copper foil is also connected to a ground line, the ground line being in the same routing direction as the sensitive signal line;

[0026] And / or, one or more second laser holes are provided between two adjacent second through holes, the arrangement direction of the plurality of second laser holes is the same as the routing direction of the sensitive signal line, the second through holes are provided near the edge of the printed circuit board, and the second copper foil is also connected to a ground line, the ground line is in the same routing direction as the sensitive signal line.

[0027] As described above, the printed circuit board may optionally have multiple sensitive signal lines arranged in the routing area, with adjacent sensitive signal lines spaced apart, the sensitive signal line closer to the first copper foil spaced apart from the first copper foil, and the sensitive signal line closer to the second copper foil spaced apart from the second copper foil.

[0028] The printed circuit board described above may optionally include at least one first line and / or first trace;

[0029] The first line and / or the first trace is located on the side of the first copper foil away from the trace area; and / or, the first line and / or the first trace is located on the side of the second copper foil away from the trace area;

[0030] The first line includes one or more of power pads, signal pads, signal vias, and power vias; the first trace includes one or more of power traces and signal traces.

[0031] As described above, the printed circuit board may optionally have the trace area disposed on the top layer, and at least one of the bottom layer and each of the intermediate layers further provided with a second trace and / or a second line, wherein the second trace and / or the second line is located within the projection range of the first copper foil, the trace area and the second copper foil.

[0032] And / or, the trace area is disposed on the bottom layer, and at least one of the top layer and each of the intermediate layers is further provided with a second trace and / or a second line, wherein the second trace / or the second line is located within the projection range of the first copper foil, the trace area and the second copper foil.

[0033] Optionally, in the printed circuit board described above, the trace area is disposed on the top layer, at least one of the intermediate layers is further provided with a second trace and a second line, and the bottom layer is provided with electronic components. The second trace, the second line, and the electronic components are located within the projection range of the first copper foil, the trace area, and the second copper foil.

[0034] This application provides a printed circuit board, comprising: a top layer and a bottom layer, wherein the top layer and / or the bottom layer are provided with a trace area, and at least one sensitive signal line is provided in the trace area; a first copper foil and a second copper foil, wherein the first copper foil is provided on one side of the trace area and the second copper foil is provided on the other side of the trace area; one or more intermediate layers are provided between the top layer and the bottom layer, wherein a third copper foil is provided on the intermediate layers; a plurality of first vias are provided on the first copper foil, wherein the first vias penetrate the first copper foil, and the first copper foil is connected to the third copper foil through the copper of the via wall; and a plurality of second vias are provided on the second copper foil, wherein the second vias penetrate the second copper foil, and the second copper foil is connected to the third copper foil through the copper of the via wall. This application provides multiple first vias and multiple second vias on the first and second copper foils on both sides of the trace area. These vias are connected to the third copper foil of the intermediate layer. Noise generated by peripheral electronic components on the printed circuit board is coupled to the third copper foil of the intermediate layer, thereby increasing the isolation between the sensitive signal lines and the peripheral electronic components and reducing the impact of the peripheral electronic components on the sensitive signal lines in the trace area. This is beneficial to ensuring the normal use of the printed circuit board. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A top view of a printed circuit board provided in an embodiment of this application;

[0037] Figure 2 A cross-sectional view of a printed circuit board provided in an embodiment of this application;

[0038] Figure 3 A top view of the top layer of a printed circuit board provided in an embodiment of this application;

[0039] Figure 4 for Figure 3 A cross-sectional view of a printed circuit board in one embodiment;

[0040] Figure 5 for Figure 3 A cross-sectional view of the printed circuit board in another embodiment;

[0041] Figure 6 for Figure 3 A cross-sectional view of the printed circuit board in another embodiment;

[0042] Figure 7 for Figure 3 A cross-sectional view of the printed circuit board in another embodiment;

[0043] Figure 8 for Figure 3 A cross-sectional view of the printed circuit board in another embodiment;

[0044] Figure 9 A top view of the top layer of a printed circuit board provided in another embodiment of this application;

[0045] Figure 10 A top view of the top layer of a printed circuit board provided in another embodiment of this application;

[0046] Figure 11 A top view of the top layer of a printed circuit board provided in another embodiment of this application;

[0047] Figure 12 A top view of the top layer of a printed circuit board provided in another embodiment of this application;

[0048] Figure 13A top view of the top layer of a printed circuit board provided in another embodiment of this application;

[0049] Figure 14 A partial cross-sectional view between the top and second layers of a printed circuit board provided in an embodiment of this application;

[0050] Figure 15 A partial cross-sectional view between the top and second layers of a printed circuit board provided in another embodiment of this application;

[0051] Figure 16 A partial cross-sectional view between the top and second layers of a printed circuit board provided in another embodiment of this application;

[0052] Figure 17 A partial cross-sectional view between the top and second layers of a printed circuit board provided for another embodiment of this application;

[0053] Figure 18 A top view of the top layer of a printed circuit board provided in another embodiment of this application. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.

[0055] Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0056] Figure 1 A top view of a printed circuit board provided in an embodiment of this application; Figure 2 A cross-sectional view of a printed circuit board provided in an embodiment of this application.

[0057] Please refer to Figures 1-2 This embodiment provides a printed circuit board, including:

[0058] The top layer 1000 and the bottom layer 2000 are provided. The top layer 1000 and / or the bottom layer 2000 are provided with a wiring area 1100. At least one sensitive signal line 1110 is provided in the wiring area 1100.

[0059] A first copper foil 1200 and a second copper foil 1300 are provided, with the first copper foil 1200 disposed on one side of the trace area 1100 and the second copper foil 1300 disposed on the other side of the trace area 1100.

[0060] One or more intermediate layers 3000 are disposed between the top layer 1000 and the bottom layer 2000, and a third copper foil 3100 is disposed on the intermediate layer 3000.

[0061] Multiple first vias are provided on the first copper foil 1200. The first vias penetrate the first copper foil 1200, and the first copper foil 1200 is connected to the third copper foil 3100 through the copper of the hole wall of the first via.

[0062] Multiple second vias are provided on the second copper foil 1300. The second vias penetrate the second copper foil 1300, and the second copper foil 1300 is connected to the third copper foil 3100 through the copper of the hole wall of the second via.

[0063] In this embodiment, multiple first vias and multiple second vias are respectively provided on the first copper foil 1200 and the second copper foil 1300 on both sides of the trace area 1100. The first vias and the second vias are connected to the third copper foil 3100 of the intermediate layer 3000. The noise generated by the peripheral electronic components on the printed circuit board will be coupled to the third copper foil 3100 of the intermediate layer 3000, thereby increasing the isolation between the sensitive signal line 1110 and the peripheral electronic components, reducing the impact of the peripheral electronic components on the sensitive signal line 1110 in the trace area 1100, and helping to ensure the normal use of the printed circuit board.

[0064] In this embodiment, the plurality of first vias include several first laser holes 1210 and several first through holes 1220, and the plurality of second vias include several second laser holes 1310 and several second through holes 1320.

[0065] Specifically, the first through-hole 1220 and the second through-hole 1320 penetrate the printed circuit board. The bottom layer 2000, each intermediate layer 3000, and the top layer 1000 are electrically connected through the first through-hole 1220 and the second through-hole 1320. Specifically, the trace area 1100, the first copper foil 1200, and the second copper foil 1300 are all located on the top layer 1000. A third copper foil 3100 is provided on the intermediate layer 3000, and a fourth copper foil is provided on the bottom layer 2000. The first through-hole 1220 is formed in the first copper foil 1200, and the first copper foil 1200, the third copper foil 3100, and the fourth copper foil are electrically connected through the copper on the hole wall of the first through-hole 1220. The second through-hole 1320 is formed in the second copper foil 1300, and the second copper foil 1300, the third copper foil 3100, and the fourth copper foil are electrically connected through the copper on the hole wall of the second through-hole 1320.

[0066] The first laser hole 1210 extends from the first copper foil 1200 to the third copper foil 3100. A first copper pillar is provided inside the first laser hole 1210, and the first copper foil 1200 and the third copper foil 3100 are electrically connected through the first copper pillar.

[0067] The second laser hole 1310 extends from the second copper foil 1300 to the third copper foil 3100. A second copper pillar is provided inside the second laser hole 1310, and the second copper foil 1300 and the third copper foil 3100 are electrically connected through the second copper pillar.

[0068] In one possible implementation, the arrangement direction of the plurality of first vias 1220 in this embodiment is the same as the routing direction of the sensitive signal line 1110, and one or more first laser holes 1210 are provided between two adjacent first vias 1220. The arrangement direction of the plurality of second vias 1320 is the same as the routing direction of the sensitive signal line 1110, and one or more second laser holes 1310 are provided between two adjacent second vias 1320.

[0069] With the above setup, the gap between the two through holes can be filled by laser holes. In this way, when the noise generated by the peripheral electronic components on the printed circuit board passes through the two through holes, it will be guided by the laser holes to the third copper foil, thereby reducing the impact of noise on the sensitive signal line 1110.

[0070] Furthermore, at least one first laser hole 1210 is provided between two adjacent first through holes 1220; and / or, at least one second laser hole 1310 is provided between two adjacent second through holes 1320.

[0071] Furthermore, at least two first laser holes 1210 are provided between two adjacent first through holes 1220, and the arrangement direction of the at least two first laser holes 1210 is perpendicular to the routing direction of the sensitive signal line 1110. At least two second laser holes 1310 are provided between two adjacent second through holes 1320, and the arrangement direction of the at least two second laser holes 1310 is perpendicular to the routing direction of the sensitive signal line 1110.

[0072] Optionally, in this embodiment, two adjacent first laser holes 1210 are tangent, or the distance between two adjacent first laser holes 1210 is less than or equal to 1.5 mm.

[0073] The two adjacent second laser holes 1310 are tangent, or the distance between the two adjacent second laser holes 1310 is less than or equal to 1.5 mm.

[0074] The adjacent first laser aperture 1210 is tangent to the first through hole 1220, or the distance between the adjacent first laser aperture 1210 and the first through hole 1220 is less than or equal to 1.5 mm.

[0075] The adjacent second laser aperture 1310 is tangent to the second through aperture 1320, or the distance between the adjacent second laser aperture 1310 and the second through aperture 1320 is less than or equal to 1.5 mm.

[0076] In one possible implementation, the arrangement direction of the plurality of first through holes 1220 in this embodiment is the same as the routing direction of the sensitive signal line 1110, and one or more first laser holes 1210 are provided between two adjacent first through holes 1220.

[0077] And / or, the arrangement direction of several second vias 1320 is the same as the routing direction of the sensitive signal line 1210. The second vias 1320 are located close to the edge of the printed circuit board. The second copper foil 1300 is also connected to a ground wire, and the ground wire is in the same routing direction as the sensitive signal line 1210.

[0078] And / or, one or more second laser holes 1310 are provided between two adjacent second through holes 1320, the arrangement direction of the multiple second laser holes 1310 is the same as the routing direction of the sensitive signal line 1210, the second through holes 1320 are provided close to the edge of the printed circuit board, and the second copper foil 1300 is also connected to a ground line, the ground line is in the same routing direction as the sensitive signal line 1210.

[0079] In one possible implementation, a plurality of sensitive signal lines 1110 are provided in the wiring area 1100 of this embodiment. Two adjacent sensitive signal lines 1110 are spaced apart. The sensitive signal line 1110 on the side closer to the first copper foil 1200 is spaced apart from the first copper foil 1200, and the sensitive signal line 1110 on the side closer to the second copper foil 1300 is spaced apart from the second copper foil 1300.

[0080] In one possible implementation, the printed circuit board of this embodiment further includes at least one first line 1410 and / or a first trace 1420;

[0081] The first line 1410 and / or the first trace 1420 are located on the side of the first copper foil 1200 away from the trace area 1100; and / or, the first line 1410 and / or the first trace 1420 are located on the side of the second copper foil 1300 away from the trace area 1100.

[0082] The first line 1410 includes one or more of power pads, signal pads, signal vias, and power vias; the first trace 1420 includes one or more of power traces and signal traces.

[0083] In one possible implementation, the routing area 1100 of this embodiment is disposed on the top layer 1000, and at least one of the bottom layer 2000 and each intermediate layer 3000 is further provided with a second routing and a second line, the second routing and the second line being located within the projection range of the first copper foil 1200, the routing area 1100 and the second copper foil 1300.

[0084] In one possible implementation, the trace area 1100 of this embodiment is disposed on the top layer 1000, at least one of the intermediate layers 3000 is further provided with a second trace and a second line, and the bottom layer 2000 is provided with electronic components. The second trace, the second line and the electronic components are located within the projection range of the first copper foil 1200, the trace area 1100 and the second copper foil 1300.

[0085] The solution of this application will be described in detail below with reference to specific embodiments.

[0086] Figure 3 A top view of the top layer of a printed circuit board provided in an embodiment of this application; Figure 4 for Figure 3 A cross-sectional view of a printed circuit board according to one embodiment. Wherein, Figure 4 It is along Figure 3 The figure shows cross-sectional views of laser apertures 206, 205, 201, 202, 211, and 200. The top layer is shown as the TOP layer; the bottom layer is shown as the BOTTOM layer; and there are four middle layers, shown as L02, L03, L04, and L05. In the figure, the sensitive signal line 40 can be a radio frequency (RF) trace (e.g., Wi-Fi RF trace, LTE RF trace, GPS RF trace, etc.), a fetal heart rate monitoring signal trace for a medical fetal heart rate monitor (signal swing is only at the μV level), a microphone sampling signal trace, or a sensitive MIPI signal trace or differential signal trace. For example, the swing of a 25GB / s differential signal trace is only 30mV, making it extremely susceptible to interference from surrounding power traces or vias, clock signal traces or vias, etc. Both laser-drilled holes and through-holes in the diagram consist of two parts: a pad (hole plate) and a drilled hole. Through-holes are created by first drilling a hole in the PCB board, then electroplating the hole walls. The electroplated portion forms the hole plate. Through-hole 202 contains a drilled hole 203, and through-hole 205 contains a drilled hole 204. Laser-drilled holes are created using laser processing, and the drilled holes are then electroplated to fill the gaps. A laser-drilled hole can be considered a solid copper pillar.

[0087] Please refer to Figure 3A sensitive signal line 40 (e.g., RF trace, microphone sampling signal trace, etc.) is set in a local area of ​​the TOP layer of the printed circuit board 310. A ground copper foil 207 (i.e., the first copper foil) of the TOP layer is set to the left of the sensitive signal line 40. A gap 51 (i.e., a copper-free area) is set between the ground copper foil 207 and the sensitive signal line 40. Laser holes 30, 206, 205, 201, 32, 202, 211, 31, 200, and 33 are set from top to bottom on the ground copper foil 207. Among them, laser holes 30 and 206 are arranged side by side in the horizontal direction, and the edge of the plate of laser hole 30 is tangent to the edge of the plate of laser hole 206; laser holes 32 and 201 are arranged side by side in the horizontal direction, and the edge of the plate of laser hole 32 is tangent to the edge of the plate of laser hole 201; laser holes 31 and 211 are arranged side by side in the horizontal direction, and the edge of the plate of laser hole 31 is tangent to the edge of the plate of laser hole 211; laser holes 33 and 200 are arranged side by side in the horizontal direction, and the edge of the plate of laser hole 33 is tangent to the edge of the plate of laser hole 200.

[0088] A ground copper foil 52 (i.e., the second copper foil) of the TOP layer is set to the right of the sensitive signal line 40, and a gap 50 (i.e., a copper-free area) is set between the ground copper foil 52 and the sensitive signal line 40. Laser holes 41, 34, 35, 36, 58, 37, 42, 38, 43, and 39 are set on the ground copper foil 52 from top to bottom. Among them, laser holes 41 and 34 are arranged side by side in the horizontal direction, and the edge of the plate of laser hole 41 is tangent to the edge of the plate of laser hole 34; laser holes 36 and 58 are arranged side by side in the horizontal direction, and the edge of the plate of laser hole 36 is tangent to the edge of the plate of laser hole 58; laser holes 42 and 38 are arranged side by side in the horizontal direction, and the edge of the plate of laser hole 42 is tangent to the edge of the plate of laser hole 38; laser holes 39 and 43 are arranged side by side in the horizontal direction, and the distance between the edge of the plate of laser hole 39 and the edge of the plate of laser hole 43 is L23, 0≦L23<1.5mm, preferably L23=0, that is, the edge of the plate of laser hole 39 is tangent to the edge of the plate of laser hole 43, which saves space.

[0089] Continue reading Figure 3 and Figure 4The ground copper foil 207 of the TOP layer connects laser holes 211, 200, 202, 201, 205, and 206 in the TOP layer. Through holes 202 connect the ground copper foil 207 of the TOP layer, the ground copper foil 208 of the L02 layer, the ground copper foil 212 of the L03 layer, the ground copper foil 213 of the L04 layer, the ground copper foil 214 of the L05 layer, and the ground copper foil 210 of the BOTTOM layer into a low-impedance whole. In this embodiment, the third copper foil includes ground copper foil 208, ground copper foil 212, ground copper foil 213, and ground copper foil 214. Generally, the ground copper foil 208 of layer L02 is set as a complete ground plane, meaning that only ground copper foil 208 is set on layer L02. Noise in the ground copper foil 207 of layer TOP, layer 212 of layer L03, layer 213 of layer L04, layer 214 of layer L05, and layer 210 of layer BOTTOM at the locations of vias 202 and 202 will be absorbed and attenuated by the ground copper foil 208 of layer L02. This significantly reduces noise on the ground copper foil 207 of layer TOP, layer 212 of layer L03, layer 213 of layer L04, layer 214 of layer L05, and layer 210 of layer BOTTOM at the locations of vias 202 and 202, greatly reducing the EMI radiation and radio frequency spurious emissions of the entire product. Laser holes 211, 200, 201, and 206 are moved from layer TOP to layer L02, while... Figure 4 In the illustrated scheme, laser holes 211, 200, 201, and 206 tightly connect the ground copper foil 207 of the TOP layer and the ground copper foil 208 of the L02 layer in the Z direction of the printed circuit board 310 stack-up structure. Combined with vias 202 and 205, a low-impedance connection is achieved between the ground copper foil 207 of the TOP layer and the ground copper foil 208 of the L02 layer. This prevents sensitive signal lines 40 (e.g., RF traces) from venting to surrounding signal traces and vias (e.g., clock traces). Figure 4 (Unmarked), power traces and vias ( Figure 4 (Not marked), TOP layer pads ( Figure 4 (Not marked) Leakage is prevented, and the holes also prevent signal traces and vias (such as clock traces) around laser holes 211, 200, 202, 201, 205, and 206. Figure 4 (Unmarked), power traces and vias ( Figure 4 (Not marked), TOP layer pads ( Figure 4 (Unmarked) The pulsed electric field (radiation) leakage causes interference to sensitive signal lines 40 (e.g., RF traces). Simultaneously, due to the low-impedance connection between the ground copper foil 207 of the TOP layer and the ground copper foil 208 of the L02 layer, the signal traces and vias (e.g., clock traces) surrounding laser holes 211, 200, 202, 201, 205, and 206 are also affected. Figure 4 (Unmarked), power traces and vias ( Figure 4 (Not marked), TOP layer pads ( Figure 4 (Unmarked) Ground noise generated on its trace (absorbed by the ground copper foil 208 of the L02 layer) is negligible for sensitive signal lines 40 (e.g., RF traces).

[0090] In this embodiment, the edge spacing between laser aperture 211 and laser aperture 200 is L2. This is to avoid interference with signal traces and vias (e.g., clock traces) around laser aperture 211 and laser aperture 200. Figure 4 (Unmarked), power traces and vias ( Figure 4 (Not marked), TOP layer pads ( Figure 4 (Unmarked) The pulsed electric field radiation generates leakage interference to the sensitive signal line 40. The edge spacing between laser aperture 211 and laser aperture 200 is L2≦1.5mm, preferably L2=0, that is, the edge of the aperture disk of laser aperture 211 is tangent to the edge of the aperture disk of laser aperture 200. The edge of the aperture disk of laser aperture 211 and the edge of the aperture disk of laser aperture 200 can be tangent, but they cannot overlap.

[0091] The edge of the laser hole 200 is tangent to the edge of the through hole 202. The edge of the laser hole 201 is tangent to the edges of the through holes 202 and 205, respectively.

[0092] The edge spacing between laser aperture 206 and through-hole 205 is L1. This is to avoid interference with signal traces and vias (e.g., clock traces) around laser aperture 206 and through-hole 205. Figure 4 (Unmarked), power traces and vias ( Figure 4 (Not marked), TOP layer pads ( Figure 4 (Unmarked) The pulsed electric field radiation causes leakage interference to the sensitive signal line 40. The edge spacing between laser hole 206 and through hole 205 is L1≦1.5mm, preferably the edge spacing between laser hole 211 and laser hole 200 is L2=0, that is, the edge of the aperture plate of laser hole 211 is tangent to the edge of the aperture plate of laser hole 200. The edge of the aperture plate of laser hole 211 and the edge of the aperture plate of laser hole 200 can be tangent, but they cannot overlap.

[0093] In this embodiment, laser holes 211, 200, 201, and 206 are processed from the TOP layer to the L02 layer of the printed circuit board 310 using a laser processing method. Due to limitations in existing laser hole processing technology, the thickness H1 of the insulating medium from the TOP layer to the L02 layer is less than or equal to 3 mil (0.075 mm), and the thickness H5 of the insulating medium from the BOTTOM layer to the L05 layer is less than or equal to 3 mil (0.075 mm). The thicknesses H1 and H5 of the insulating medium from the TOP layer to the L02 layer and from the BOTTOM layer to the L05 layer must be symmetrically distributed.

[0094] Continue reading Figure 4 , Figure 3 Through-holes 202 and 205 were added around the sensitive signal line 40. Therefore, through-holes 202 and 205 can make low-impedance connections between the ground copper foil 207 of the TOP layer, the ground copper foil 208 of the L02 layer, the ground copper foil 212 of the L03 layer, the ground copper foil 213 of the L04 layer, the ground copper foil 214 of the L05 layer, and the ground copper foil 210 of the BOTTOM layer, thereby reducing the voltage difference between the ground copper foils of each layer and improving the performance of board-level EMI.

[0095] Figure 5 for Figure 3 A cross-sectional view of the printed circuit board in another embodiment. Figure 5 The cutting direction and Figure 4 same.

[0096] and Figure 4 Comparison of options Figure 5 The difference between the two plans lies in the fact that... Figure 4 The laser aperture 206 in the TOP-L02 layer is replaced with the laser aperture 220 in the TOP-L02-L03 layer. This means the laser aperture 220 extends from the TOP layer through to the L02 and L03 layers, creating a low-impedance connection between the TOP layer ground copper foil 207 and the L02 and L03 layer ground copper foils 208 and 212. The thickness H2 of the insulating medium from the L02 layer to the L03 layer is less than or equal to 3 mil (0.075 mm), the thickness H4 of the insulating medium from the L05 layer to the L04 layer is less than or equal to 3 mil (0.075 mm), and the thicknesses H1 and H5 of the insulating medium from the L02 layer to the L03 layer and from the L05 layer to the L04 layer should be symmetrically distributed.

[0097] In addition to the differences mentioned above, Figure 5 Other parts of the plan and Figure 4 They are all the same, so I will not repeat the description.

[0098] Figure 6 for Figure 3 A cross-sectional view of the printed circuit board in another embodiment. Figure 6 The cutting direction and Figure 4same.

[0099] and Figure 5 Comparison of options Figure 6 The difference between the two plans lies in the fact that... Figure 5 The laser aperture 220 in the TOP-L02-L03 layer is changed to the laser aperture 221 in the TOP-L02-L03-L04 layer. That is, the laser aperture 221 runs from the TOP layer through the L02, L03, and L04 layers, connecting the ground copper foil 207 of the TOP layer with the ground copper foil 208 of the L02 layer, the ground copper foil 212 of the L03 layer, and the ground copper foil 213 of the L04 layer with low impedance. The thickness H2 of the insulating medium from the L03 layer to the L04 layer is less than or equal to 3 mil (0.075 mm).

[0100] In addition to the differences mentioned above, Figure 6 Other parts of the plan and Figure 5 They are all the same, so I will not repeat the description.

[0101] Figure 7 for Figure 3 A cross-sectional view of the printed circuit board in another embodiment. Figure 7 The cutting direction and Figure 4 same.

[0102] and Figure 6 Comparison of options Figure 7 The difference between the two plans lies in the fact that... Figure 6 The laser aperture 221 in the TOP-L02-L03-L04 layer is changed to the laser aperture 222 in the TOP-L02-L03-L04-L05 layer. That is, the laser aperture 222 runs from the TOP layer through the L02, L03, L04 and L05 layers, and the ground copper foil 207 of the TOP layer is connected to the ground copper foil 208 of the L02 layer, the ground copper foil 212 of the L03 layer, the ground copper foil 213 of the L04 layer and the ground copper foil 214 of the L05 layer with low impedance.

[0103] In addition to the differences mentioned above, Figure 7 Other parts of the plan and Figure 6 They are all the same, so I will not repeat the description.

[0104] Figure 8 for Figure 3 A cross-sectional view of the printed circuit board in another embodiment.

[0105] and Figure 4 Comparison of options Figure 8The difference in the scheme lies in the fact that the laser holes 211 in the TOP layer are arranged sequentially in the Z direction as laser holes 270, 271, 272, 273, 274, 275, 276, 277, 278, 295, 268, 262, and 267. Among them, laser holes 206, 201, 200, 211, 270, 271, 272, 273, 274, 275, 276, 277, 278, 268, and 262 achieve a low-impedance connection between the ground copper foil 207 of the TOP layer and the ground copper foil 208 of the L02 layer. The projection of the sensitive signal line 40 on the TOP layer falls entirely within the ground copper foil 208 on the L02 layer. The ground copper foil 208 on the L02 layer completely covers the projection of the sensitive signal line 40 on the L02 layer. In other words, the sensitive signal line 40 on the TOP layer has a complete reference plane, i.e., the ground copper foil 208, on the adjacent L02 layer. Vias 202 and 205 provide low-impedance connections for the ground copper foils 207 (TOP layer), 208 (L02 layer), 212 (L03 layer), 213 (L04 layer), 214 (L05 layer), and 210 (BOTTOM layer). Vias 295 and 267 provide low-impedance connections for the ground copper foils 207 (TOP layer), 208 (L02 layer), 252 (L03 layer), 253 (L04 layer), 254 (L05 layer), and 255 (BOTTOM layer).

[0106] A BGA (Ballistic Array) is installed between vias 202 and 256 on the BOTTOM layer of the printed circuit board 310. The GridArray (BGA) device 297 has pads 90, 91, 92, 93, 94, 95, and 96 on its main body pins. A laser via 80 on pad 90 connects to a signal trace 70 on the L05-BOTTOM layer. Pads 91, 92, 93, 94, 95, and 96 also connect to the L05-BOTTOM layer. Pads 90, 93, 94, and 95 each have a laser via 85 connected to a signal trace 75 on the L05-BOTTOM layer.

[0107] Signal traces 285, 286, 287, and 288 are set on layer L04; signal traces 280, 281, 282, and 283 are set on layer L03. That is, between vias 202 and 256, various signal traces are set in the areas of layers L03, L04, and L05 where the sensitive signal line 40 of the TOP layer is projected. BGA devices (only BGA devices are used as an example, and device types are not limited) are set in the area where the sensitive signal line 40 of the TOP layer is projected onto the BOTTOM layer. This results in the inability to set vias connecting to the ground copper foil 207 of the TOP layer and the ground copper foil 208 of the L02 layer in the area between vias 202 and 256. Laser holes 200, 211, 270, 271, 272, 273, 274, 275, 276, 277, and 278 are provided on the TOP layer ground copper foil 207 and L02 layer ground copper foil 208 between via 202 and via 256. Power and clock traces are placed around the sensitive signal line 40 on the TOP layer without interfering with it, meeting design requirements. One to 20 rows of laser holes can be provided between via 202 and via 256.

[0108] In addition to the differences mentioned above, Figure 8 Other parts of the plan and Figure 4 They are all the same, so I will not describe them again.

[0109] Figure 9 A top view of the top layer of a printed circuit board provided in another embodiment of this application.

[0110] and Figure 3 Comparison of options Figure 9 The difference in the scheme lies in the fact that the edge of the laser aperture 43 and the edge of the laser aperture 39 are not tangent, and the distance between the edge of the laser aperture 43 and the edge of the laser aperture 39 is L23, where 0 <L23≦1.5mm。

[0111] Sensitive signal lines 53 and 54 are placed between ground copper foil 52 and ground copper foil 207. Sensitive signal lines 53 and 54 form a sensitive differential trace (for example, the swing of a 25GB / s differential trace signal is only 30mV, making it highly susceptible to electric field interference from surrounding signal and power traces on the same layer). A gap 57 (no copper foil area) is placed between sensitive signal lines 53 and 54; a gap 55 (no copper foil area) is placed between sensitive signal line 53 and ground copper foil 207; and a gap 56 (no copper foil area) is placed between sensitive signal line 54 and ground copper foil 52. The line widths of sensitive signal lines 53 and 54, gaps 57, 55, and 56, and the thickness of the insulation layer from the TOP layer to the L02 layer must meet the impedance control requirements of the differential trace (e.g., 100 ohms).

[0112] In addition to the differences mentioned above, Figure 9 Other parts of the plan and Figure 3 They are all the same, so I will not describe them again.

[0113] Figure 10 A top view of the top layer of a printed circuit board provided in another embodiment of this application.

[0114] and Figure 3 Comparison of options Figure 10 The difference in the design lies in the placement of a signal trace 60 (e.g., a clock trace) to the right of the TOP layer ground copper foil 52. This signal trace 60 connects to a signal via 803 (signal vias include both through-hole and laser-drilled vias; this example only uses through-hole 803 and does not limit the type of signal via). The signal via 803 is located to the right of the through-hole 37. Below the signal via 803 and to the right of the laser-drilled via 39, a power via 804 (power vias include both through-hole and laser-drilled vias; this example only uses through-hole 804 and does not limit the type of power via) is placed. A gap 63 (i.e., a copper-free area) is provided between the ground copper foil 52 and the signal trace 60. The width of the gap 63 is L31, with L31 ≥ 2 mil (preferably L31 ≥ 3 mil), primarily considering the etching capabilities of the PCB manufacturer. The gap (i.e., the copper-free area) between the power via 804 and the TOP layer ground copper foil 52 is L34, where L34 ≥ 2mil (preferably L34 ≥ 3mil). The gap between the signal via 803 and the TOP layer ground copper foil 52 is L32, where L32 ≥ 2mil (preferably L32 ≥ 3mil).

[0115] A power trace 61 is positioned to the right of the TOP layer ground copper foil 207. A gap 62 (i.e., a copper-free area) is provided between the ground copper foil 207 and the power trace 61. The width of the gap 62 is L30, L30 ≥ 2mil (preferably L30 ≥ 3mil), mainly considering the etching capabilities of the PCB manufacturer. The power trace 61 is connected to the power pad 811, and the power pin of component 801 ( Figure 10 (Not shown) Soldered onto power pad 811, the gap between power pad 811 and the TOP layer ground copper foil 207 is L33, L33 ≥ 2mil (preferably L33 ≥ 3mil). The signal pins of component 801 ( Figure 10 (Not indicated) Soldered on signal pad 802, the gap between signal pad 802 and TOP layer ground copper foil 207 is L35, L35≧2mil (preferably L35≧3mil).

[0116] A sensitive signal line 40 (e.g., RF trace, differential trace, etc.) is positioned to the left of the ground copper foil 52 in the TOP layer. A gap 51 with a width of L32 is provided between the ground copper foil 52 and the sensitive signal line 40. A gap 50 with a width of L33 is also provided between the ground copper foil 52 and the sensitive signal line 40. Preferably, L32 = L33. When the sensitive signal line 40 has impedance control requirements, the line width of the sensitive signal line 40, the gaps 51 and 50, and the thickness of the insulation layer from the TOP layer to the L02 layer must meet the impedance control requirements of the sensitive signal line 40 (e.g., 50 ohms for RF traces). If the sensitive signal line 40 transmits a low-frequency microphone signal, impedance control is not required.

[0117] Figure 10 The first trace in the scheme includes the power pad 811 and signal pad 802 of component 801 to the left of ground copper foil 200, and the first trace includes power trace 61.

[0118] Figure 11 A top view of the top layer of a printed circuit board provided in another embodiment of this application.

[0119] and Figure 10 Compare, Figure 11 Will Figure 10The signal traces 60 (e.g., clock traces), signal vias 803 (signal vias include signal through holes and signal laser holes; this example only uses signal through hole 803 and does not limit the type of signal via), and power vias 804 (power vias include power through holes and power laser holes; this example only uses power through hole 804 and does not limit the type of power via) are removed and replaced by the edge 333 of the PCB board 310. Specifically, ground copper foil 207 and ground copper foil 52 are placed in the narrow space between the power traces 61, the power pads 811 and signal pads 802 of component 801, and the edge 333 of the PCB board 310. A sensitive [something] is placed between the ground copper foil 207 and the ground copper foil 52. The sensitive signal line 40 has a gap 51 (i.e., a copper-free area) between it and the ground copper foil 207, a gap 50 (i.e., a copper-free area) between it and the ground copper foil 52, and a gap 68 (i.e., a copper-free area) between the ground copper foil 52 and the edge 333 of the PCB board 310. The width of the gap 68 is L50 ≥ 0.15 mm (preferably L50 ≥ 0.2 mm). The gap 68 is used to maintain a safe distance between the ground copper foil 52 and the edge of the PCB board 310, so as to prevent the PCB manufacturer from scratching the ground copper foil 52 with the milling cutter when processing the edge 333 of the PCB board 310, which would cause the ground copper foil 52 to be exposed and oxidized. Figure 11 The case where the sensitive signal 40 trace area is close to the right edge 333 of the PCB board 310, while the right edge 331 of the PCB board 310 does not have the first line and the first trace, that is, the first line and the first trace are distributed on the left side of the sensitive signal 40 trace area.

[0120] Figure 11 The first trace in the scheme includes the power pad 811 and signal pad 802 of component 801 to the left of ground copper foil 200, and signal vias 803 (signal vias include signal through holes and signal laser holes; signal through hole 803 is used as an example only, and the type of signal via is not limited) and power vias 804 (power vias include power through holes and power laser holes; power through hole 804 is used as an example only, and the type of power via is not limited) to the right of ground copper foil 52. The first trace includes signal traces 60 (e.g., clock traces) and power traces 61.

[0121] In addition to the differences mentioned above, Figure 11 Other parts of the plan and Figure 10 They are all the same, so I will not repeat the description.

[0122] Figure 12 A top view of the top layer of a printed circuit board provided in another embodiment of this application.

[0123] and Figure 11 Compare, Figure 12 Will Figure 11Laser holes 34, 35, 36, 37, 38, 39 between laser hole 41 and board edge 333 are removed. Instead, multiple single-row laser holes (41, 366, 58, 388, 42, and 43) are installed in the ground copper foil 52 between the sensitive signal line 40 and board edge 333. These laser holes are electrically connected to the ground copper foil 52. The arrangement of laser holes 41, 366, 58, 388, 42, and 43 is parallel to the sensitive signal line 40 in the vertical direction. Due to space constraints on the PCB board 310, vias cannot be added between the sensitive signal line 40 and the board edge 333. A gap 68 (i.e., a copper-free area) is provided between the ground copper foil 52 and the board edge 333 of the PCB board 310. The width of the gap 68 is L50 ≥ 0.15 mm (preferably L50 ≥ 0.2 mm). The gap 68 is used to maintain a safe distance between the ground copper foil 52 and the board edge of the PCB board 310, preventing the PCB manufacturer from scratching the ground copper foil 52 with a milling cutter during the processing of the board edge 333 of the PCB board 310, which could lead to oxidation of the exposed ground copper foil 52. A gap 50 with a width of L33 is provided between the sensitive signal line 40 and the ground copper foil 52. Apart from the above differences, Figure 12 Other parts of the plan and Figure 11 They are all the same, so I will not repeat the description.

[0124] Figure 12 The application scenarios shown are mainly found in PCB boards with small size and very high density, such as vehicle trackers (belonging to in-vehicle wireless devices) and dashcams (belonging to in-vehicle wireless devices). This means that the sensitive signal line 40 (e.g., RF trace) is placed near the board edge 333, while various lines and components (e.g., Figure 13 The circuit includes power traces 61, component 801, power pads 811 and signal pads 802 of component 801, and a ground copper foil 207 is set between various lines and components and sensitive signal lines 40. Laser holes 206, 30, 205, 201, 32, 202, 211, 31, 200, and 207 are set in the ground copper foil 207.

[0125] Figure 13 A top view of the top layer of a printed circuit board provided in another embodiment of this application. Figure 14 A partial cross-sectional view between the top and second layers of a printed circuit board provided in an embodiment of this application;

[0126] Figure 15A partial cross-sectional view between the top and second layers of a printed circuit board provided in another embodiment of this application; Figure 16 A partial cross-sectional view between the top and second layers of a printed circuit board provided for another embodiment of this application; Figure 17 A partial cross-sectional view between the top and second layers of a printed circuit board provided in another embodiment of this application.

[0127] and Figure 12 Compare, Figure 13 Will Figure 12 Remove laser hole 41 and laser hole 366 from the image. Figure 12 The edge 333 in the middle is a regular straight line, while Figure 13 The vertical direction from bottom to top: the positions of laser holes 43, 42, 388, and 58, and the shape of the plate edge 334 are all consistent with... Figure 12 Similarly, but the board edge 334 above the laser hole 58 is recessed to the left, thus cutting a notch 330, while various circuits and components (e.g., ...) are arranged to the left of the sensitive signal line 40. Figure 12 The power trace 61, component 801, power pad 811 and signal pad 802 of component 801 are not shifted to the left, so through holes and laser holes cannot be set at the notch 330. Only ground line 99 is added at the board edge 334 between sensitive signal line 40 and notch 330. Since there is no interference source at the board edge 334 between sensitive signal line 40 and notch 330, this design basically meets the design requirements of sensitive signal line 40 (such as RF traces, microphone sampling signal traces, etc.).

[0128] Due to space constraints on PCB board 310, through holes cannot be added to the left of sensitive signal line 40. In the vertical direction from bottom to top, where laser holes 43 to 58 are distributed, only a single row of laser holes can be added: laser hole 43, laser hole 42, laser hole 388, and laser hole 58.

[0129] A gap 50 with a width of L33 is provided between the sensitive signal line 40 and the ground copper foil 52 and the ground line 99.

[0130] A gap 689 (i.e., a copper-free area) is formed between the ground copper foil 52 and the edge 334 of the PCB board 310. The width of the gap 689 is L50 ≥ 0.15 mm (preferably L50 ≥ 0.2 mm). The gap 689 is used to maintain a safe distance between the ground copper foil 52 and the edge of the PCB board 310, so as to prevent the PCB manufacturer from scratching the ground copper foil 52 with the milling cutter when processing the edge 334 of the PCB board 310, which would cause the ground copper foil 52 to be exposed and oxidized.

[0131] A gap 688 (i.e., the copper-free area) exists between the ground wire 99 and the edge 334 of the PCB board 310. The width of the gap 688 is L50 ≥ 0.15 mm (preferably L50 ≥ 0.2 mm). The gap 688 is used to maintain a safe distance between the ground wire 99 and the edge of the PCB board 310, so as to prevent the PCB manufacturer from scratching the ground copper foil 52 with the milling cutter when processing the edge 334 of the PCB board 310, which would lead to the exposure of the ground copper foil 52 and oxidation problems. Apart from the above differences, Figure 13 Other parts of the plan and Figure 11 They are all the same, so I will not repeat the description.

[0132] Figure 13 The application scenarios shown are mainly found in vehicles with small PCB board size and very high density, such as vehicle trackers (which belong to vehicle wireless devices) and dashcams (which belong to vehicle wireless devices).

[0133] Figure 14 that is Figure 13 A partial cross-sectional view of the TOP layer and L02 layer (second layer) in the horizontal direction of laser aperture 206 and laser aperture 30 along the vertical direction of position A1. Figure 15 that is Figure 13 A partial cross-sectional view of the TOP layer and L02 layer (second layer) in the horizontal direction of the through hole 205 along the vertical direction of position A2.

[0134] Figure 16 that is Figure 13 A partial cross-sectional view of the TOP layer and L02 layer (second layer) in the horizontal direction of the through hole 202 and the laser hole 388 along the vertical direction of position A3; Figure 17 that is Figure 13 A partial cross-sectional view of the TOP layer and L02 layer (second layer) in the horizontal direction of laser apertures 211, 31, and 42 along the vertical direction of position A4. Figures 13-17 The ground copper foil 208 of the middle L02 layer is electrically connected to the ground copper foil 207 of the TOP layer through laser holes 206, 30, 205, 201, 32, 202, 200, and 33. The ground copper foil 208 is electrically connected to the ground copper foil 52 of the TOP layer through laser holes 43, 42, 388, and 58.

[0135] Figure 18 A top view of the top layer of a printed circuit board provided in another embodiment of this application.

[0136] and Figure 10 Compare, Figure 18 Will Figure 10The power trace 61, component 801, power pad 811 of component 801, and signal pad 802 are removed and replaced by the board edge 331 of PCB board 310. Specifically, ground copper foil 207 and ground copper foil 52 are placed in the narrow space between the signal trace 60 (e.g., clock trace), signal via 803 (signal vias include signal through holes and signal laser holes; only signal through hole 803 is used as an example, and the type of signal via is not limited), power via 804 (power vias include power through holes and power laser holes; only power through hole 804 is used as an example, and the type of power via is not limited) and the board edge 333 of PCB board 310. A gap 51 (i.e., a copper-free area) is provided between the sensitive signal line 40 and the ground copper foil 207, a gap 50 (i.e., a copper-free area) is provided between the sensitive signal line 40 and the ground copper foil 52, and a gap 69 (i.e., a copper-free area) is provided between the ground copper foil 207 and the edge 331 of the PCB board 310. The width of the gap 69 is L51 ≥ 0.15 mm (preferably L51 ≥ 0.2 mm). The gap 69 is used to maintain a safe distance between the ground copper foil 207 and the edge of the PCB board 310, so as to prevent the PCB manufacturer from scratching the ground copper foil 207 with the milling cutter when processing the edge 331 of the PCB board 310, which would cause the ground copper foil 207 to be exposed and oxidized.

[0137] Figure 18 This refers to the case where the sensitive signal 40 trace area is close to the left edge 331 of the PCB board 310, meaning that the first line and the first trace are distributed on the right side of the sensitive signal 40 trace area. However, the first line and the first trace are not distributed on the left edge 331 of the PCB board 310.

[0138] Figure 18 The first trace in the solution includes a signal via 803 (signal vias include signal through holes and signal laser holes; this example only uses signal through hole 803 and does not limit the type of signal via) and a power via 804 (power vias include power through holes and power laser holes; this example only uses power through hole 804 and does not limit the type of power via). The first trace includes a signal trace 60 (e.g., a clock trace).

[0139] In addition to the differences mentioned above, Figure 18 Other parts of the plan and Figure 10 They are all the same, so I will not repeat the description.

[0140] It should be noted that, in order to demonstrate the rationality and practicality of the design of the radio frequency signal (sensitive signal) structure in the printed circuit board provided in the above embodiments of the present invention, in order to Figure 18 The sensitive signal (radio frequency signal) structure in dashcams, combined with a WiFi antenna, is used in dashcams. Taking dashcams as an example, the following is the process of testing and analyzing the active WiFi signal of dashcams:

[0141] The experimental environment included an OTA anechoic chamber and a network analyzer. Table 1 shows the active S11 test data of the WiFi antenna in the dashcam: the S11 value of the WiFi antenna in the 2412MHz band is -10.329dB, the S11 value in the 2442MHz band is -10.387dB, and the S11 value in the 2484MHz band is -11.003dB. The S11 values ​​of the WiFi antenna in the 2412MHz, 2442MHz, and 2484MHz bands are all less than -10dB, which meets the requirements of dashcams (broadband products) for WiFi antenna S11 parameters. That is, within the 100MHz bandwidth range of 2.4GHz to 2.5GHz, VSWR < 2, which fully meets the bandwidth requirements of dashcams (broadband products) for high-throughput data transmission of 2.4G Wi-Fi, proving that the design of the RF signal (sensitive signal) structure in the printed circuit board provided in this embodiment of the invention is reasonable and scientific.

[0142] Table 1. S11 Test Data for WiFi Antennas

[0143] Channel Test requirements specifications Test data Does it meet the requirements? 2412 <-10dB -10.465dB satisfy 2442 <-10dB -10.493dB satisfy 2484 <-10dB -11.015dB satisfy

[0144] Furthermore, the design rationality and practicality of the radio frequency signal (sensitive signal) structure in the printed circuit board provided by the embodiments of the present invention are as follows: Figure 11 The sensitive signal (RF signal) structure in the system, combined with the LTE antenna, is used in vehicle trackers (belonging to wireless vehicle devices). Taking a vehicle tracker as an example, the following is the process of active test analysis of the transmission and reception of the five bands of the vehicle tracker:

[0145] The experimental environment included an OTA anechoic chamber and a network analyzer. Table 2 presents the active test data for LTE antenna transmission and reception across the four bands of the complete device. As shown in Table 2, the transmission test selected five LTE bands: LTE Band 38, LTE Band 39, LTE Band 40, LTE Band 41, and LTE Band 34. Specifically, when LTE Band 38 selected channel 38150, the operating frequency was 2610MHz, and the transmit power in TRP mode was 20.53dBm; when LTE Band 38 selected channel 38150, the operating frequency was 2610MHz, and the receive sensitivity in TIS mode was -95.86dBm. When LTE Band 39 selects channel 3855, the operating frequency is 1910MHz, and the transmit power in TRP mode is 19.88dBm; when LTE Band 39 selects channel 3855, the operating frequency is 1910MHz, and the transmit power in TIS mode is -92.27dBm. When LTE Band 40 selects channel 39550, the operating frequency is 2390MHz, and the transmit power in TRP mode is 20.89dBm; when LTE Band 40 selects channel 39550, the operating frequency is 2390MHz, and the receive sensitivity in TIS mode is -95.97dBm. When LTE Band 41 selects channel 41490, the operating frequency is 2680MHz, and the transmit power in TRP mode is 20.23dBm; when LTE Band 41 selects channel 41490, the operating frequency is 2680MHz, and the receive sensitivity in TIS mode is -95.9dBm. When LTE Band 34 selects channel 36275, the operating frequency is 2017.5MHz, and the transmit power in TRP mode is 19.25dBm; when LTE Band 34 selects channel 36275, the operating frequency is 2017.5MHz, and the receive sensitivity in TIS mode is -93.26dBm. The above test data, regardless of the transmit power in TRP mode or the receive sensitivity in TIS mode, are within the allowable range for LTE and meet the design requirements of the vehicle tracker (a wireless vehicle-mounted device).

[0146] Table 2. Active test data of LTE antenna transmission and reception across 4 bands of the entire device.

[0147]

[0148] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0149] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0150] It should be noted that in the description of this application, the terms "first" and "second" are used only for convenience in describing different components and should not be construed as indicating or implying a sequential relationship, relative importance, or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of those features.

[0151] The embodiments or implementation methods in this application are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0152] In the description of this application, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this application. In this application, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0153] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A printed circuit board, characterized in that, include: A top layer and a bottom layer, wherein a routing area is provided in the top layer and / or the bottom layer, and at least one sensitive signal line is provided in the routing area; A first copper foil and / or a second copper foil, wherein the first copper foil is disposed on one side of the trace area and the second copper foil is disposed on the other side of the trace area; One or more intermediate layers are disposed between the top layer and the bottom layer, and a third copper foil is disposed on the intermediate layers; Multiple first vias are disposed on the first copper foil, the first vias penetrate the first copper foil, and the first copper foil is connected to the third copper foil through the copper of the hole wall of the first via; And / or, a plurality of second vias are disposed on the second copper foil, the second vias penetrate the second copper foil, and the second copper foil is connected to the third copper foil through the copper of the hole wall of the second via; The plurality of first vias include a plurality of first laser holes and a plurality of first through holes, and the plurality of second vias include a plurality of second laser holes and a plurality of second through holes; The first through-hole and the second through-hole penetrate the printed circuit board, and the bottom layer, each of the intermediate layers and the top layer are electrically connected through the first through-hole and the second through-hole; The first laser hole extends from the first copper foil to the third copper foil, and a first copper pillar is provided in the first laser hole. The first copper foil and the third copper foil are electrically connected through the first copper pillar. And / or, the second laser aperture extends from the second copper foil to the third copper foil, a second copper pillar is provided in the second laser aperture, and the second copper foil and the third copper foil are electrically connected through the second copper pillar.

2. The printed circuit board according to claim 1, characterized in that, The arrangement direction of the plurality of first through holes is the same as the routing direction of the sensitive signal line, and one or more first laser holes are provided between two adjacent first through holes; And / or, the arrangement direction of several second through holes is the same as the routing direction of the sensitive signal line, and one or more second laser holes are provided between two adjacent second through holes.

3. The printed circuit board according to claim 2, characterized in that, At least one first laser hole is provided between two adjacent first through holes; And / or, at least one second laser hole is provided between two adjacent second through holes.

4. The printed circuit board according to claim 3, characterized in that, At least two first laser holes are provided between two adjacent first through holes; the arrangement direction of the at least two first laser holes is perpendicular to the routing direction of the sensitive signal line; And / or, at least two second laser holes are provided between two adjacent second through holes, and the arrangement direction of the at least two second laser holes is perpendicular to the routing direction of the sensitive signal line.

5. The printed circuit board according to claim 4, characterized in that, The two adjacent first laser holes are tangent to each other, or the edge spacing between the two adjacent first laser holes is less than or equal to 1.5 mm; The two adjacent second laser holes are tangent to each other, or the edge spacing between two adjacent second laser holes is less than or equal to 1.5 mm; The adjacent first laser aperture is tangent to the first through hole, or the edge distance between the adjacent first laser aperture and the first through hole is less than or equal to 1.5 mm; The adjacent second laser aperture is tangent to the second through hole, or the edge distance between the adjacent second laser aperture and the second through hole is less than or equal to 1.5 mm.

6. The printed circuit board according to claim 1, characterized in that, The arrangement direction of the plurality of first through holes is the same as the routing direction of the sensitive signal line, and one or more first laser holes are provided between two adjacent first through holes; And / or, the arrangement direction of several second vias is the same as the routing direction of the sensitive signal line, the second vias are disposed close to the edge of the printed circuit board, and the second copper foil is also connected to a ground line, the ground line being in the same routing direction as the sensitive signal line; And / or, one or more second laser holes are provided between two adjacent second through holes, the arrangement direction of the plurality of second laser holes is the same as the routing direction of the sensitive signal line, the second through holes are provided near the edge of the printed circuit board, and the second copper foil is also connected to a ground line, the ground line is in the same routing direction as the sensitive signal line.

7. The printed circuit board according to any one of claims 1-6, characterized in that, Multiple sensitive signal lines are arranged in the routing area, with adjacent sensitive signal lines spaced apart. The sensitive signal lines closer to the first copper foil are spaced apart from the first copper foil, and the sensitive signal lines closer to the second copper foil are spaced apart from the second copper foil.

8. The printed circuit board according to claim 7, characterized in that, It also includes at least one first line and / or a first routing; The first line and / or the first trace is located on the side of the first copper foil away from the trace area; and / or, the first line and / or the first trace is located on the side of the second copper foil away from the trace area; The first line includes one or more of power pads, signal pads, signal vias, and power vias; the first trace includes one or more of power traces or power copper foil and signal traces.

9. The printed circuit board according to claim 8, characterized in that, The trace area is located on the top layer, and at least one of the bottom layer and each of the intermediate layers is further provided with a second trace and / or a second line, wherein the second trace and / or the second line is located within the projection range of the first copper foil, the trace area and the second copper foil. And / or, the trace area is disposed on the bottom layer, and at least one of the top layer and each of the intermediate layers is further provided with a second trace and / or a second line, wherein the second trace / or the second line is located within the projection range of the first copper foil, the trace area and the second copper foil.

10. The printed circuit board according to claim 8, characterized in that, The trace area is located on the top layer, and at least one of the intermediate layers is further provided with a second trace and a second line. The bottom layer is provided with electronic components. The second trace, the second line, and the electronic components are located within the projection range of the first copper foil, the trace area, and the second copper foil.

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