Semiconductor Structure and Method for Processing Semiconductor Structure

Abstract

The present disclosure provides a semiconductor structure and a method for processing the semiconductor structure. The semiconductor structure includes a substrate, a bit line structure, a multi-layer side isolation layer, and a top isolation layer. The bit line structure is disposed on the substrate. The multi-layer side isolation layer is sequentially disposed on the side surface of the bit line structure from the inside to the outside. The top isolation layer covers the top surfaces of the bit line structure and the multi-layer side isolation layer. By covering the top surfaces of the bit line structure and the multi-layer side isolation layer with the top isolation layer, the present disclosure can use the top isolation layer to protect the side isolation layer from oxidation in subsequent manufacturing processes, avoid the formation of voids in the device due to the oxidation of the side isolation layer, and is beneficial to improving the product yield.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for processing a semiconductor structure. Background Art

[0002] For semiconductor devices such as dynamic random access memories, in order to reduce the Cbl of the devices, the existing solution is to integrate a silicon carbon oxide (SiCO, i.e., oxygen-doped silicon carbide) spacer into the bit line structure of the semiconductor device. However, it has been found through research that the above-mentioned silicon carbon oxide spacer is extremely easy to be oxidized, resulting in voids in the device and reducing the product yield. Summary of the Invention

[0003] A main object of the present disclosure is to overcome at least one defect of the above-mentioned prior art, and to provide a semiconductor structure in which a silicon carbon oxide spacer is not easily oxidized.

[0004] Another main object of the present disclosure is to overcome at least one defect of the above-mentioned prior art, and to provide a method for processing a semiconductor structure that can protect a silicon carbon oxide spacer from being oxidized during the manufacturing process.

[0005] To achieve the above object, the present disclosure adopts the following technical solutions:

[0006] According to one aspect of the present disclosure, there is provided a semiconductor structure, including a substrate, a bit line structure, a multi-layer side isolation layer, and a top isolation layer; the bit line structure is disposed on the substrate; the multi-layer side isolation layer is sequentially disposed on the side of the bit line structure from the inside to the outside; the top isolation layer covers the top surface of the bit line structure and the top surface of the multi-layer side isolation layer.

[0007] According to one embodiment of the present disclosure, the side surface of the top isolation layer is flush with the side surface of the outermost side isolation layer.

[0008] According to one embodiment of the present disclosure, the edge of the top isolation layer covers a part of the side surface of the outermost side isolation layer.

[0009] According to one embodiment of the present disclosure, along the direction parallel to the top surface of the top isolation layer, the ratio of the width of the part of the top isolation layer that extends beyond the outermost side isolation layer to the overall width of the top isolation layer is 1:20 to 1:5.

[0010] According to one embodiment of the present disclosure, the ratio of the height of the part of the side isolation layer covered by the top isolation layer to the total height of the side isolation layer is 1:30 to 1:10.

[0011] According to one embodiment of the present disclosure, the thickness of the top isolation layer is 30 nm to 50 nm.

[0012] According to one embodiment of the present disclosure, the material of the top isolation layer is the same as that of the outermost side isolation layer.

[0013] According to one embodiment of the present disclosure, the material of the top isolation layer is silicon nitride.

[0014] According to one embodiment of the present disclosure, the multi-layer side isolation layer includes a first side isolation layer, a second side isolation layer, and a third side isolation layer from inside to outside, where: the material of the first side isolation layer is silicon oxycarbide; and / or, the material of the second side isolation layer is silicon oxide; and / or, the material of the third side isolation layer is silicon nitride.

[0015] According to one embodiment of the present disclosure, the bit line structure includes a bit line contact layer, a bit line conductive layer, and a bit line insulating layer; the bit line contact layer is disposed on the substrate; the bit line conductive layer is disposed on the top surface of the bit line contact layer; the bit line insulating layer is disposed on the top surface of the bit line conductive layer.

[0016] According to one embodiment of the present disclosure, where: the material of the bit line contact layer is polysilicon; and / or, the material of the bit line conductive layer is tungsten; and / or, a titanium nitride layer is disposed between the bit line conductive layer and the bit line contact layer.

[0017] According to another aspect of the present disclosure, a method for processing a semiconductor structure is provided, including: providing a substrate, forming a bit line structure on the substrate, an oxidation material is filled between adjacent bit line structures, and a multi-layer side isolation layer is sequentially disposed on the side surface of the bit line structure from inside to outside; patterning the oxidation material, and the side isolation layer located on the top surface of the bit line structure is removed during the patterning process; forming a top isolation layer on the top surfaces of the bit line structure and the multi-layer side isolation layer; and forming a capacitor contact layer between adjacent bit line structures.

[0018] According to one embodiment of the present disclosure, in the step of patterning the oxidation material, an oxygen-free etching process is used, and the material of the precursor is fluorine.

[0019] According to one embodiment of the present disclosure, it further includes: after the side isolation layer located on the top surface of the bit line structure is removed, using oxygen-free plasma to remove impurities on the top surfaces of the bit line structure and the side isolation layer.

[0020] According to one embodiment of the present disclosure, the plasma material of the oxygen-free plasma is hydrogen, nitrogen, or a mixed gas of hydrogen and nitrogen.

[0021] According to one embodiment of the present disclosure, the oxidation material is filled between adjacent bit line structures by a deposition process with low temperature and low radio frequency power. The temperature of the deposition process is less than 75°C, and the radio frequency power is less than 350 W.

[0022] As can be seen from the above technical solutions, the advantages and positive effects of the semiconductor structure and the method for processing the semiconductor structure proposed by the present disclosure are as follows:

[0023] The semiconductor structure proposed by the present disclosure includes a substrate, bit line structures, a multi-layer side isolation layer, and a top isolation layer. By covering the top isolation layer on the top surface of the bit line structures and the top surface of the multi-layer side isolation layer, the present disclosure can use the top isolation layer to protect the side isolation layer from oxidation in subsequent manufacturing processes, avoiding the formation of voids in the device due to the oxidation of the side isolation layer, which is beneficial to improving the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] By considering the following detailed description of the preferred embodiments of the present disclosure in conjunction with the accompanying drawings, various objectives, features, and advantages of the present disclosure will become more apparent. The drawings are only exemplary illustrations of the present disclosure and are not necessarily drawn to scale. In the drawings, the same reference numerals always represent the same or similar components. Among them:

[0025] Figure 1 is a partial structural schematic diagram of a semiconductor structure shown according to an exemplary embodiment;

[0026] Figure 2 is a partial structural schematic diagram of a semiconductor structure shown according to another exemplary embodiment;

[0027] Figure 3 is a partial structural schematic diagram of a semiconductor structure shown according to another exemplary embodiment;

[0028] Figure 4 is a flowchart of a method for processing a semiconductor structure shown according to an exemplary embodiment;

[0029] Figure 5 and Figure 6 are respectively partial structural schematic diagrams of the semiconductor structure at several steps of the method for processing the semiconductor structure shown in Figure 4 shown.

[0030] The description of the reference numerals is as follows:

[0031] 100. Bit line structure;

[0032] 110. Bit line contact layer;

[0033] 120. Bit line conductive layer;

[0034] 130. Bit line insulating layer;

[0035] 210. First side isolation layer;

[0036] 220. Second side isolation layer;

[0037] 230. Third side isolation layer;

[0038] 300. Top isolation layer;

[0039] D. Thickness;

[0040] G. Impurities;

[0041] H0. Height;

[0042] H1. Height;

[0043] PG. Oxygen-free plasma;

[0044] S1 to S4. Steps;

[0045] W0. Width;

[0046] W1. Width. Detailed implementation manners

[0047] Typical embodiments embodying the features and advantages of the present disclosure will be described in detail in the following description. It should be understood that the present disclosure can have various variations in different embodiments, all of which do not depart from the scope of the present disclosure, and the descriptions and drawings therein are for illustrative purposes in nature and not for limiting the present disclosure.

[0048] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form a part of the present disclosure and in which are shown by way of example different exemplary structures, systems, and steps that can implement various aspects of the present disclosure. It should be understood that other specific solutions of components, structures, exemplary devices, systems, and steps can be used and structural and functional modifications can be made without departing from the scope of the present disclosure. Moreover, although terms such as "above", "between", "inside", etc. may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, for example, according to the directions of the examples described in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional direction of the structure to fall within the scope of the present disclosure.

[0049] Refer to Figure 1, which representatively shows a partial structural schematic diagram of the semiconductor structure proposed by the present disclosure, and specifically shows a partial structure of a bit line structure 100 of the semiconductor structure. In this exemplary embodiment, the semiconductor structure proposed by the present disclosure is described by taking a resistive random access memory as an example. It is easy for those skilled in the art to understand that, in order to apply the related designs of the present disclosure to other types of semiconductor devices, various modifications, additions, substitutions, deletions or other changes are made to the following specific embodiments, and these changes are still within the scope of the principle of the semiconductor structure proposed by the present disclosure.

[0050] As Figure 1 shown, in this embodiment, the semiconductor structure proposed by the present disclosure includes a substrate, a bit line structure 100, a multi-layer side isolation layer, and a top isolation layer 300. Specifically, the bit line structure 100 is disposed on the substrate. The multi-layer side isolation layer is sequentially disposed on the side of the bit line structure 100 from the inside to the outside. The top isolation layer 300 covers the top surface of the bit line structure 100 and the top surface of the multi-layer side isolation layer. The top surface of the bit line structure 100 refers to the surface of the bit line structure 100 away from the substrate side, and the top surface of the multi-layer side isolation layer refers to the surface of the multi-layer side isolation layer away from the substrate side. It can be known that the top surface referred to in the embodiments of the present application is the surface away from the substrate side. Through the above design, the semiconductor structure proposed by the present disclosure can protect the side isolation layer from oxidation by covering the top isolation layer 300 on the top surfaces of the bit line structure 100 and the side isolation layer, and avoid the formation of voids in the device due to the oxidation of the side isolation layer, which is beneficial to improving the product yield.

[0051] As described above, as Figure 1 shown, in this embodiment, the semiconductor structure is described by taking the semiconductor structure including three side isolation layers as an example. These three side isolation layers are the first side isolation layer 210, the second side isolation layer 220, and the third side isolation layer 230 from the inside to the outside. That is, the first side isolation layer 210 is in direct contact with the bit line structure 100, the third side isolation layer 230 is the outermost side isolation layer, and the second side isolation layer 220 is located between the first side isolation layer 210 and the second side isolation layer 220. In some embodiments, the semiconductor structure proposed by the present disclosure may also include two, four or more side isolation layers, and is not limited thereto.

[0052] As Figure 1 shown, in this embodiment, the side surface of the top isolation layer 300 may be flush with the side surface of the third side isolation layer 230 (i.e., the outermost side isolation layer).

[0053] In some embodiments, as Figure 2 shown, along the direction parallel to the top surface of the top isolation layer 300, the top isolation layer 300 may also extend beyond the side surface of the third side isolation layer 230.

[0054] In some embodiments, such as Figure 3 shown, the edge of the top isolation layer 300 may also cover a partial side surface of the third side isolation layer 230.

[0055] Such as Figure 2 and Figure 3 shown, in some embodiments, along the direction parallel to the top surface of the top isolation layer 300, the width W1 of the part (taking one side as an example) of the top isolation layer 300 that extends beyond the third side isolation layer 230, and the ratio of the overall width W0 of the top isolation layer 300 can be 1:20 to 1:5, such as 1:20, 1:15, 1:10, 1:5, etc., so as to enhance the adhesion between the top isolation layer 300 and the top surface of the bit line structure 100 and the top surfaces of the multi-layer side isolation layers. In some embodiments, the ratio of the width W1 to the width W0 can also be less than 1:20, or can be greater than 1:5, such as 1:21, 3:10, etc., and is not limited thereto.

[0056] Such as Figure 3 shown, in some embodiments, the height H1 of the partial side surface of the side isolation layer covered by the top isolation layer 300, and the ratio of the total height H0 of this side isolation layer can be 1:30 to 1:10, such as 1:30, 1:20, 1:15, 1:10, etc., so as to enhance the adhesion between the top isolation layer 300 and the side isolation layer. In some embodiments, the ratio of the height H1 to the height H0 can also be less than 1:30, or can be greater than 1:10, such as 1:31, 3:20, etc., and is not limited thereto.

[0057] Such as Figure 1 shown, in this embodiment, the thickness D of the top isolation layer 300 can be 30 nm to 50 nm, such as 30 nm, 35 nm, 40 nm, 50 nm, etc. In some embodiments, the thickness D of the top isolation layer 300 can also be less than 30 nm, or can be greater than 50 nm, such as 29 nm, 52 nm, etc., and is not limited thereto.

[0058] In this embodiment, the material of the top isolation layer 300 can be the same as that of the third side isolation layer 230 (i.e., the outermost side isolation layer).

[0059] In this embodiment, the material of the top isolation layer 300 can be silicon nitride (Si3N4).

[0060] In this embodiment, the material of the first side isolation layer 210 can be silicon carbon oxide (SiCO).

[0061] In this embodiment, the material of the second side isolation layer 220 can be silicon oxide (SiO2).

[0062] In this embodiment, the material of the third side isolation layer 230 may be silicon nitride.

[0063] As Figure 1 shown, in this embodiment, the bit line structure 100 may include a bit line contact layer 110, a bit line conductive layer 120, and a bit line insulating layer 130. Specifically, the bit line contact layer 110 is disposed on the substrate. The bit line conductive layer 120 is disposed on the top surface of the bit line contact layer 110. The bit line insulating layer 130 is disposed on the top surface of the bit line conductive layer 120. On this basis, the multi-layer side isolation layers are sequentially disposed on the sides of the bit line contact layer 110, the bit line conductive layer 120, and the bit line insulating layer 130 from the inside to the outside, that is, the first side isolation layer 210 covers the sides of the bit line contact layer 110, the bit line conductive layer 120, and the bit line insulating layer 130. Furthermore, the top isolation layer 300 covers at least the top surface of the bit line insulating layer 130 and the top surfaces of the multi-layer side isolation layers.

[0064] In this embodiment, the material of the bit line contact layer 110 may be polysilicon.

[0065] In this embodiment, the material of the bit line conductive layer 120 may be tungsten (W).

[0066] In this embodiment, a titanium nitride layer (TiN, such as Ti2N2 or Ti3N4) may be disposed between the bit line conductive layer 120 and the bit line contact layer 110.

[0067] In this embodiment, the semiconductor structure proposed by the present disclosure may further include a capacitor contact layer, and the capacitor contact layer may be formed by patterning an oxide material filled between adjacent bit line structures 100. Among them, the oxide material may be filled between adjacent bit line structures 100 by a deposition process with low temperature and low radio frequency power.

[0068] Among them, the top isolation layer 300 can be formed during the formation of the bit capacitor contact layer. Specifically, the side isolation layer can first cover the side and top surfaces of the bit line structure 100 during the manufacturing process. During the patterning process of the oxidation material between adjacent bit line structures 100, after the oxidation material starts to be patterned, the side isolation layer located on the top surface of the bit line structure 100 will be etched away. At this time, the top isolation layer 300 can be first formed on the top surface of the bit line structure 100 and the top surface of the remaining side isolation layer, and then the oxidation material is continuously patterned, and finally the capacitor contact layer is formed between adjacent bit line structures 100. During this patterning process, the top isolation layer 300 covering the oxidation material is etched away together. At the same time, the top isolation layer 300 covering the top surfaces of the bit line structure 100 and the side isolation layer can provide a protective effect for the side isolation layer, preventing the side isolation layer from being oxidized during the patterning process of the oxidation material, and further avoiding the problem that the oxidized isolation layer causes voids in the device during subsequent processes and affects the device yield.

[0069] It should be noted that the above patterning process of the oxidation material can be understood as an overall manufacturing process in which the semiconductor structure forms a capacitor contact layer by patterning the oxidation material. On this basis, in this overall manufacturing process, the side isolation layer located on the top surface of the bit line structure 100 will be etched away during the patterning process of the oxidation material. In the present disclosure, after this part of the side isolation layer is etched away, the top isolation layer 300 is first formed, and then the oxidation material is continuously etched, and the top isolation layer 300 can protect the top of the remaining side isolation layer from being oxidized during the continued patterning process.

[0070] In addition, when forming the top isolation layer 300, a layer of the top isolation layer 300 can be first deposited on the surface of the semiconductor structure, that is, the top isolation layer 300 can cover the top surfaces of the bit line structure 100 and the side isolation layer. Accordingly, during the continued patterning process of the oxidation material, the top isolation layer 300 covering the top surfaces of the bit line structure 100 and the side isolation layer can provide a protective effect for the side isolation layer, and the top isolation layer 300 covering the oxidation material will be etched away. On this basis, when depositing the top isolation layer 300, the thickness of the top isolation layer 300 covering the top surfaces of the bit line structure 100 and the side isolation layer can be made greater than the thickness of the top isolation layer 300 covering the oxidation material, so that during the patterning process of the oxidation material, the top isolation layer 300 covering the oxidation material can be etched away, and the top isolation layer 300 covering the top surfaces of the bit line structure 100 and the side isolation layer can maintain its protective effect. In this embodiment, when the oxidation material is filled by a deposition process, the temperature of the deposition process can be less than 75 °C, such as 30 °C, 50 °C, 65 °C, 74 °C, etc.

[0071] In this embodiment, when the oxidation material is filled by a deposition process, the radio frequency power of the deposition process can be less than 350 W, such as 250 W, 300 W, 345 W, etc.

[0072] In this embodiment, the patterning process of the oxidation material can adopt an oxygen-free etching process, and the oxygen-free etching process can use fluorine (F) as a precursor.

[0073] It should be noted here that the semiconductor structures shown in the drawings and described in this specification are only a few examples of the many semiconductor structures that can adopt the principles of the present disclosure. It should be clearly understood that the principles of the present disclosure are by no means limited to any details or any components of the semiconductor structures shown in the drawings or described in this specification.

[0074] Based on the above detailed description of several exemplary embodiments of the semiconductor structure proposed by the present disclosure, an exemplary embodiment of the processing method of the semiconductor structure proposed by the present disclosure will be described below.

[0075] Refer to Figure 4 , which representatively shows a schematic flow chart of the processing method of the semiconductor structure proposed by the present disclosure. In this exemplary embodiment, the processing method of the semiconductor structure proposed by the present disclosure is described by taking a static random access memory as an example. It is easy for those skilled in the art to understand that in order to apply the relevant designs of the present disclosure to the processing processes of other types of semiconductor devices, various modifications, additions, substitutions, deletions, or other changes are made to the following specific embodiments, and these changes are still within the scope of the principles of the processing method of the semiconductor structure proposed by the present disclosure.

[0076] As Figure 4 shown, in this embodiment, the processing method of the semiconductor structure proposed by the present disclosure includes:

[0077] Step S1: Provide a substrate, form a bit line structure 100 on the substrate, an oxidation material is filled between adjacent bit line structures 100, and multiple layers of side isolation layers are sequentially arranged on the side of the bit line structure 100 from the inside to the outside;

[0078] Step S2: Pattern the oxidation material, and the side isolation layer located on the top surface of the bit line structure 100 is removed during this patterning process;

[0079] Step S3: Form a top isolation layer 300 on the top surfaces of the bit line structure 100 and the multiple layers of side isolation layers;

[0080] Step S4: Form a capacitor contact layer between adjacent said bit line structures.

[0081] Through the above process design, the top isolation layer 300 covers the top surfaces of the bit line structure 100 and the multi-layer side isolation layer in the present disclosure, enabling the top isolation layer 300 to protect the side isolation layer from oxidation in subsequent processes, avoiding the formation of voids in the device due to the oxidation of the side isolation layer, and being conducive to improving the product yield.

[0082] In step S1, the semiconductor structure includes a substrate, a bit line structure 100, an oxidation material, and a multi-layer side isolation layer. Among them, the bit line structure 100 is formed on the substrate. The surface of the bit line structure 100 (including its top surface and side surfaces) is sequentially covered with a multi-layer side isolation layer from the inside to the outside. The oxidation material is filled between adjacent bit line structures 100.

[0083] In the present embodiment, for step S1, the oxidation material can be filled between adjacent bit line structures 100 by a deposition process at low temperature and low radio frequency power.

[0084] In the present embodiment, for step S1, when the oxidation material is filled by a deposition process, the temperature of the deposition process can be less than 75 °C, such as 30 °C, 50 °C, 65 °C, 74 °C, etc.

[0085] In the present embodiment, for step S1, when the oxidation material is filled by a deposition process, the radio frequency power of the deposition process can be less than 350 W, such as 250 W, 300 W, 345 W, etc.

[0086] In the present embodiment, for step S1, taking the example that the surface of the bit line structure 100 is sequentially covered with three side isolation layers from the inside to the outside, these three side isolation layers can be the first side isolation layer 210, the second side isolation layer 220, and the third side isolation layer 230 respectively. That is, the first side isolation layer 210 is in direct contact with the bit line structure 100, the third side isolation layer 230 is the outermost side isolation layer, and the second side isolation layer 220 is located between the first side isolation layer 210 and the second side isolation layer 220. On this basis, the material of the first side isolation layer 210 can be silicon oxycarbide.

[0087] In the present embodiment, for step S1, the material of the second side isolation layer 220 can be silicon oxide.

[0088] In the present embodiment, for step S1, the material of the third side isolation layer 230 can be silicon nitride.

[0089] In this embodiment, for step S1, the bit line structure 100 may include a bit line contact layer 110, a bit line conductive layer 120, and a bit line insulating layer 130. Specifically, the bit line contact layer 110 is disposed on the substrate. The bit line conductive layer 120 is disposed on the top surface of the bit line contact layer 110. The bit line insulating layer 130 is disposed on the top surface of the bit line conductive layer 120. On this basis, the multi-layer side isolation layer is sequentially disposed on the sides of the bit line contact layer 110, the bit line conductive layer 120, and the bit line insulating layer 130 from the inside to the outside, and the side isolation layer in step S1 also covers the top surface of the bit line insulating layer 130.

[0090] In this embodiment, for step S1, the material of the bit line contact layer 110 may be polysilicon.

[0091] In this embodiment, for step S1, the material of the bit line conductive layer 120 may be tungsten.

[0092] In this embodiment, for step S1, a titanium nitride layer may be disposed between the bit line conductive layer 120 and the bit line contact layer 110.

[0093] In step S2, the semiconductor structure includes a substrate, the bit line structure 100, the remaining oxidation material, and the remaining side isolation layer. Among them, the oxidation material is partially etched and removed by patterning in this step S2, and the side isolation layer located on the top surface of the bit line structure 100 is removed simultaneously during the above patterning process. At this time, the remaining side isolation layer is located on the side of the bit line structure 100, and the top surfaces of the bit line structure 100 and the side isolation layer are both exposed.

[0094] In this embodiment, for step S2, the patterning process of the oxidation material may adopt an oxygen-free etch-back process, and the oxygen-free etch-back process may use fluorine as a precursor.

[0095] In this embodiment, as Figure 5 shown, for step S2, during the process of patterning the oxidation material, after the side isolation layer located on the top surface of the bit line structure 100 is removed, impurities G, such as residual photoresist particles, etc., will remain on the top of the bit line structure 100 and the remaining side isolation layer. Accordingly, as Figure 6 shown, the processing method of the semiconductor structure proposed by the present disclosure may also include:

[0096] Step S21, using oxygen-free plasma PG to remove the impurities G on the top surfaces of the bit line structure 100 and the side isolation layer.

[0097] In this embodiment, as Figure 6 shown, for step S21, the plasma material of the oxygen-free plasma PG may be hydrogen, nitrogen, or a mixed gas of hydrogen and nitrogen.

[0098] In step S3, the semiconductor structure includes a substrate, a bit line structure 100, remaining oxidation material, remaining side isolation layers, and a top isolation layer 300. Among them, the top isolation layer 300 can be a single layer in this step S3, that is, the top isolation layer 300 not only covers the top surfaces of the bit line structure 100 and the side isolation layers, but also covers the oxidation material.

[0099] In the present embodiment, for step S3, the material of the top isolation layer 300 can be the same as that of the outermost side isolation layer.

[0100] In the present embodiment, for step S3, the material of the top isolation layer 300 can be silicon nitride.

[0101] In step S4, the semiconductor structure includes a substrate, a bit line structure 100, remaining oxidation material, remaining side isolation layers, and a remaining top isolation layer 300. Among them, the oxidation material is continuously patterned and etched in this step S4, and finally a capacitive contact layer of the semiconductor structure is formed between adjacent bit line structures 100. During this patterning process, the top isolation layer 300 covering the oxidation material is etched and removed together. At the same time, the top isolation layer 300 covering the top surfaces of the bit line structure 100 and the side isolation layers can provide a protection effect for the side isolation layers, avoiding the side isolation layers from being oxidized during the patterning process of the oxidation material, and further avoiding the problem that the oxidized isolation layers cause voids in the device in subsequent processes and affect the device yield.

[0102] It should be noted that the etching of the oxidation material in step S2 and step S4 can be understood as an overall process in which the semiconductor structure forms a capacitive contact layer by etching the oxidation material. On this basis, in this overall process, the side isolation layer on the top surface of the bit line structure 100 will be etched off during the patterning process of the oxidation material. In the present disclosure, after this part of the side isolation layer is etched off, the top isolation layer 300 is first formed, and then the oxidation material is continuously etched, and the top isolation layer 300 can protect the top of the remaining side isolation layers from being oxidized during the continued patterning process.

[0103] In this embodiment, for step S3, a top isolation layer 300 may be deposited on the surface of the semiconductor structure, that is, the top isolation layer 300 may cover the top surfaces of the bit line structure 100 and the side isolation layer. Accordingly, in the subsequent etching process of the oxidation material (i.e., step S4), the top isolation layer 300 covering the top surfaces of the bit line structure 100 and the side isolation layer can provide a protection function for the side isolation layer, and the top isolation layer 300 covering the oxidation material will be etched away. On this basis, when depositing the top isolation layer 300, the thickness of the top isolation layer 300 covering the top surfaces of the bit line structure 100 and the side isolation layer can be made greater than the thickness of the top isolation layer 300 covering the oxidation material, which is convenient for the top isolation layer 300 covering the oxidation material to be etched away during the patterning process of the oxidation material, and the top isolation layer 300 covering the top surfaces of the bit line structure 100 and the side isolation layer can maintain its protection function.

[0104] In this embodiment, after step S4, the thickness D of the remaining top isolation layer 300 on the top surfaces of the bit line structure 100 and the side isolation layer may be 30 nm to 50 nm, such as 30 nm, 35 nm, 40 nm, 50 nm, etc. In some embodiments, the thickness D of the remaining top isolation layer 300 at the above positions may also be less than 30 nm, or may be greater than 50 nm, such as 29 nm, 52 nm, etc., and is not limited thereto.

[0105] It should be noted here that the processing methods of the semiconductor structure shown in the drawings and described in this specification are only several examples of many processing methods that can adopt the principles of the present disclosure. It should be clearly understood that the principles of the present disclosure are by no means limited to any details or any steps of the processing methods of the semiconductor structure shown in the drawings or described in this specification.

[0106] In summary, the semiconductor structure proposed by the present disclosure includes a substrate, a bit line structure 100, a multi-layer side isolation layer, and a top isolation layer 300. By covering the top surfaces of the bit line structure 100 and the multi-layer side isolation layer with the top isolation layer 300, the present disclosure can utilize the top isolation layer 300 to protect the side isolation layer from oxidation in subsequent processes, avoid the formation of voids in the device due to the oxidation of the side isolation layer, and is beneficial to improving the product yield.

[0107] Exemplary embodiments of the semiconductor structure and the method of processing the semiconductor structure proposed by the present disclosure have been described and / or illustrated in detail above. However, the embodiments of the present disclosure are not limited to the specific embodiments described herein. On the contrary, each component and / or step of each embodiment can be used independently and separately from other components and / or steps described herein. Each component and / or each step of one embodiment can also be used in combination with other components and / or steps of other embodiments. When introducing the elements / components / etc. described and / or illustrated herein, the terms "a", "an", and "the above" etc. are used to indicate the existence of one or more elements / components / etc. The terms "comprising", "including", and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc. Furthermore, the terms "first" and "second" etc. in the claims and the specification are only used as labels and are not numerical limitations on their objects.

[0108] Although the semiconductor structure and the method of processing the semiconductor structure proposed by the present disclosure have been described according to different specific embodiments, those skilled in the art will recognize that modifications can be made to the embodiments of the present disclosure within the spirit and scope of the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate; A bit line structure disposed on the substrate; A multi-layer side isolation layer sequentially disposed on the side of the bit line structure from inside to outside; A top isolation layer covering the top surface of the bit line structure and the top surface of the multi-layer side isolation layer, with the edge of the top isolation layer covering a part of the side surface of the outermost side isolation layer. Along the direction parallel to the top surface of the top isolation layer, the ratio of the width of the part of the top isolation layer exceeding the outermost side isolation layer to the overall width of the top isolation layer is 1:20 to 1:

5.

2. The semiconductor structure according to claim 1, characterized in that, The side surface of the top isolation layer is flush with the side surface of the outermost side isolation layer.

3. The semiconductor structure according to claim 1, characterized in that, The ratio of the height of the part of the side isolation layer covered by the top isolation layer to the total height of the side isolation layer is 1:30 to 1:

10.

4. The semiconductor structure according to claim 1, wherein The thickness of the top isolation layer is 30 nm to 50 nm.

5. The semiconductor structure according to claim 1, characterized in that The material of the top isolation layer is the same as that of the outermost side isolation layer.

6. The semiconductor structure according to claim 1, wherein, The material of the top isolation layer is silicon nitride.

7. The semiconductor structure according to claim 1, characterized in that, The multi-layer side isolation layer is respectively a first side isolation layer, a second side isolation layer, and a third side isolation layer from inside to outside: where The material of the first side isolation layer is silicon oxycarbide; and / or The material of the second side isolation layer is silicon oxide; and / or The material of the third side isolation layer is silicon nitride.

8. The semiconductor structure according to claim 1, wherein The bit line structure includes: A bit line contact layer disposed on the substrate; A bit line conductive layer disposed on the top surface of the bit line contact layer; and A bit line insulating layer disposed on the top surface of the bit line conductive layer.

9. The semiconductor structure according to claim 8, wherein: The material of the bit line contact layer is polysilicon; and / or The material of the bit line conductive layer is tungsten; and / or A titanium nitride layer is disposed between the bit line conductive layer and the bit line contact layer.

10. A processing method for forming the semiconductor structure according to any one of claims 1-9, comprising: Providing a substrate, forming a bit line structure on the substrate, filling an oxidation material between adjacent bit line structures, and sequentially disposing a multi-layer side isolation layer on the side of the bit line structure from inside to outside; Patterning the oxidation material, and removing the side isolation layer located on the top surface of the bit line structure during the patterning process; Forming a top isolation layer on the top surface of the bit line structure and the multi-layer side isolation layer; Forming a capacitor contact layer between adjacent bit line structures.

11. The method for processing a semiconductor structure according to claim 10, wherein In the step of patterning the oxidation material, an oxygen-free etching process is used, and the material of the precursor is fluorine.

12. The method for processing a semiconductor structure according to claim 10, wherein, Further comprising: After removing the side isolation layer located on the top surface of the bit line structure, using oxygen-free plasma to remove impurities on the top surface of the bit line structure and the side isolation layer.

13. The method for processing a semiconductor structure according to claim 12, wherein, The plasma material of the oxygen-free plasma is hydrogen, nitrogen, or a mixed gas of hydrogen and nitrogen.

14. The method for processing a semiconductor structure according to claim 10, wherein The oxidation material is filled between adjacent bit line structures by a deposition process at low temperature and low radio frequency power, and the temperature of the deposition process is less than 75 °C, and the radio frequency power is less than 350 W.

Images