Method for manufacturing a semiconductor structure and structure thereof

Abstract

Embodiments of the present application relate to the field of semiconductor, and provide a manufacturing method of a semiconductor structure and the structure thereof. The manufacturing method of the semiconductor structure comprises: providing a substrate, a plurality of spaced active regions on the substrate, and an isolation structure between adjacent active regions, wherein the active region comprises a plurality of sub-active regions, and the substrate further has an initial bit line, and the sub-active region intersects with the initial bit line; patterning the active region, the isolation structure and the initial bit line to form a word line trench extending along a third direction parallel to the surface of the substrate, the word line trench being located in the sub-active region, the isolation structure and the initial bit line, and the remaining initial bit line serving as a bit line; forming a gate dielectric layer on the surface of the sub-active region exposed by the word line trench; and forming a word line and an insulating structure, the word line being located on the gate dielectric layer and filling the word line trench, and the insulating structure being located between the word line and the bit line.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor, and particularly, to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] Memory is a memory component used to store programs and various data information. The random access memory (RAM) used by a general computer system can be divided into dynamic random access memory (DRAM) and static random access memory (SRAM). Dynamic random access memory is a commonly used semiconductor memory device in computers, which is composed of many repeated memory cells.

[0003] A memory cell generally includes a capacitor and a transistor. The drain of the transistor is connected to a bit line, and the source is connected to the capacitor. The capacitor includes a capacitor contact structure and a capacitor. The word line of the memory cell can control the opening or closing of the channel region of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.

[0004] However, the current manufacturing process of the memory is relatively complex. SUMMARY

[0005] Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, which at least have advantages of optimizing the process flow of the manufacturing method of the semiconductor structure.

[0006] According to some embodiments of the present application, the present application provides a manufacturing method of a semiconductor structure, which includes: providing a substrate, a plurality of spaced active regions on the substrate, and an isolation structure between adjacent active regions, the active regions extending along a first direction parallel to the surface of the substrate, and the active regions including a plurality of sub-active regions arranged along the first direction, and the substrate further having an initial bit line extending along a second direction parallel to the surface of the substrate, and the sub-active regions intersecting the initial bit line; patterning the active regions, the isolation structure, and the initial bit line to form a word line trench extending along a third direction parallel to the surface of the substrate, the word line trench being located in the sub-active region, the isolation structure, and the initial bit line, and the remaining initial bit line serving as a bit line; forming a gate dielectric layer on the surface of the sub-active region exposed by the word line trench; forming a word line and an insulating structure, the word line being located on the gate dielectric layer and filling the word line trench, and the insulating structure being located between the word line and the bit line.

[0007] In some embodiments, the initial bit line comprises: an initial bit line metal layer and an initial bit line contact layer stacked in sequence; in a process step of forming the word line trench, the word line trench penetrates the initial bit line contact layer at least in a direction perpendicular to the substrate surface, leaving the initial bit line contact layer as a bit line contact layer and the initial bit line metal layer as a bit line metal layer, the bit line contact layer and the bit line metal layer as the bit line.

[0008] In some embodiments, a depth of the word line trench within the initial bit line metal layer is less than or equal to 2 / 3 of a total thickness of the initial bit line metal layer.

[0009] In some embodiments, the steps of forming the active region, the isolation structure and the initial bit line comprise: providing an initial substrate; patterning the initial substrate to form a bit line trench, the bit line trench extending along the second direction; forming the initial bit line to fill the bit line trench; after forming the initial bit line, patterning the initial substrate on both sides of the initial bit line to form the active region, the initial substrate under the initial bit line as the substrate; forming the isolation structure on the substrate, the isolation structure filling a region between the active region and the initial bit line.

[0010] In some embodiments, after forming the bit line trench, further comprising: forming a first protective layer on a sidewall of the sub-active region within the bit line trench, and the initial bit line metal layer formed on a surface of the first protective layer; after forming the word line, further comprising: removing the first protective layer to form a first air gap.

[0011] In some embodiments, before forming the initial bit line, further comprising: forming a first isolation layer within the bit line trench, and the first isolation layer between the initial bit line and the substrate.

[0012] In some embodiments, the process steps of forming the first isolation layer and the initial bit line comprise: forming an initial isolation layer within the bit line trench, a top surface of the initial isolation layer lower than a top surface of the active region; removing part of the initial isolation layer to form a groove, the initial isolation layer under the groove as the first isolation layer, and the initial isolation layer between an inner wall of the groove and the sub-active region as the first protective layer; forming the initial bit line to fill the groove, a top surface of the initial bit line higher than a top surface of the first protective layer, and part of the initial bit line in contact with the sub-active region.

[0013] In some embodiments, the sub-active region exposed to the word line trench is subjected to an oxidation process to form the gate dielectric layer.

[0014] In some embodiments, the oxidation process also oxidizes the bit line surface exposed by the word line trench to form an oxide layer.

[0015] In some embodiments, after forming the word line, the oxide layer on the bit line sidewall is removed to form a second air gap as part of the insulating structure.

[0016] In some embodiments, after forming the second air gap, further comprising forming a word line protection layer on the top surface of the word line and filling the word line trench.

[0017] According to some embodiments of the present application, another aspect of the embodiments of the present application further provides a semiconductor structure, comprising: a substrate and a plurality of spaced active regions and an isolation structure between adjacent active regions on the substrate, the active regions extending along a first direction parallel to the substrate surface, and the active regions comprising a plurality of sub-active regions arranged along the first direction, the substrate further having a bit line extending along a second direction parallel to the substrate surface, and the sub-active regions intersecting the bit line; a word line trench extending along a third direction parallel to the substrate surface, the word line trench being located within the sub-active regions, the isolation structure, and the bit line; a gate dielectric layer on the surface of the sub-active regions exposed by the word line trench; a word line on the gate dielectric layer and filling the word line trench, and an insulating structure between the word line and the bit line.

[0018] In some embodiments, the bit line comprises: a bit line metal layer and a bit line contact layer on the surface of the bit line metal layer, stacked in sequence; in a direction perpendicular to the substrate surface, the bottom surface of the word line is lower than or flush with the bottom surface of the bit line contact layer.

[0019] In some embodiments, in a direction perpendicular to the substrate surface, the depth of the word line in the bit line metal layer is less than or equal to 2 / 3 of the total thickness of the bit line metal layer.

[0020] In some embodiments, further comprising: a first isolation layer between the bit line and the substrate; and a first air gap between the bit line metal layer and the sub-active region.

[0021] In some embodiments, the insulating structure comprises a second air gap between the sidewall of the bit line metal layer and the sidewall of the word line.

[0022] In some embodiments, further comprising: a word line protection layer on the top surface of the word line.

[0023] The technical scheme provided by the embodiments of the present application has at least the following advantages: the substrate, the active region, the isolation structure and the initial bit line are provided, the active region, the isolation structure and the initial bit line are patterned to form the word line trench and the bit line, the gate dielectric layer is formed at the bottom of the word line trench, the word line and the insulation structure are formed, the process flow of the manufacturing method of the semiconductor structure is optimized by forming the bit line first and then forming the word line, and the volume of the semiconductor structure is reduced by forming the word line and the bit line with a top surface not higher than the active region. BRIEF DESCRIPTION OF DRAWINGS

[0024] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which will better illustrate certain aspects of the present embodiments, but are not intended to limit the present embodiments unless otherwise specifically indicated, the drawings in the figures are not to scale.

[0025] Figures 1 to 15 The semiconductor structure schematic diagram corresponding to each step of the manufacturing method of the semiconductor structure provided by the embodiments of the present application. DETAILED DESCRIPTION

[0026] The embodiments of the present application provide a manufacturing method of a semiconductor structure and a structure thereof, and the process flow of the manufacturing method of the semiconductor structure is optimized by forming the bit line first and then forming the word line.

[0027] The embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art can understand that in the embodiments of the present application, many technical details are proposed in order to make the reader better understand the present application. However, the technical scheme claimed by the present application can be realized even without these technical details and various changes and modifications based on the following embodiments.

[0028] Reference Figures 1 to 9 A substrate 100, a plurality of spaced active regions 110 on the substrate 100 and an isolation structure 120 between adjacent active regions 110 are provided, the active regions 110 extend along a first direction X parallel to the surface of the substrate 100, and the active regions 110 include a plurality of sub-active regions 11 arranged along the first direction X, the substrate 100 further has an initial bit line 130 extending along a second direction Y parallel to the surface of the substrate 100, and the sub-active regions 11 respectively intersect with the initial bit line 130.

[0029] Specifically, referring to Figure 1 and Figure 2providing an initial substrate 12; patterning the initial substrate 12 to form a bit line trench 140 extending along a second direction Y, in some embodiments, the initial substrate 12 can be patterned by a mask etching method, a mask layer 150 with a pattern shape is formed on the surface of the initial substrate 12, and the initial substrate 12 is etched with the mask layer 150 as a mask to form the bit line trench 140.

[0030] In some embodiments, the material of the initial substrate 12 can be a silicon material, a germanium material, or a compound material such as gallium arsenide, and in other embodiments, the initial substrate 12 can also be an insulating material. It can be understood that the corresponding material can be selected according to the needs.

[0031] Reference is made to Figure 3 forming an initial bit line 130 filling the bit line trench 140 (see Figure 2 ), in some embodiments, the initial bit line 130 includes: an initial bit line metal layer 13 and an initial bit line contact layer 14 stacked in sequence, and in other embodiments, the initial bit line can also be a single-layer structure including only the initial bit line metal layer or the initial bit line contact layer.

[0032] In some embodiments, the material of the initial bit line metal layer 13 can be tungsten metal, and the material of the initial bit line contact layer 14 can be polysilicon.

[0033] Before forming the initial bit line 130, it further includes: forming a first isolation layer 170 in the bit line trench 140 (see Figure 2 ), and the first isolation layer 170 is located between the initial bit line 130 and the substrate 100, the first isolation layer 170 is used to isolate the initial bit line metal layer 13 from directly contacting the substrate 100, to prevent the initial bit line metal layer 13 from ion diffusion and polluting the substrate 100.

[0034] In some embodiments, the material of the first isolation layer 170 can be silicon nitride.

[0035] In some embodiments, the method of forming the first isolation layer 170 includes: forming an initial isolation layer in the bit line trench 140 (see Figure 2 ), the top surface of the initial isolation layer is lower than the top surface of the initial substrate 12; patterning part of the thickness of the initial isolation layer to form a groove, the initial isolation layer directly below the groove as the first isolation layer 170, and the initial isolation layer between the inner wall of the groove and the initial substrate 12 as a first protective layer 180, the first protective layer 180 provides a process basis for the subsequent formation of the first air gap.

[0036] In some embodiments, the method for forming the initial bit line 130 includes: forming the initial bit line 130 filled in the groove, the top surface of the initial bit line 130 is higher than the top surface of the first protective layer 180, and the partial thickness of the initial bit line 130 also contacts the sidewall of the initial substrate 12. It can be understood that the metal material of the initial bit line metal layer 13 may have ion diffusion, and when the initial bit line metal layer 13 directly contacts the initial substrate 12, the initial substrate 12 may be contaminated. By isolating the initial bit line metal layer 13 from the initial substrate 12 through the first protective layer 180, the initial bit line metal layer 13 is prevented from directly contacting the initial substrate 12, thereby reducing the probability of the initial bit line metal layer 13 contaminating the initial substrate 12, and further improving the stability of the semiconductor structure.

[0037] In some embodiments, after the initial bit line 130 is formed, a bit line protective layer 190 is formed on the top surface of the initial bit line 130, and the bit line protective layer 190 is used to protect the initial bit line 130. In other embodiments, the bit line protective layer can not be formed, that is, the top surface of the initial bit line is flush with the top surface of the initial substrate.

[0038] In some embodiments, the material of the bit line protective layer 190 can be the same as the material of the first isolation layer 170, which is a silicon nitride material.

[0039] Reference Figures 4 to 8 After the initial bit line 130 is formed, the initial substrate 12 located on both sides of the initial bit line 130 is patterned to form an active region 110, and the initial substrate 12 located directly below the initial bit line 130 serves as a substrate 100.

[0040] Specifically, referring to Figure 4 A second initial mask layer 200 is formed on the surface of the initial substrate 12. In some embodiments, the second initial mask layer 200 can be a two-layer structure of an etching layer 15 and a pattern layer 16. The material of the etching layer 15 in contact with the surface of the initial substrate 12 can be selected according to the material of the bit line protective layer 190, which is used to protect the bit line protective layer 190 from being etched during etching. The pattern layer 16 is used to provide an etching pattern.

[0041] Reference Figure 5 And Figure 6 , Figure 5 And Figure 6 is along Figure 4 the top-down direction of the semiconductor structure manufacturing method.

[0042] Specifically, the second initial mask layer 200 (refer to Figure 4 ) is patterned to form a second mask layer 210. It should be noted that Figure 5 andFigure 6 The circle in the figure represents a second initial mask layer 200 (refer to Figure 4 ) is interrupted from the circle, finally forming an island-shaped second mask layer 210, which is used as a mask for forming an active region.

[0043] Referring to Figure 7 and Figure 8 , the active region 110 is formed by etching the initial substrate 12, so that the material of the initial substrate 12 can be a semiconductor material such as silicon or germanium, and the material of the active region 110 is the same as that of the initial substrate 12.

[0044] It can be understood that, since the etching layer 15 and the bit line protection layer 190 are made of the same material, the bit line protection layer 190 and the initial bit line 130 below the bit line protection layer 190 will not be etched during the etching process, so that the sub-active region 11 intersecting with the initial bit line 130 is formed.

[0045] In other embodiments, the material of the initial substrate can also be an insulating material, and the method of forming the active region can be to pattern the initial substrate to form an active region recess, and then fill the active region recess with a corresponding material according to requirements to form the active region.

[0046] Referring to Figure 9 , an isolation structure 120 is formed on the substrate 100, which fills the area surrounded by the active region 110 and the initial bit line 130, and is used to isolate adjacent active regions 110 and protect the initial bit line 130.

[0047] In some embodiments, the material of the isolation structure 120 can be an insulating material such as silicon nitride, and a corresponding material can be selected according to requirements.

[0048] In other embodiments, the material of the initial substrate is an insulating material, in which case the method of forming the active region can be to first form an active region recess and then form the active region. Since the material of the initial substrate is an insulating material, there is no need to additionally form an isolation structure, and the initial substrate directly below the bit line structure serves as a substrate, and the remaining initial substrate serves as an isolation structure.

[0049] Referring to Figure 10 , the active region 110, the isolation structure 120, and the initial bit line 130 (refer to Figure 9 ) are patterned to form a word line trench 220 extending in a third direction Z parallel to the surface of the substrate 100, the word line trench 220 being located within the sub-active region 11, the isolation structure 120, and the initial bit line 130, and the remaining initial bit line 130 serving as a bit line 230, and the word line trench 220 provides a process basis for subsequent formation of a word line.

[0050] In some embodiments, the method of forming the word line trench 220 can be mask etching, in the process of forming the word line trench 220, the word line trench 220 penetrates the initial bit line contact layer 14 at least in the direction perpendicular to the surface of the substrate 100, the remaining initial bit line contact layer 14 becomes the bit line contact layer 17, the remaining initial bit line metal layer 13 becomes the bit line metal layer 18, and the bit line contact layer 17 and the bit line metal layer 18 become the bit line 230.

[0051] In some embodiments, the depth of the word line trench 220 in the initial bit line metal layer 13 is less than or equal to 2 / 3 of the total thickness of the initial bit line metal layer 13 (refer to Figure 9 ), it can be understood that the deeper the depth of the word line trench 220, the thinner the thickness of the initial bit line metal layer 13 in the direction perpendicular to the surface of the substrate 100, which will affect the normal operation of the semiconductor structure.

[0052] Referring to Figures 11 to 14 , Figures 11 to 14 is Figure 10 a structural schematic diagram of the cross-section making method along the Y1, Y2, X1 and X2 directions.

[0053] Specifically, referring to Figure 11 and Figure 12 , the gate dielectric layer 240 is formed on the surface of the sub-active region 11 exposed by the word line trench 220, in some embodiments, the method of forming the gate dielectric layer 240 can be to perform oxidation treatment on the sub-active region 11 exposed by the word line trench 220 to form the gate dielectric layer 240; in other embodiments, the method of forming the gate dielectric layer can also be to deposit an oxide layer on the surface of the sub-active region exposed by the word line trench to form the gate dielectric layer, and the gate dielectric layer 240 is used to improve the reliability of the semiconductor structure.

[0054] In the process of oxidation treatment, the surface of the bit line 230 (refer to Figure 10 ) exposed by the word line trench 220 is also subjected to oxidation treatment to form an oxide layer 250, and the oxide layer 250 provides a process basis for the subsequent formation of a second air gap, in other embodiments, the method of forming the oxide layer can also be to deposit an oxide layer on the sidewall of the word line trench to form the oxide layer.

[0055] Referring to Figure 13 and Figure 14 , the word line 260 and the insulating structure 270 are formed, the word line 260 is located on the gate dielectric layer 240 and fills the word line trench 220, and the insulating structure 270 is located between the word line 260 and the bit line 230, and the insulating structure 270 is used to isolate the word line 260 from the bit line 230 to prevent contact between the word line 260 and the bit line 230.

[0056] Specifically, referring to Figure 13 In some embodiments, the thickness of the word line 260 is less than or equal to 2 / 3 of the thickness of the bit line metal layer 18 in a direction perpendicular to the surface of the substrate 100, for example, the thickness of the word line 260 is 1 / 2 of the thickness of the bit line metal layer 18. It can be understood that the smaller the thickness of the word line 260, the smaller the parasitic capacitance between the word line 260 and the bit line metal layer 18, which is beneficial to improve the performance of the semiconductor structure. In other embodiments, the word line can also be in contact with the oxide layer of the sidewall of the bit line contact layer.

[0057] Referring to Figure 14 After forming the word line 260, the method further includes: removing the first protective layer 180 (referring to Figure 13 ) to form a first air gap 280. The dielectric constant of air is about 1. The first air gap 280 is formed to improve the insulation performance between the word line 260 and the bit line metal layer 18, while reducing the parasitic capacitance, thereby improving the stability of the semiconductor structure.

[0058] After forming the word line 260, the method further includes: removing the oxide layer 250 on the sidewall of the bit line 230 to form a second air gap 300. The second air gap 300 is part of the insulation structure 270. Forming the second air gap 300 can improve the insulation performance between the word line 260 and the active region 110, while reducing the parasitic capacitance, thereby improving the stability of the semiconductor structure.

[0059] Referring to Figure 15 In some embodiments, after forming the second air gap 300, the method further includes: forming a word line protective layer 290. The word line protective layer 290 is located on the top surface of the word line 260 and fills the word line trench 220. The word line protective layer 290 is used to protect the word line 260. In other embodiments, the word line protective layer can also not be formed, that is, the word line fills the word line trench.

[0060] The embodiments of the present application provide a semiconductor structure manufacturing method. After forming the active region 110, the isolation structure 120 and the initial bit line 130 on the patterned substrate 100, forming the word line trench 220 and the bit line 230, forming the gate dielectric layer 240 on the bottom surface of the word line trench 220, and forming the word line 260 and the insulation structure 270 on the surface of the gate dielectric layer 240, the step of the semiconductor structure manufacturing process is reduced by forming the bit line 230 first and then forming the word line 260, thereby reducing the process time of producing the semiconductor structure.

[0061] Correspondingly, the embodiments of the present application also provide a semiconductor structure, which will be described in detail below in combination with the drawings. It should be noted that the same or corresponding parts of the semiconductor structure manufacturing method described above can refer to the corresponding description above, which will not be described hereinafter.

[0062] Reference Figure 15 The semiconductor structure includes: a substrate 100 and a plurality of spaced active regions 110 and isolation structures 120 between adjacent active regions 110 on the substrate 100, the active regions 110 extend along a first direction X parallel to the surface of the substrate 100, and the active regions 110 include a plurality of sub-active regions 11 arranged along the first direction X, and the substrate 100 further has a bit line 230 extending along a second direction Y parallel to the surface of the substrate 100, and the sub-active regions 11 intersect the bit line 230; a word line trench 220 extending along a third direction Z parallel to the surface of the substrate 100, the word line trench 220 is located within the sub-active regions 11, the isolation structures 120 and the bit line 230; a gate dielectric layer 240, the gate dielectric layer 240 is located on the surface of the sub-active regions 11 exposed by the word line trench 220; a word line 260 and an insulating structure 270, the word line 260 is located on the gate dielectric layer 240 and fills the word line trench 220, and the insulating structure 270 is located between the word line 260 and the bit line 230, by forming a semiconductor structure in which the word line 260 and the bit line 230 are both located within the isolation structure 120, thereby reducing the volume of the semiconductor structure.

[0063] In some embodiments, the material of the substrate 100 can be the same as the material of the active region 110, both of which can be semiconductor materials such as silicon, germanium, etc., in other embodiments, the material of the substrate 100 can be the same as the material of the isolation structure 120, both of which can be insulating materials such as silicon oxide or silicon nitride, etc., in other embodiments, the material of the substrate 100 can be different from the materials of the active region 110 and the isolation structure 120, it can be understood that the material of the substrate 100 can be selected according to the manufacturing process.

[0064] In some embodiments, the bit line 230 includes: a bit line metal layer 18 and a bit line contact layer 17 on the surface of the bit line metal layer 18 stacked in sequence; in the direction perpendicular to the surface of the substrate 100, the bottom surface of the word line 260 is lower than or flush with the bottom surface of the bit line contact layer 17, by setting the word line 260 within the isolation structure 120, the volume of the semiconductor structure can be reduced.

[0065] When the bottom surface of the word line 260 is lower than the bottom surface of the bit line contact layer 17, in the direction of the surface of the vertical substrate 100, the word line 260 is located at a depth of the bit line metal layer 18 less than or equal to 2 / 3 of the total thickness of the bit line metal layer 18. It can be understood that the depth of the word line 260 in the bit line metal layer 18 is related to the depth of the word line trench 220, the deeper the word line trench 220, the deeper the word line 260 can be located in the bit line metal layer 18. In the plane perpendicular to the surface of the substrate 100, by reducing the thickness of the bit line metal layer 18 in the word line trench 220, the performance of the word line 260 is affected, and the thinner the thickness of the word line 260 located in the bit line metal layer 18, the less the parasitic capacitance between the word line 260 and the bit line 230, thereby improving the performance of the semiconductor structure.

[0066] In some embodiments, the semiconductor structure further comprises: a first isolation layer 170 located between the bit line 230 and the substrate 100; and a first air gap 280 located between the sidewall of the bit line metal layer 18 and the sidewall of the sub-active region 11. It can be understood that when the substrate 100 is a semiconductor material, the first isolation layer 170 is used to isolate the bit line metal layer 18 and the substrate 100, preventing ion diffusion of the bit line metal layer 18 and thereby polluting the substrate 100. When the substrate is an insulating material, it can also not contain the first isolation layer; the first air gap 280 is used to isolate the bit line metal layer 18 and the active region 110, thereby preventing ion diffusion of the bit line metal layer 18 and thereby polluting the active region 110. The first air gap 280 can also isolate the bit line metal layer 18 and the word line 260, thereby improving the insulation between the bit line metal layer 18 and the word line 260, and forming the first air gap 280 can reduce the parasitic capacitance between the bit line metal layer 18 and the active region 110.

[0067] In some embodiments, the insulating structure 270 comprises a second air gap 300 located between the sidewall of the bit line metal layer 18 and the sidewall of the word line 260, and the insulating structure 270 is used to isolate the word line 260 and the bit line 230. The insulating structure 270 further comprises an oxide layer 250, and the insulating performance of the second air gap 300 is better than that of the oxide layer 250. In other embodiments, the insulating structure can only contain an oxide layer or only contain a second air gap.

[0068] In some embodiments, the semiconductor structure further comprises a word line protection layer 290 located on the top surface of the word line 260, and the word line protection layer 290 is used to protect the word line 260. In other embodiments, the semiconductor structure can also only contain a word line, i.e., the top surface of the word line is flush with the isolation structure.

[0069] The embodiment provides a semiconductor structure with the word line 260 and the bit line 230 located in the isolation structure 120, reduces the volume of the semiconductor structure through the bit line 230 located in the isolation structure 120, improves the insulation between the bit line metal layer 18 and the word line 260 by setting the first air gap 280 to isolate the bit line metal layer 18 and the active region 110, improves the insulation between the word line 260 and the bit line 230 by setting the second air gap 300, and reduces the parasitic capacitance between the word line 260 and the bit line 230

[0070] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for realizing the application, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the application. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the application, so the protection scope of the application should be subject to the range defined by the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, along with a plurality of spaced active regions on the substrate and an isolation structure between adjacent active regions. The active regions extend along a first direction parallel to the surface of the substrate, and each active region includes a plurality of sub-active regions arranged along the first direction. The substrate also has an initial bit line extending along a second direction parallel to the surface of the substrate, and the sub-active regions intersect the initial bit line. The active region, the isolation structure, and the initial bit line are graphically represented to form a word line trench extending in a third direction parallel to the substrate surface. The word line trench is located within the sub-active region, the isolation structure, and the initial bit line, with the remaining initial bit line serving as a bit line. A gate dielectric layer is formed, the gate dielectric layer being located on the surface of the sub-active region exposed by the word line trench; A word line and an insulating structure are formed, wherein the word line is located on the gate dielectric layer and fills the word line trench, and the insulating structure is located between the word line and the bit line.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The initial bit line includes: an initial bit line metal layer and an initial bit line contact layer stacked sequentially; in the process step of forming the word line trench, the word line trench penetrates the initial bit line contact layer at least in the direction perpendicular to the substrate surface, the remaining initial bit line contact layer serves as a bit line contact layer, the remaining initial bit line metal layer serves as a bit line metal layer, and the bit line contact layer and the bit line metal layer serve as the bit line.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The depth of the word line trench within the initial bit line metal layer is less than or equal to 2 / 3 of the total thickness of the initial bit line metal layer.

4. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The steps of forming the active region, the isolation structure, and the initial bit line include: Provide initial substrate; The initial substrate is patterned to form bit line trenches that extend along the second direction; Form the initial bit line that fills the bit line trench; After the initial bit line is formed, the initial substrate located on both sides of the initial bit line is patterned to form the active region, and the initial substrate located below the initial bit line is used as the substrate. The isolation structure is formed on the substrate, and the isolation structure fills the region between the active region and the initial bit line.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, After forming the bit line trench, the method further includes: forming a first protective layer on the sidewall of the sub-active region within the bit line trench, wherein the initial bit line metal layer is located on the surface of the first protective layer; after forming the word line, the method further includes: removing the first protective layer to form a first air gap.

6. The method for fabricating a semiconductor structure according to claim 5, characterized in that, Before forming the initial bit line, the method further includes: forming a first isolation layer within the bit line trench, wherein the first isolation layer is located between the initial bit line and the substrate.

7. The method for fabricating a semiconductor structure according to claim 6, characterized in that, The process steps for forming the first isolation layer and the initial bit line include: An initial isolation layer is formed within the bit line trench, wherein the top surface of the initial isolation layer is lower than the top surface of the active region; A portion of the initial isolation layer is removed to form a groove, the initial isolation layer below the groove serves as the first isolation layer, and the initial isolation layer between the inner wall of the groove and the sub-active region serves as the first protective layer. The initial bit line is formed to fill the groove, the top surface of the initial bit line is higher than the top surface of the first protective layer, and a portion of the initial bit line contacts the sub-active region.

8. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The sub-active region exposed by the word line trench is oxidized to form the gate dielectric layer.

9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, During the oxidation process, the surface of the bit line exposed by the word line groove is also oxidized to form an oxide layer.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, After the word line is formed, the oxide layer located on the sidewall of the word line is removed to form a second air gap, which is part of the insulation structure.

11. The method for fabricating a semiconductor structure according to claim 10, characterized in that, After forming the second air gap, the method further includes: forming a character line protection layer, the character line protection layer being located on the top surface of the character line and filling the character line groove.

12. A semiconductor structure, characterized in that, include: The substrate and a plurality of spaced active regions on the substrate and an isolation structure between adjacent active regions, the active regions extending along a first direction parallel to the surface of the substrate, and the active regions including a plurality of sub-active regions arranged along the first direction, the substrate also having a bit line extending along a second direction parallel to the surface of the substrate, and the sub-active regions intersecting the bit line; A word line trench extending in a third direction parallel to the surface of the substrate, the word line trench being located within the sub-active region, the isolation structure, and the bit line; A gate dielectric layer, the gate dielectric layer being located on the surface of the sub-active region exposed by the word line trench; The word lines and insulating structures are provided, wherein the word lines are located on the gate dielectric layer and fill the word line trenches, and the insulating structures are located between the word lines and the bit lines.

13. The semiconductor structure according to claim 12, characterized in that, The bit line includes: a bit line metal layer stacked sequentially and a bit line contact layer located on the surface of the bit line metal layer; in a direction perpendicular to the substrate surface, the bottom surface of the word line is lower than or flush with the bottom surface of the bit line contact layer.

14. The semiconductor structure according to claim 13, characterized in that, In a direction perpendicular to the substrate surface, the word line is located at a depth in the bit line metal layer that is less than or equal to 2 / 3 of the total thickness of the bit line metal layer.

15. The semiconductor structure according to claim 13, characterized in that, Also includes: A first isolation layer is located between the bit line and the substrate; A first air gap is located between the bit line metal layer and the sub-active region.

16. The semiconductor structure according to claim 13, characterized in that, The insulating structure includes a second air gap located between the bit line metal layer sidewall and the word line sidewall.

17. The semiconductor structure according to claim 12, characterized in that, Also includes: A character line protective layer, wherein the character line protective layer is located on the top surface of the character line.

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