A data operation method and device

Abstract

The application provides a data operation method and device, relates to the technical field of communication, and is used for reducing the delay of MPI operation and improving the execution efficiency of MPI. The method is applied to a network card, the network card is coupled with a memory through a bus, and the method comprises the following steps: receiving a first message, wherein the first message comprises operation instruction information and first data; determining, according to the operation instruction information, that data operation needs to be performed on the first data; obtaining second data from the memory, wherein the second data is local data of the data operation in the MPI operation; and performing data operation on the first data and the second data to obtain a first operation result.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a data processing method and apparatus. Background Technology

[0002] With the rapid development of high-performance computing (HPC) and artificial intelligence (AI) applications, the execution efficiency of message passing interface (MPI) communication functions is becoming increasingly important. MPI communication functions include reduce functions such as MPI_reduce and MPI_allreduce, with MPI reduce functions accounting for a large proportion (approximately 40%) in MPI applications. Improving the execution efficiency of MPI reduce functions will significantly improve the runtime efficiency of MPI applications. MPI reduce functions can be decomposed into three parts: computation, synchronization, and communication. This paper will optimize the computation part of the MPI reduce function.

[0003] In existing technologies, the computational portion of MPI operations is typically offloaded by the send queue (SQ) task of the server's external network interface card. Specifically, for example... Figure 1 As shown, the method includes: S1. The network card writes data A1 from the network packet into the dynamic random access memory (DRAM); S2. The network card schedules a task SQ. When the task of the selected SQ is to perform a reduce operation on the data A1, the network card reads data A1 from the packet in the DRAM; S3. The network card reads local data A2 from the DRAM; S4. The network card completes the operation on data A1 and data A2, and writes the result into the DRAM.

[0004] In the above method, the network card can only perform the data operation when it is scheduled to the SQ corresponding to the computing task. When the network scale is larger, the number of SQs corresponding to the network card is more. At this time, the latency of the network card scheduling to the SQ corresponding to the computing task is also larger, resulting in a larger latency of the MPI operation. Summary of the Invention

[0005] This application provides a data processing method and apparatus for reducing the latency of MPI operations and improving the execution efficiency of MPI operations.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] In a first aspect, a data operation method in MPI operation is provided, applied to a network card coupled with a memory through a bus. The method comprises: receiving a first message, which can be sent by another server performing message passing interface (MPI) operation in a network, and the first message comprises operation indication information and first data; determining, according to the operation indication information, a data operation of the MPI operation needed to be performed on the first data; obtaining second data from the memory, which is local data of the data operation in the MPI operation; completing the data operation of the first data and the second data in the MPI operation (such as addition or multiplication, etc.), to obtain a first operation result; and further, writing the first operation result into the memory.

[0008] In the above technical solution, when the network card receives and obtains the operation indication information and the first data in the first message, the network card can determine, according to the operation indication information, the data operation of the MPI operation needed to be performed on the first data, and then directly obtains the local data (i.e. the second data) of the data operation in the MPI operation from the memory, and completes the data operation of the first data and the second data to obtain the first operation result. Compared with the prior art, the network card does not need to write the first data into the memory, but directly obtains the second data when obtaining the first data, i.e. performs on-the-fly calculation on the first data and the second data, reduces the read and write times of the memory, thereby reducing the delay of the MPI operation and improving the execution efficiency of the MPI.

[0009] In a possible implementation manner of the first aspect, the method comprises: receiving a first message, which comprises first data; when the first message carries operation indication information, determining a data operation of a message passing interface (MPI) operation needed to be performed on the first data, and obtaining second data from the memory, which is local data of the operation of the MPI operation; and completing the MPI operation of the first data and the second data to obtain a first operation result. It should be understood that the scheme can further comprise: writing the first operation result into the memory.

[0010] It should be understood that the operation indication information can be carried in the message header of the first message, for example, the message header of the existing message is extended, and the operation indication information is carried in the message header obtained by the extension.

[0011] In a possible implementation manner of the first aspect, the first message further comprises a storage address of the second data, and obtaining the second data from the memory comprises: reading the second data from the memory according to the storage address. Further, writing the first operation result into the memory comprises: storing the first operation result on the storage location where the second data is located to overwrite the second data according to the storage address of the second data. In the above possible implementation manner, useless data can be avoided from occupying the storage space in the memory, thereby improving the utilization rate of the memory.

[0012] In a possible implementation manner of the first aspect, the network card, the memory and the bus are integrated in a chip system SoC. In the possible implementation manner, by integrating the network card, the memory and the bus in the SoC, the end-to-end transmission delay can be reduced, and the execution efficiency of the data operation in the MPI operation is further improved.

[0013] In a possible implementation manner of the first aspect, the operation indication information includes an operation type and a data type. In the possible implementation manner, the operation type and the data type can be used to determine that the first data needs to perform the data operation of the MPI operation, so that when the network card obtains the information, the first data does not need to be written into the memory, but the second data is directly obtained, the data operation of the first data and the second data is implemented, the read and write times of the memory are reduced, the delay of the MPI operation is reduced, and the execution efficiency of the MPI is improved.

[0014] In a possible implementation manner of the first aspect, the operation indication information is carried in a packet header of the first packet. In the possible implementation manner, a simple and effective manner of carrying the operation indication information is provided.

[0015] In a possible implementation manner of the first aspect, the MPI operation includes an MPI reduce operation or an MPI allreduce operation. In the possible implementation manner, the delay of the MPI reduce operation or the MPI allreduce operation can be reduced, and the execution efficiency of the MPI reduce operation or the MPI allreduce operation is improved.

[0016] In a possible implementation manner of the first aspect, the network card is further coupled with the processor through the bus, and the method further includes: sending notification information to the processor, the notification information being used to indicate that the data operation is completed. In the possible implementation manner, by sending the notification information to the processor, the state of the MPI operation recorded by the processor can be consistent with the actual state of the MPI operation, so that the order and efficiency of the MPI operation are ensured.

[0017] In a second aspect, a data operation apparatus is provided. The apparatus is a network card or a chip built in the network card. The network card is coupled with a memory through a bus. The apparatus comprises: a receiving unit configured to receive a first packet from a network; a processing unit configured to parse the first packet to obtain operation instruction information and first data included in the first packet, the operation instruction information being used to indicate that a data operation of a message passing interface (MPI) operation is needed on the first data; and an obtaining unit configured to obtain second data from the memory, the second data being local data of the data operation in the MPI operation. The processing unit is further configured to complete the data operation of the first data and the second data to obtain a first operation result. Further, the apparatus further comprises a writing unit configured to write the first operation result into the memory.

[0018] In a possible implementation of the second aspect, the apparatus comprises: a receiving unit configured to receive a first packet, the first packet comprising first data; a processing unit configured to determine, when the first packet carries operation instruction information, that a data operation of an MPI operation is needed on the first data; an obtaining unit configured to obtain second data from the memory, the second data being local data of the operation in the MPI operation; and the processing unit is further configured to complete the MPI operation of the first data and the second data to obtain a first operation result. It should be understood that the scheme can further comprise writing the first operation result into the memory. It should be understood that the operation instruction information can be carried in a packet header of the first packet, for example, the operation instruction information is carried in an extended packet header of an existing packet header.

[0019] In a possible implementation of the second aspect, the first packet further comprises a storage address of the second data. The obtaining unit is further configured to read the second data from the memory according to the storage address. Further, the writing unit is further configured to store the first operation result on a storage location of the second data to replace the second data according to the storage address of the second data.

[0020] In a possible implementation of the second aspect, the network card, the memory and the bus are integrated in a system on chip (SoC).

[0021] In a possible implementation of the second aspect, the operation instruction information comprises an operation type and a data type.

[0022] In a possible implementation of the second aspect, the operation instruction information is carried in a packet header of the first packet.

[0023] In a possible implementation of the second aspect, the MPI operation corresponding to the first data comprises an MPI reduce operation or an MPI allreduce operation.

[0024] In a possible implementation manner of the second aspect, the network card is further coupled with the processor through a bus, and the apparatus further includes a sending unit configured to send notification information to the processor, the notification information being used to indicate that the data operation is completed.

[0025] In a third aspect, a data operation apparatus is provided. The apparatus is a network card or a chip built in the network card. The network card is coupled with a memory through a bus. The memory stores codes and data. The network card runs the codes in the memory so that the apparatus performs the data operation method provided in the first aspect or any possible implementation manner of the first aspect.

[0026] In another aspect of the present application, a computer readable storage medium is provided. The computer readable storage medium stores instructions. When the instructions are run on a computer, the computer is caused to perform the data operation method provided in the first aspect or any possible implementation manner of the first aspect.

[0027] In another aspect of the present application, a computer program product is provided. When the computer program product is run on a device, the device is caused to perform the data operation method provided in the first aspect or any possible implementation manner of the first aspect.

[0028] It can be understood that any data operation apparatus, computer storage medium or computer program product provided above are used to perform the corresponding method provided above, and thus the beneficial effects achieved by the data operation apparatus, computer storage medium or computer program product can refer to the beneficial effects of the corresponding method provided above, which will not be described herein again. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 An execution schematic diagram of an MPI operation;

[0030] Figure 2 An execution schematic diagram of an MPI operation provided by an embodiment of the present application;

[0031] Figure 3a A structure schematic diagram of a server provided by an embodiment of the present application;

[0032] Figure 3b A structure schematic diagram of another server provided by an embodiment of the present application;

[0033] Figure 4 A flow schematic diagram of a data operation method provided by an embodiment of the present application;

[0034] Figure 5 A flow schematic diagram of another data operation method provided by an embodiment of the present application;

[0035] Figure 6 An execution schematic diagram of an MPI operation provided by an embodiment of the present application;

[0036] Figure 7 A structural schematic diagram of a data operation device provided by an embodiment of the present application is shown in FIG. 1.

[0037] Figure 8 A structural schematic diagram of another data operation device provided by an embodiment of the present application is shown in FIG. 2. DETAILED DESCRIPTION

[0038] In the present application, “at least one” means one or more, and “multiple” means two or more. “And / or” describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character “ / ” generally represents an “or” relationship between the associated objects before and after it. “At least one of the following” or similar expressions means any combination of these items, including any combination of single item or multiple items. For example, at least one of a, b, or c can represent a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or multiple. In addition, the present application uses “first”, “second”, and the like to distinguish the same items or similar items with basically the same function and effect. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and do not limit the order. Those skilled in the art can understand that “first”, “second”, and the like do not limit the quantity and execution order.

[0039] It should be noted that in the present application, “exemplary” or “for example” is used to represent an example, illustration, or description. Any embodiment or design scheme described as “exemplary” or “for example” in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the use of “exemplary” or “for example” is intended to present the relevant concept in a specific manner.

[0040] Before introducing the embodiments of the present application, first, the related technical terms involved in the embodiments of the present application are introduced and described.

[0041] Message passing interface (MPI) is a message passing programming interface, which provides a multi-language function library for implementing a series of MPI interfaces. The MPI standard defines a set of functions, so that the application program can send messages from one MPI process to another MPI process.

[0042] MPI collective communication can refer to communication through MPI to implement different functions, which can be referred to as MPI collective communication functions, including reduce function types such as MPI reduce and MPI allreduce. That is, MPI reduce and MPI allreduce are both defined standard collective communication functions, and the difference between the two functions is that the final result of MPI Reduce is that a process node in the communication domain obtains the final calculation result, and MPI Allreduce is that each process node in the communication domain can obtain the final calculation result.

[0043] Among them, the MPI collective communication can also be commonly referred to as an MPI operation, which can generally be divided into three parts, namely synchronization, calculation and communication. The synchronization can refer to the synchronization and information interaction between different operation processes, or the synchronization between different step tasks in the same process; the calculation can refer to the specified operation of the input data in each process; and the communication can refer to the data transmission between different nodes in the communication domain. For ease of description, the MPI collective communication is collectively referred to as an MPI operation in this paper.

[0044] For example, as shown in Figure 2 , assuming that an MPI_allreduce operation is performed in a communication domain with a networking scale of 8 nodes (denoted as P0 to P7 respectively), and a recursive doubling algorithm is used, then each node in the communication domain only needs to send and receive communication 3 times, and when all nodes complete 3 times of sending and receiving communication, the MPI_allreduce operation is completed. The specific implementation steps can include the following steps S01 to S03.

[0045] S01. The nodes with a distance of 1 exchange 1 / 8 data with each other and perform reduction operation, and the result is that each node obtains 1 / 4 reduction result of the data. For example, as shown in Table 1 below, P0 and P1 exchange data A and B, P2 and P3 exchange data C and D, P4 and P5 exchange data E and F, and P6 and P7 exchange data G and H, and each node performs addition operation, then P0 and P1 obtain A+B, P2 and P3 obtain C+D, P4 and P5 obtain E+F, and P6 and P7 obtain G+H.

[0046] S02. Nodes with distance 2 exchange 1 / 4 data with each other and perform reduction operation, and each node gets 1 / 2 reduction result of data. For example, as shown in Table 1 below, P0 and P2 exchange data A+B and C+D with each other, and P1 and P3 exchange data C+D and A+B with each other, P4 and P6 exchange data E+F and G+H with each other, and P5 and P7 exchange data G+H and E+F with each other, and each node performs addition operation, then P0 to P3 all get A+B+C+D, and P4 to P7 all get E+F+G+H.

[0047] S03. Nodes with distance 4 exchange 1 / 2 data with each other and perform reduction operation, and each node gets reduction result of all data. For example, as shown in Table 1 below, P0 and P4 exchange data A+B+C+D and E+F+G+H with each other, P1 and P5 exchange data A+B+C+D and E+F+G+H with each other, P2 and P6 exchange data A+B+C+D and E+F+G+H with each other, and P3 and P7 exchange data A+B+C+D and E+F+G+H with each other, and each node performs addition operation, then P0 to P7 all get A+B+C+D+E+F+G+H.

[0048] Table 1

[0049]

[0050] Figure 3a and Figure 3b The structure schematic diagram of two exemplary servers provided by the embodiments of the present application can include a memory 301, a processor 302, a network card 303 and a bus 304, the memory 301, the processor 302 and the network card 303 are connected with each other through the bus 304.

[0051] The memory 301 can be configured to store data, software programs and modules, and mainly include a program storage area and a data storage area. The program storage area can store an operating system, at least one application required by a function, and the like. The data storage area can store data created during use of the device, and the like. For example, the operating system can include a Linux operating system, a Unix operating system, or a Window operating system, and the like. The at least one application (application, APP) required by a function can include an artificial intelligence (artificial intelligence, AI) related APP, a high performance computing (high performance computing, HPC) related APP, a deep learning (deep learning, DL) related APP, or a computer graphics (computer graphics, CG) related APP, and the like. In a possible example, the memory 301 includes, but is not limited to, a static random access memory (static RAM, SRAM), a dynamic random access memory (dynamic RAM, DRAM), a synchronous dynamic random access memory (synchronous DRAM, SDRAM), or a high-speed random access memory, and the like. Further, the memory 301 can also include other non-volatile memories, such as at least one magnetic disk storage device, a flash memory device, or other volatile solid-state memory devices.

[0052] In addition, the processor 302 is configured to control and manage the operation of the server, such as by running or executing software programs and / or modules stored in the memory 301, and calling data stored in the memory 301, performing various functions of the server and processing data. In a possible example, the processor 302 includes, but is not limited to, a central processing unit (central processing unit, CPU), a network processing unit (network processing unit, NPU), a graphics processing unit (graphics processing unit, GPU), an application specific integrated circuit (application specific integrated circuit, ASIC), a field programmable gate array (field programmable gate array, FPGA) or other programmable logic device, transistor logic device, logic circuit, or any combination thereof. It can implement or execute various exemplary logic blocks, modules and circuits described in combination with the disclosure. The processor 302 can also be a combination of computing functions, such as one or more microprocessor combinations, combinations of digital signal processors and microprocessors, and the like.

[0053] The network card 303 can be used to implement the communication between the server and an external network. For example, the network card 303 can be a smart network interface card (smart NIC). In some possible embodiments, the network card 303 can support a remote direct memory access (RDMA) mode. For example, the network card 303 can receive a packet from a network through the RDMA mode, and send a packet to another device in the network through the RDMA mode. The network card 303 can store the received packet in the memory 301 through the RDMA mode.

[0054] The bus 304 can include an extended industry standard architecture (EISA) bus, a peripheral component interconnect express (PCIe) bus, or the like. The bus 304 can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, Figure 3a and Figure 3b Only one thick line is used to represent the bus in the figure, but it does not mean that there is only one bus or only one type of bus.

[0055] In the embodiments of the present application, as shown in Figure 3a The memory 301, the processor 301, and the network card 303 can be integrated in a system of chip (SoC) of the server. Alternatively, as shown in Figure 3b The memory 301 and the processor 301 can be integrated in a system of chip (SoC) of the server, and the network card 303 is an external network card connected to the SoC through an external bus.

[0056] Figure 4 A flowchart of a data operation method provided in the embodiments of the present application is shown. The method can be executed by the network card in the server provided above, and the method includes the following steps.

[0057] S401: The network card receives a first packet, the first packet includes operation instruction information and first data, and determines, according to the operation instruction information, that an MPI operation needs to be performed on the first data.

[0058] The server can be any one of a plurality of servers in a communication domain, which can collectively perform an MPI operation. The plurality of servers can send and receive messages to each other via a network, and the messages can include data for data operation in the MPI operation. For example, the plurality of servers include a first server and a second server, the server can be the first server, the server can receive a first message sent by the second server, and the server can send a second message to the second server. The first message and the second message can be messages of the same format, and only the data included in the messages is different. Hereinafter, the first message is taken as an example for description.

[0059] In addition, the first message can be a message based on a RDMA over Converged Ethernet (RoCE) protocol. The first message can include a message header and a payload, the operation indication information can be carried in the message header of the first message, and the first data can be carried in the payload of the first message. For example, based on an existing RoCE protocol message, an extension message header is added, and the operation indication information is carried in the extension message header. For example, 4 bits of reduce_eth are added in the standard RDMA transport header field, 1 bit of which can be used to indicate a specific data type reduce_type (for example, the data type can include int8, int16, int32, uint8, uint16, uint32, FP16, or FP32), and the other 1 bit is used to indicate a specific operation type reduce_code (for example, the operation type includes max, min, or sum), and the remaining 2 bits can be reserved. Correspondingly, when the operation indication information is carried in the extension message header, the interface between the software and the hardware based on RDMA is also increased to a corresponding write read (WR) type for reading or writing the extension message header.

[0060] Further, the MPI operation corresponding to the first data can be any MPI operation including data operation, for example, the MPI operation can be an MPI reduce operation or an MPI allreduce operation.

[0061] Optionally, the operation indication information can include an operation type and a data type of the data operation in the MPI operation, for example, the operation type can be addition, subtraction, or multiplication, and the data type can be half-precision floating point number, single-precision floating point number, double-precision floating point number, or integer. The specific operation type and data type, and the related description of the above MPI operation can be referred to the description in the related art, and the embodiments of the present application are not described herein.

[0062] Specifically, when the server is performing the MPI operation, a processor (e.g., a CPU) in the server can send a data operation task to the network card. Subsequently, the network card of the server can receive a first packet sent from another server in the network, and the network card can parse the first packet to obtain operation indication information and first data included in the first packet. When the server parses the operation indication information, the network card can determine, according to the operation indication information, that the data operation in the MPI operation needs to be performed on the first data. For example, the operation indication information includes an operation type and a data type of the MPI reduce operation, and the network card can determine, according to the operation type and the data type, that the data operation of the MPI reduce operation needs to be performed on the first data.

[0063] S402: The network card obtains second data from the memory.

[0064] The memory can include an internal memory, which can be a dynamic random access memory (DRAM). The second data can be local data stored in the DRAM for the data operation of the MPI operation. The data type of the second data can be the same as the data type of the first data, for example, the data type of the first data and the data type of the second data are both indicated by the operation indication information in the first packet.

[0065] In addition, the storage address corresponding to the second data can be carried in the first packet. Specifically, after the network card receives the first packet and parses the first packet, the network card can obtain the storage address of the second data from the first packet, so that the network card can obtain the second data from the memory of the server based on the storage address.

[0066] S403: The network card completes the data operation of the first data and the second data to obtain a first operation result.

[0067] When the network card obtains the first data and the second data, the network card can perform the data operation on the first data and the second data based on the operation indication information to obtain a first operation result. For example, the operation type indicated by the operation indication information is addition and the data type is floating point number, and the network card can add the first data and the second data based on the addition rule corresponding to the floating point number to obtain the first operation result; or the operation type indicated by the operation indication information is multiplication and the data type is floating point number, and the network card can multiply the first data and the second data based on the multiplication rule corresponding to the floating point number to obtain the first operation result.

[0068] Further, as shown in FIG. 4, after S403, the method further includes S404. Figure 5

[0069] ​S404: The network card stores the first operation result in the memory.

[0070] Specifically, when the network card obtains the first operation result, the network card can store the first operation result in the memory of the server, for example, the network card stores the first operation result in the DRAM included in the memory. Optionally, the storage address of the first operation result can be the same as the storage address of the second data, that is, the network card can store the first operation result in the storage position of the second data according to the storage address of the second data to cover the second data.

[0071] Optionally, as shown in S404, the method further includes S405. Figure 5

[0072] S405: The network card sends notification information to the processor, and the notification information is used to indicate that the data operation is completed.

[0073] Specifically, after the network card stores the first operation result in the memory, the network card can send notification information to the processor, and the notification information is used to indicate that the data operation is completed. When the processor receives the communication information, the processor can determine that the data operation is completed, thereby synchronizing the related state information of the MPI operation to ensure that the actual state of the MPI operation is consistent with the recorded state. Optionally, the processor can also send the next task to the network card to make the network card continue to execute the corresponding task.

[0074] Further, the processor can divide the data operation in the MPI operation into a plurality of data operation tasks, and send the plurality of data operation tasks to the network card in the order of the plurality of data operation tasks, that is, after a previous data operation task is completed, the next data operation task is sent to the network card, until the plurality of data operation tasks are all completed. For each data operation task in the plurality of data operation tasks, the network card can execute according to the method provided above.

[0075] For example, for the first data operation task in the plurality of data operation tasks, Figure 2 ​As shown in the MPI operation, the data operation in the MPI operation can include three data operation tasks. Taking the server as P0 for example, the network card can complete the MPI operation by performing three data operations in sequence. Specifically, first, the processor sends the network card a task of data operation A+B, the network card performs A+B operation according to S401-S405 and reports; second, the processor sends the network card a task of data operation A+B+C+D, the network card performs A+B+C+D operation according to S401-S405 and reports; finally, the processor sends the network card a task of data operation A+B+C+D+E+F+G+H, the network card performs A+B+C+D+E+F+G+H operation according to S401-S405 and reports.

[0076] As shown in the MPI operation, the data operation in the MPI operation can include three data operation tasks. Taking the server as P0 for example, the network card can complete the MPI operation by performing three data operations in sequence. Specifically, first, the processor sends the network card a task of data operation A+B, the network card performs A+B operation according to S401-S405 and reports; second, the processor sends the network card a task of data operation A+B+C+D, the network card performs A+B+C+D operation according to S401-S405 and reports; finally, the processor sends the network card a task of data operation A+B+C+D+E+F+G+H, the network card performs A+B+C+D+E+F+G+H operation according to S401-S405 and reports. Figure 6 As shown in the MPI operation, the data operation in the MPI operation can include three data operation tasks. Taking the server as P0 for example, the network card can complete the MPI operation by performing three data operations in sequence. Specifically, first, the processor sends the network card a task of data operation A+B, the network card performs A+B operation according to S401-S405 and reports; second, the processor sends the network card a task of data operation A+B+C+D, the network card performs A+B+C+D operation according to S401-S405 and reports; finally, the processor sends the network card a task of data operation A+B+C+D+E+F+G+H, the network card performs A+B+C+D+E+F+G+H operation according to S401-S405 and reports. Figure 6 As shown in the MPI operation, the data operation in the MPI operation can include three data operation tasks. Taking the server as P0 for example, the network card can complete the MPI operation by performing three data operations in sequence. Specifically, first, the processor sends the network card a task of data operation A+B, the network card performs A+B operation according to S401-S405 and reports; second, the processor sends the network card a task of data operation A+B+C+D, the network card performs A+B+C+D operation according to S401-S405 and reports; finally, the processor sends the network card a task of data operation A+B+C+D+E+F+G+H, the network card performs A+B+C+D+E+F+G+H operation according to S401-S405 and reports. Figure 6The second data is denoted as A1, and the first operation result is denoted as R1. It should be understood that after receiving the RDMA packet from the network, a local RQ_WQE needs to be consumed, which indicates a piece of local DDR space. After receiving the first packet, it is determined that the MPI operation needs to be performed on the first data based on the operation indication information carried in the extended packet header, and therefore, after obtaining the first data, the on-the-fly operation is first performed on the first data. After obtaining the calculation result, the calculation result is written into the memory space indicated by the RQ_WQE. The subsequent CPU can obtain the corresponding calculation result from the corresponding memory space.

[0077] In the above execution process, from the perspective of the CPU, the CPU does not perceive the entire calculation process, and only processes the reported interrupt after the calculation is completed, thereby greatly reducing the operating system (OS) noise of the CPU and improving the execution efficiency of the CPU. The entire process only needs one DDR write and one DDR read, and the entire delay includes the read DDR delay, the RDMA network card processing data calculation delay, and one DDR write operation.

[0078] In the embodiment of the present application, when the network card receives the first packet to obtain the operation indication information and the first data in the first packet, the network card can directly obtain the second data from the memory, and complete the data operation of the first data and the second data according to the operation indication information to obtain the first operation result. Compared with the prior art, the network card does not need to write the first data into the memory, but directly obtains the second data when the first data is obtained, that is, the on-the-fly calculation is performed on the first data and the second data, thereby reducing the read and write times of the memory, reducing the delay of the MPI operation, and improving the execution efficiency of the MPI. In addition, when the network card, the processor and the memory in the server are integrated in the SoC of the server, the end-to-end transmission delay can also be reduced, and the execution efficiency of the MPI operation is further improved.

[0079] The above mainly introduces the data operation method in the MPI operation provided by the embodiment of the present application from the perspective of the server. It can be understood that the server includes the hardware structure and / or software module corresponding to the execution of each function in order to realize the above functions. Those skilled in the art should easily realize that the network elements and algorithm steps of each example described in combination with the embodiments disclosed in the present text can be realized in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0080] The embodiments of the present application can divide the functional modules of the data operation device in the MPI operation according to the above method examples. For example, each functional module can be divided according to each function, or two or more functions can be integrated in one processing module. The integrated module can be realized in the form of hardware or in the form of a software functional module. It should be noted that the division of the modules in the embodiments of the present application is illustrative, and is only a logical functional division. In actual implementation, another division manner can be used.

[0081] In the case of dividing each functional module according to each function, Figure 7 A possible structure schematic diagram of the data operation device involved in the above embodiments is shown. The device is a network card or a chip built in the network card. The network card is coupled with a memory through a bus. The device includes a receiving unit 501, a processing unit 502 and an obtaining unit 503. The receiving unit 501 is configured to support the device to receive a first message from a network. The processing unit 502 is configured to support the device to parse the first message to obtain operation instruction information and first data included in the first message. The operation instruction information is used to indicate that the MPI operation of the data operation is needed for the first data. The obtaining unit 503 is configured to support the device to obtain second data from the memory. The second data is local data of the data operation in the MPI operation. The processing unit 502 is further configured to support the device to complete the data operation of the first data and the second data in the MPI operation to obtain a first operation result. Further, the device further includes a writing unit 504 and a sending unit 505. The writing unit 504 is configured to support the device to write the first operation result into the memory. The sending unit 505 is configured to support the device to send notification information to a processor. The notification information is used to indicate that the data operation is completed.

[0082] It should be noted that all related contents of each step involved in the above method embodiments can be cited to the functional description of the corresponding functional module, which will not be repeated here.

[0083] On the basis of the hardware implementation, the processing unit 502 and the writing unit 504 in the present application can be part of the functions of the processor of the device. The receiving unit 501, the obtaining unit 503 and the sending unit 505 can be a set of transceiver functions of the device. The transceiver can generally include a transmitter and a receiver. The specific transceiver can also be referred to as a communication interface.

[0084] Figure 8Fig. 8 shows another possible structure of the data processing apparatus involved in the above embodiments, a network card or a chip built in the network card, which is coupled with a memory through a bus. The apparatus includes a processor 602 and a communication interface 603. The processor 602 is configured to control and manage actions of the apparatus, for example, the processor 602 can support the apparatus to perform S401-S405 in the above embodiments and / or other processes of the technologies described herein through the communication interface 603. In addition, the apparatus can further include a memory 601 and a bus 604, the processor 602, the communication interface 603 and the memory 601 are connected with each other through the bus 604; the communication interface 603 is configured to support the apparatus to communicate; and the memory 601 is configured to store program codes and data of the apparatus.

[0085] The processor 602 can be a central processing unit, a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array, or other programmable logic device, transistor logic device, hardware component, or any combination thereof. It can implement or execute the various exemplary logical blocks, modules and circuits described in connection with the disclosure. The processor can also be a combination of computing functions, such as one or more microprocessor combinations, digital signal processor and microprocessor combinations, etc. The bus 604 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For the sake of representation, Figure 8 Only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0086] In another embodiment of the present application, a readable storage medium is also provided, which stores computer execution instructions. When a device (which can be a single chip microcomputer, a chip, etc.) executes the steps of the network card in the method provided by the above method embodiments, the aforementioned readable storage medium can include a U disk, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk, and various media that can store program codes.

[0087] In another embodiment of the present application, a computer program product is also provided, which includes computer execution instructions stored in a computer readable storage medium. When at least one processor of a device can read the computer execution instructions from the computer readable storage medium, the at least one processor executes the computer execution instructions to make the device perform the steps of the network card in the method provided by the above method embodiments.

[0088] Finally, it should be noted that the above-described embodiments are merely possible implementations of the present application, but the present application is not limited to this, and any changes or substitutions within the technical scope disclosed in the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A data processing method, characterized by, Applied to a network card, the network card is coupled with a memory through a bus, and the method comprises: receiving a first message, the first message comprising operation indication information, first data and a storage address of second data; determining, according to the operation indication information, that data operation of a message passing interface (MPI) operation is required on the first data; obtaining, according to the storage address of the second data, the second data from the memory, the second data being local data of the data operation in the MPI operation; completing data operation of the first data and the second data in the MPI operation to obtain a first operation result; storing the first operation result on a storage location where the second data is located according to the storage address of the second data to overwrite the second data.

2. The method of claim 1, wherein, The network card, the memory and the bus are integrated in a system on chip (SoC).

3. The method according to claim 1 or 2, characterized in that, The operation indication information comprises an operation type and a data type.

4. The method according to claim 1 or 2, characterized in that, The operation indication information is carried in a message header of the first message.

5. The method according to claim 1 or 2, characterized in that, The MPI operation comprises an MPI_reduce operation or an MPI_allreduce operation.

6. The method of claim 1 or 2, wherein, The network card is further coupled with a processor through the bus, and the method further comprises: sending notification information to the processor, the notification information being used for indicating completion of the data operation.

7. A data processing apparatus, characterized by comprising: The device is a network card or a chip built in the network card, the network card is coupled with a memory through a bus, and the device comprises: a receiving unit configured to receive a first message, the first message comprising operation indication information, first data and a storage address of second data; a processing unit configured to determine, according to the operation indication information, that data operation of a message passing interface (MPI) operation is required on the first data; an obtaining unit configured to obtain, according to the storage address of the second data, the second data from the memory, the second data being local data of the data operation in the MPI operation; the processing unit is further configured to complete data operation of the first data and the second data in the MPI operation to obtain a first operation result; a writing unit configured to store the first operation result on a storage location where the second data is located according to the storage address of the second data to overwrite the second data.

8. The apparatus of claim 7, wherein, The network card, the memory and the bus are integrated in a system on chip (SoC).

9. The apparatus of claim 7 or 8, wherein, The operation indication information comprises an operation type and a data type.

10. The apparatus of claim 7 or 8, wherein, The operation indication information is carried in a message header of the first message.

11. The apparatus of claim 7 or 8, wherein, The MPI operation comprises an MPI_reduce operation or an MPI_allreduce operation.

12. The apparatus of claim 7 or 8, wherein, The network card is further coupled with a processor through the bus, and the device further comprises: a sending unit configured to send notification information to the processor, the notification information being used for indicating completion of the data operation.

13. A data processing apparatus, characterized by comprising: The device is a network card or a chip built in the network card, the network card is coupled with a memory through a bus, and the memory stores codes and data, and the network card runs the codes in the memory to enable the device to execute the data operation method in any one of claims 1-6.

14. A computer-readable storage medium, characterized in that, The computer readable storage medium stores instructions which, when executed on a computer, cause the computer to perform the data operation method of any one of claims 1-6.

15. A computer program product, characterised in that, The computer program product, when executed on a device, causes the device to perform the data operation method of any one of claims 1-6.

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