Page table prefetch method, memory management unit, chip and related products

Abstract

The present disclosure provides a page table prefetching method, a storage management unit, a chip and related products, and relates to the technical field of computers. If a received virtual address belongs to a trigger address range, a page table in a set range is stored in a page table cache. The scheme provided by the present disclosure can improve the hit rate of a TLB.

Description

Technical Field

[0001] This disclosure relates to computer technology, and more particularly to a page table prefetching method, a memory management unit, a chip, a circuit board, a computer-readable storage medium, and a computer program product. Background Technology

[0002] The System Memory Management Unit (SMMU) in a System on Chip (SoC) is typically used to translate virtual addresses to physical addresses during memory access. To reduce memory access overhead during address translation, the SMMU usually uses a Translation Lookaside Buffer (TLB) to store a portion of the page table. When the SMMU receives a virtual address, it first looks up the corresponding page table in the TLB. If the TLB does not contain the corresponding page table (i.e., a TLB miss), the SMMU needs to read a new page table from off-chip storage to replace the portion of the page table stored in the TLB. This method reduces memory access efficiency and incurs significant overhead. Therefore, a solution is needed to improve the TLB hit rate to increase data processing speed. Summary of the Invention

[0003] This disclosure provides a page table prefetching method, a storage management unit, a chip, and related products. By pre-storing page tables within a certain address range in the page table cache, the TLB hit rate can be improved, thereby increasing the speed of storage access.

[0004] The first aspect of this disclosure is to provide a page table prefetching method, comprising:

[0005] Receive the virtual address and obtain the trigger address range for prefetching the page table;

[0006] If the received virtual address belongs to the trigger address range, the prefetch length stores the page table within the set range into the page table cache; and the set range is updated, and the updated set range is used for the next prefetch of the page table.

[0007] A second aspect of this disclosure is to provide a storage management unit, the storage management unit comprising:

[0008] Page table cache is used to store page tables;

[0009] The controller is used to receive virtual addresses and obtain the trigger address range of page tables. If the received virtual address belongs to the trigger address range, the prefetch length stores the page tables within the set range into the page table cache; and updates the set range, the updated set range is used for the next prefetch of page tables.

[0010] A third aspect of this disclosure is to provide a chip including a memory management unit as described in the second aspect.

[0011] A fourth aspect of this disclosure is to provide a computer-readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement the method as described in the first aspect above.

[0012] A fifth aspect of this disclosure is to provide a computer program product including a computer program that, when executed by a processor, implements the method described in the first aspect above.

[0013] The page table prefetching method, memory management unit, chip, and related products disclosed herein include: receiving a virtual address and obtaining a trigger address range for prefetching page tables; if the received virtual address belongs to the trigger address range, the page tables within the set range are stored in the page table cache for a prefetch length; and updating the set range, the updated set range being used for the next page table prefetch. The page table prefetching method, memory management unit, chip, and related products disclosed herein can automatically prefetch page tables within a set range when trigger conditions are met, ensuring that the page tables are stored in the SMMU before use, thereby improving the TLB hit rate. Furthermore, the method and chip disclosed herein can dynamically update the set range to achieve automatic updating and replacement of page tables in the SMMU. Attached Figure Description

[0014] Figure 1 This is a schematic flowchart illustrating a page table prefetching method as an exemplary embodiment of the present disclosure;

[0015] Figure 2 This is a schematic diagram illustrating the trigger address range and the setting range as an exemplary embodiment of this disclosure;

[0016] Figure 3 This is a schematic diagram illustrating the updating of the trigger address range as an exemplary embodiment of this disclosure;

[0017] Figure 4 A schematic flowchart of a page table prefetching method provided in another embodiment of this disclosure;

[0018] Figure 5 This is a schematic diagram illustrating the determination of a trigger address range as an exemplary embodiment of the present disclosure;

[0019] Figure 6 This is a schematic diagram illustrating the determination of a trigger address range, as shown in another exemplary embodiment of this disclosure.

[0020] Figure 7 This is a schematic diagram illustrating the determination of a set range as an exemplary embodiment of the present disclosure;

[0021] Figure 8 A schematic diagram illustrating the determination of a set range for another exemplary embodiment of this disclosure;

[0022] Figure 9 This is a schematic diagram illustrating an update trigger address range as an example of this disclosure;

[0023] Figure 10 This is another exemplary illustration of an update trigger address range shown in this disclosure;

[0024] Figure 11 A schematic diagram of the structure of a page table prefetching device shown in an exemplary embodiment of this disclosure;

[0025] Figure 12 This is a schematic diagram of the structure of a page table prefetching device, which is another exemplary embodiment of the present disclosure. Detailed Implementation

[0026] Currently, the System Memory Management Unit (SMMU) in a System on Chip (SOC) is typically used to translate virtual addresses to physical addresses during memory access. To reduce memory access overhead during address translation, the SMMU usually uses a Translation Lookaside Buffer (TLB) to store a portion of the page table. The TLB divides the virtual address into a series of equal-sized portions called pages through paging memory management, and assigns a number to each page. Similarly, physical memory is divided into contiguous portions of the same size called page frames, and each page frame is numbered. The page table stores a mapping between page numbers and page frame numbers. Therefore, when the chip reads data, the chip hardware typically receives a virtual address provided by the software. It checks the TLB to see if a physical address corresponding to that virtual address is stored. If a physical address is found, a hit occurs; otherwise, a miss occurs. If a TLB hit occurs, the virtual address can be translated to a physical address based on the mapping between virtual and physical addresses in the page table, allowing read and write operations to be performed on the address space pointed to by the physical address. If a TLB miss occurs, in order to translate the virtual address into a physical address, the SMMU needs to read a new page table from off-chip memory to replace part of the page table stored in the TLB. This method will reduce memory access efficiency and incur significant overhead.

[0027] To improve TLB hit rate, existing technologies employ page table prefetching schemes, where the page table represents the mapping between virtual and physical addresses. Specifically, when a virtual address falls within a threshold address range, multiple consecutive page tables are retrieved to increase the TLB hit probability. However, this fixed prefetching method cannot guarantee that the next received virtual address will hit the previously prefetched page table. In latency-sensitive scenarios, it fails to meet the performance requirements of the SMMU.

[0028] To address the aforementioned technical issues, the solution provided in this disclosure can dynamically update the setting range used for prefetching page tables, thereby improving the TLB hit probability.

[0029] Figure 1 This is a schematic flowchart illustrating a page table prefetching method as an exemplary embodiment of the present disclosure.

[0030] like Figure 1 As shown, the page table prefetching method provided in this disclosure includes:

[0031] Step 101: Receive the virtual address and obtain the trigger address range for prefetching the page table.

[0032] The solution provided in this disclosure can be executed by a system-on-a-chip (SoC) with data processing capabilities, specifically by the SoC's system memory management unit (SMMU).

[0033] Optionally, the SMMU on the chip is configured with a trigger address range, which can be dynamically updated. For example, the trigger address range can be updated every time a page table is prefetched, as described below.

[0034] The SMMU can receive a virtual address, which is used for data access. The SMMU can look up the page table in the TLB based on this virtual address. If the TLB hits, the SMMU can determine the physical address corresponding to the virtual address based on the matched page table and perform data read / write operations on the corresponding address in memory. If the TLB misses, the SMMU needs to retrieve the corresponding page table from external memory and store it in the TLB to perform virtual-to-physical address translation, and then perform memory access based on the translated physical address.

[0035] Step 102: If the received virtual address belongs to the trigger address range, then store the page table within the set range into the page table cache.

[0036] Optionally, if the virtual address received by the SMMU falls within the trigger address range, then the conditions for automatic prefetching are met. Therefore, the SMMU can automatically prefetch the page tables and store the page tables within the specified range into the page table cache (TLB). For example, if the obtained trigger address range is 1-10 and the received virtual address is 3, then the virtual address is considered to fall within the trigger address range. Therefore, the prefetching process can be performed, and the page tables within the specified range can be stored in the page table cache (TLB).

[0037] Optionally, a set range can be configured in the SMMU. If the received virtual address belongs to the trigger address range, the page table within that range is cached in the TLB to increase the probability of a TLB hit when a virtual address is received next time. In this embodiment of the present disclosure, the set range can be dynamically variable. Therefore, when a virtual address is received next time, the range of the page table prefetched is not fixed, thereby improving the TLB hit rate.

[0038] Step 103: Update the setting range. The updated setting range will be used for the next page prefetch.

[0039] Optionally, after completing a prefetch operation, the set range can be updated. When the next received virtual address falls within the trigger address range, the page table within the updated set range can be prefetched. As the received virtual address changes, the next received virtual address may also change. Therefore, by dynamically adjusting the set range, the range of the prefetched page table can be adjusted, thereby increasing the probability that the next received virtual address falls within the prefetched page table range, thus improving the TLB hit rate.

[0040] In one embodiment of this disclosure, after completing a prefetch operation, the SMMU can also update the trigger address range and the setting range for the prefetch page table. Optionally, after completing a prefetch operation, the SMMU can dynamically update the trigger address range and the setting range of the page table according to preset prefetch parameters such as the prefetch direction. For example, the SMMU can move the trigger address range in a preset direction by a preset length to obtain the updated trigger address range.

[0041] Optionally, the SMMU can also pre-set the address change direction, which can be determined based on the address change pattern when the functional module actually issues virtual addresses. For example, if the virtual address issued by the functional module changes in an increasing pattern, the address change direction is set to increase; if the virtual address issued by the functional module changes in a decreasing pattern, the address change direction is set to decrease.

[0042] Optionally, the SMMU can determine the setting range based on the direction of address change. For example, if the address change direction is increasing, the setting range for prefetching can be determined along the increasing direction; if the address change direction is decreasing, the setting range for prefetching can be determined along the decreasing direction.

[0043] Figure 2 This is a schematic diagram illustrating the trigger address range and the setting range as an exemplary embodiment of the present disclosure.

[0044] like Figure 2 As shown, the example is based on an increasing address change direction. For instance, if a trigger address range 21 exists, and the received virtual address 22 belongs to this range, the page table within the set range 23 can be stored in the TLB. Optionally, after page table prefetching is complete, the trigger address range can be updated. For example, the trigger address range can be updated according to the address change direction described above. For instance, if the address change is increasing, the trigger address range can be moved in the increasing direction to obtain the updated trigger address range. Furthermore, the set range used for prefetching page tables can be updated according to the address change direction. Optionally, after the SMMU receives the virtual address again, it can perform a prefetch operation based on the updated set range.

[0045] Figure 3 This is a schematic diagram illustrating the updating of the trigger address range as an exemplary embodiment of this disclosure.

[0046] like Figure 3 As shown, the explanation uses an increasing address change direction as an example. For instance, if there is a trigger address range 31, after performing a prefetch based on this range 31, it can be updated to a trigger address range 32. Specifically, the prefetch length can be shifted in the increasing direction to obtain the updated trigger address range 32. This prefetch length can, for example, be the length of a set range.

[0047] Optionally, the SMMU can update the setting range based on changes in the trigger address range. In this embodiment, the setting range can be dynamically changed; optionally, the setting range can dynamically change with changes in the trigger address range. For example, when a virtual address falls into the trigger address range, the address range near the trigger address range can be determined as the setting range for page table prefetching. Therefore, the setting range can be an address range adjacent to the trigger address range, and the setting range will also change when the trigger address range is updated. The page table prefetching method provided in this disclosure includes: receiving a virtual address and obtaining a trigger address range for prefetching a page table; if the received virtual address belongs to the trigger address range, the prefetch length stores the page table within the setting range into the page table cache; and updating the setting range, the updated setting range being used for the next page table prefetch. In the method provided in this disclosure, the setting range can be dynamically updated, thereby dynamically updating the range of the prefetched page table, increasing the probability that the next received virtual address falls into the range of the prefetched page table, and thus improving the TLB hit rate.

[0048] Figure 4 This is a schematic flowchart of a page table prefetching method provided in another embodiment of the present disclosure.

[0049] Step 401: Receive the virtual address. Step 401 is implemented similarly to step 101, and will not be described again.

[0050] Step 402: Determine the trigger address range based on the preset threshold, prefetch direction, and address boundaries.

[0051] Optionally, preset thresholds, prefetch direction, and address boundaries can be set in the SMMU. The SMMU can acquire at least one of these three parameters and determine the trigger address range based on these parameters. In this embodiment of the disclosure, these parameters can be configured internally within the SMMU or can be customized through a single passive prefetch operation by the user; no specific limitations are imposed here.

[0052] Optionally, the preset threshold is used to characterize the length of the trigger address range, the prefetch direction is used to characterize the address change direction of the virtual address obtained from the SMMU, such as whether it is an increasing or decreasing direction, and the address boundary refers to the boundary of the trigger address range.

[0053] Optionally, the address boundary can be dynamically changed. For example, after each prefetch operation is completed, the address boundary can be updated, thereby updating the trigger address range as well.

[0054] Optionally, this address boundary is also used to determine a set range, which refers to the range of page table addresses to be prefetched during a prefetch operation. By dynamically updating the trigger address range and the set range, the TLB hit rate can be improved.

[0055] Optionally, if the prefetch direction is incremental, the value of the address boundary minus the threshold is used as the starting address, and the address boundary is used as the ending address; the trigger address range is determined based on the starting and ending addresses. The prefetch direction refers to the direction in which the page table is prefetched, and the specific range of the page table can be determined based on the prefetch direction.

[0056] Figure 5 This is a schematic diagram illustrating the determination of a trigger address range as an exemplary embodiment of the present disclosure.

[0057] like Figure 5 As shown, there exists an address boundary nxt_addr and a threshold of thr. Since the prefetch direction is incremental, the address boundary nxt_addr can be used as the termination address, and (nxt_addr-thr) can be used as the starting address to obtain the trigger address range. Optionally, this trigger address range may include (nxt_addr-thr) but not nxt_addr, and the trigger address range is specifically [nxt_addr-thr, nxt_addr].

[0058] Optionally, if the prefetch direction is decreasing, the address boundary is used as the starting address, and the address boundary plus a threshold value is used as the ending address; the trigger address range is determined based on the starting and ending addresses. The prefetch direction refers to the direction in which the page table is prefetched, and the specific range of the page table can be determined based on the prefetch direction.

[0059] Figure 6 This is a schematic diagram illustrating the determination of a trigger address range, which is another exemplary embodiment of this disclosure.

[0060] like Figure 6 As shown, there exists an address boundary nxt_addr and a threshold of thr. Since the prefetch direction is decreasing, the address boundary nxt_addr can be used as the starting address, and (nxt_addr+thr) as the ending address to obtain the trigger address range. Optionally, this trigger address range may include (nxt_addr+thr) but not nxt_addr, specifically (nxt_addr, nxt_addr+thr).

[0061] If the prefetch direction is increasing, step 403 can be executed after obtaining the trigger address range.

[0062] If the prefetch direction is decreasing, step 404 can be executed after obtaining the trigger address range.

[0063] In this embodiment of the disclosure, since retrieving the page table from memory takes a long time, setting a prefetch threshold can ensure that the page table that actually uses nxt_addr is retrieved in advance before it is used. Therefore, for a period of time after the SMMU receives the virtual address falling into the address range, the virtual address received by the SMMU is still within the aforementioned trigger address range, thereby improving the TLB hit rate.

[0064] Step 403: If the received virtual address belongs to the trigger address range, the address boundary is used as the starting prefetch address, and the address boundary plus the prefetch length is used as the ending prefetch address.

[0065] The start prefetch address and the end prefetch address are used to determine the range of the prefetch page table.

[0066] If the received virtual address falls within the trigger address range, a prefetch operation can be performed. Specifically, the prefetch range can be determined based on the address boundaries, and then the page tables within the set range can be stored in the page table cache to complete the prefetch operation.

[0067] Optionally, a prefetch length can be preset in the SMMU. This prefetch length is used to characterize the length of the set range, so that the set range can be determined based on the address boundary, the prefetch length, and the prefetch direction. Specifically, if the prefetch direction is incremental, the updated address boundary can be used as the starting prefetch address, and the address boundary plus the prefetch length value can be used as the ending prefetch address, thereby obtaining the set range from the starting prefetch address to the ending prefetch address.

[0068] Figure 7 This is a schematic diagram illustrating the determination of a setting range as an exemplary embodiment of this disclosure.

[0069] like Figure 7 As shown, given an address boundary nxt_addr and a prefetch length of len, when the prefetch direction is increasing, nxt_addr can be used as the starting prefetch address, and (nxt_addr+len) as the ending prefetch address to obtain the defined range. Optionally, this defined range may include nxt_addr but not (nxt_addr+len), and the defined range is specifically [nxt_addr, nxt_addr+len).

[0070] Step 404: If the received virtual address belongs to the trigger address range, then the value of the address boundary minus the prefetch length is used as the starting prefetch address, and the address boundary is used as the ending prefetch address.

[0071] The start prefetch address and the end prefetch address are used to determine the range of the prefetch page table.

[0072] If the virtual address received by the SMMU falls within the trigger address range, a prefetch operation can be performed. Specifically, the prefetch range can be determined first based on the address boundaries, and then the page tables within the prefetch range can be stored in the page table cache to complete the prefetch operation. Optionally, a prefetch length can be pre-set in the SMMU. This prefetch length represents the length of the prefetch range, allowing the prefetch range to be determined based on the address boundaries and the prefetch length. If the prefetch direction is decreasing, the address boundary can be used as the termination prefetch address, and the value of the address boundary minus the prefetch length can be used as the starting prefetch address, thus obtaining the prefetch range from the starting prefetch address to the termination prefetch address.

[0073] Figure 8 This is a schematic diagram illustrating the determination of a setting range for another exemplary embodiment of this disclosure.

[0074] like Figure 8 As shown, given an address boundary nxt_addr and a prefetch length of len, when the prefetch direction is decreasing, nxt_addr can be used as the ending prefetch address, and (nxt_addr-len) as the starting prefetch address to obtain a defined range. This defined range can include nxt_addr but not (nxt_addr-len), specifically (nxt_addr-len, nxt_addr).

[0075] Optionally, in this embodiment of the disclosure, when the SMMU triggers an automatic prefetch operation and determines the prefetched page table setting range, the aforementioned automatic prefetch operation can be performed. Return Figure 4 The above page table prefetching method may also include:

[0076] Step 405: Store the page table within the range of the start prefetch address to the end prefetch address in the page table cache.

[0077] The SMMU can store page tables within the range of the start prefetch address to the end prefetch address in the page table cache to enable page table prefetching operations.

[0078] When the prefetch direction is increasing, if the received virtual address falls within the address range [nxt_addr-thr, nxt_addr), a page table with a range of [nxt_addr, nxt_addr+len) can be prefetched. When the prefetch direction is decreasing, if the received virtual address falls within the address range (nxt_addr, nxt_addr+thr), a page table with a range of (nxt_addr-len, nxt_addr) can be prefetched. In this embodiment, since retrieving the page table from memory takes a relatively long time, setting a prefetch length can also ensure that the page table is retrieved in advance before it is actually used, thereby improving the TLB hit rate.

[0079] Alternatively, after completing a page table prefetch operation, the SMMU can automatically update the trigger address range to achieve automatic page table updates through the automatic changes in the trigger address range and the page table prefetch range, thereby achieving automatic page table prefetching, and the page table range prefetched each time is dynamically changing.

[0080] Optionally, the trigger address range and / or setting range can be determined based on the address boundary. Therefore, after completing a page table prefetch operation, the address boundary can be updated, and then the trigger address range and / or setting range can be updated based on the updated address boundary.

[0081] See also Figure 4 The page table prefetching method described above may further include step 406 or step 407, and may further include step 408. Steps 406 and 407 represent two methods for updating the trigger address range provided by this disclosure, and step 408 represents a method for setting the update range provided by this disclosure.

[0082] Step 406: Update the trigger address range based on the preset threshold, prefetch direction, and address boundaries.

[0083] Step 407: Update the trigger address range according to the preset transition length, prefetch direction, and address boundaries.

[0084] Step 408: Update the setting range based on the prefetch length, prefetch direction, and address boundaries.

[0085] In one implementation, the SMMU can update the trigger address range using a preset threshold.

[0086] Optionally, the SMMU can update the trigger address range based on the prefetch direction to obtain the updated trigger address range.

[0087] If the prefetch direction is increasing, the trigger address range is moved in the increasing direction. If the prefetch direction is decreasing, the trigger address range is moved in the decreasing direction. Specifically, the SMMU can update the address boundaries according to the prefetch direction to obtain the updated address boundaries, and then determine the updated trigger address range based on the updated address boundaries, the preset threshold, and the prefetch direction. Furthermore, the SMMU can also update the set range used for prefetching based on the updated address boundaries.

[0088] In one embodiment, if the prefetch direction is incremental, the address boundary is updated to the sum of the new address boundary and the prefetch length; wherein, the prefetch length is used to determine the set range; the trigger address range is updated according to the updated address boundary, the preset threshold, and the prefetch direction, and the set range for prefetching the page table is determined according to the updated trigger address range. The specific method for determining the page table set range can be found in the description above.

[0089] Figure 9 This is a schematic diagram illustrating an update trigger address range as an example of this disclosure.

[0090] like Figure 9 As shown, if the prefetch direction is increasing, there exists an address boundary `nxt_addr`, and the corresponding trigger address range is [nxt_addr - thr, nxt_addr), with a prefetch length `len`. When updating the trigger address range, this address boundary can be updated in the increasing direction, specifically to (nxt_addr + len). Afterward, the SMMU can determine the updated trigger address range based on the updated address boundary (nxt_addr + len), the preset threshold `thr`, and the increasing prefetch direction; specifically, it can be [nxt_addr + len - thr, nxt_addr + len].

[0091] Optionally, the address range can be updated based on the updated address boundaries, prefetch length, and prefetch direction. For example, the address range can be updated from [nxt_addr, nxt_addr+len) to [nxt_addr+len, nxt_addr+2*len).

[0092] In one embodiment, if the prefetch direction is decreasing, the address boundary is updated to the difference between the address boundary and the prefetch length; wherein the prefetch length is used to determine the set range; the trigger address range is updated according to the updated address boundary and the preset threshold, and the set range for prefetching the page table is determined according to the updated trigger address range. The specific method for determining the page table set range can be found in the description above.

[0093] Figure 10 This is a schematic diagram illustrating another exemplary update trigger address range in this disclosure.

[0094] like Figure 10As shown, if the prefetch direction is decreasing, there exists an address boundary nxt_addr, and the corresponding trigger address range is (nxt_addr, nxt_addr + thr), with a prefetch length len. When updating the trigger address range, the address boundary can be updated in the decreasing direction, specifically to (nxt_addr - len). Afterward, the SMMU can determine the updated trigger address range based on the updated address boundary (nxt_addr - len), the preset threshold thr, and the decreasing prefetch direction; specifically, it can be (nxt_addr - len, nxt_addr - len + thr).

[0095] Optionally, the set address range can be updated based on the updated address boundary prefetch length and the prefetch direction. The set range can be updated from (nxt_addr-len, nxt_addr] to (nxt_addr-2*len, nxt_addr-len).

[0096] In another implementation, the SMMU can update the trigger address range with a preset transition length. This transition length can dynamically change during each prefetch operation, and the specific transition length can be dynamically configured by the user. See also... Figure 4 The above page table prefetching method may include:

[0097] Step 407: Update the trigger address range according to the preset transition length, prefetch direction, and address boundaries.

[0098] Optionally, the SMMU can update the address boundary based on the prefetch direction and transition length, and then update the trigger address range based on the updated address boundary. Specifically, it can be determined based on the updated address boundary, the preset threshold, and the prefetch direction, and the setting range for the prefetch page table can be determined based on the updated trigger address location. The specific method for determining the page table setting range can be found in the description above.

[0099] If the prefetch direction is increasing, the SMMU can update the address boundary to the sum of the address boundary and a preset transition length; and update the trigger address range based on the updated address boundary and a preset threshold. For example, if the prefetch direction is increasing, there exists an address boundary `nxt_addr`, and the corresponding trigger address range is [nxt_addr - thr, nxt_addr), with a transition length of `stride`. When updating the trigger address range, the SMMU can update this address boundary in the increasing direction, specifically updating it to (nxt_addr + stride). Afterward, the SMMU can determine the updated trigger address range based on the updated address boundary (nxt_addr + stride), the preset threshold `thr`, and the increasing prefetch direction, specifically [nxt_addr + stride - thr, nxt_addr + stride].

[0100] Optionally, the address range can be updated based on the updated address boundaries, prefetch length, and prefetch direction. For example, the address range can be updated from [nxt_addr, nxt_addr+len) to [nxt_addr+stride, nxt_addr+len+stride).

[0101] If the prefetch direction is decreasing, the address boundary is updated to the difference between the address boundary and the preset transition length; the trigger address range is then updated based on the updated address boundary and the preset threshold. For example, if the prefetch direction is decreasing and there exists an address boundary nxt_addr, the corresponding trigger address range is (nxt_addr, nxt_addr+thr], and the transition length is stride. When updating the trigger address range, the SMMU can update this address boundary in the decreasing direction, specifically updating the address boundary to (nxt_addr-stride).

[0102] Subsequently, the SMMU can determine the updated trigger address range based on the updated address boundary (nxt_addr - stride), the preset threshold thr, and the decreasing prefetch direction. Specifically, it can be (nxt_addr - stride, nxt_addr - stride + thr). Optionally, the set address range can also be updated based on the updated address boundary, prefetch length, and prefetch direction. For example, the set range can be updated from (nxt_addr - len, nxt_addr) to (nxt_addr - len - stride, nxt_addr - stride).

[0103] In this embodiment, the SMMU can perform automatic page table prefetching. After completing the address translation of the current virtual address, based on the dynamic update process of the aforementioned trigger address range and the set range of the page table, it can automatically perform the next page table prefetch, thus repeating the above steps multiple times until the prefetching condition is no longer met. If the prefetching condition is not met, even if the received virtual address belongs to the trigger address range, the SMMU will no longer perform the page table prefetching operation. Therefore, only when the prefetching condition is met and the received virtual address belongs to the trigger address range will the SMMU perform the step of storing the page table within the set range into the page table cache.

[0104] Optionally, the SMMU can be configured with an enable signal and a total prefetch length. When the enable signal indicates that automatic prefetching is possible and the total prefetch length is greater than 0, the prefetch condition is considered met. When the enable signal indicates that automatic prefetching is not possible, and / or the total prefetch length is equal to 0, the automatic prefetching operation is terminated.

[0105] Optionally, the user can enable the automatic prefetch function, in which case the enable signal value is set to a value indicating that automatic prefetching is possible, for example, the enable signal is set to a high level (e.g., 1). The user can also disable the automatic prefetch function, in which case the enable signal value is set to a value indicating that automatic prefetching is not possible, for example, the enable signal is set to a low level (e.g., 0). Optionally, the SMMU can also automatically enable the automatic prefetch function. For example, the automatic prefetch function requires configuring parameters such as the trigger address range. When the SMMU detects that the automatic prefetch configuration parameters are in effect, it can consider that the prefetch condition is met, and thus set the enable signal to a value indicating that automatic prefetching is possible.

[0106] Optionally, the initial value of the total prefetch length can be pre-set in the SMMU to characterize the total length that can be prefetched when continuously prefetching page tables. When the SMMU determines that the enable signal is a value that allows automatic prefetching, the chip hardware can automatically update a counter. Whenever a TLB miss occurs in the SMMU or passive prefetching is triggered, the initial value of the counter is updated to the preset total prefetch length. Passive prefetching schemes are described below.

[0107] Subsequently, after each prefetch operation that stores page tables within a defined range into the page table cache, the SMMU subtracts the prefetch length from the total prefetch length to obtain the updated total prefetch length; the prefetch length is used to determine the defined range. For example, if the prefetch length is len, then after each prefetch operation, the counter subtracts len from the total prefetch length to obtain the updated total prefetch length. When the total prefetch length decreases to 0, it is considered that the prefetch condition is not met. At this time, even if the received virtual address belongs to the trigger address range, the SMMU will no longer perform page table prefetch operations. The SMMU will only perform automatic prefetch operations again when the automatic prefetch condition is triggered again.

[0108] Optionally, the solution provided in this disclosure also provides a passive prefetching method. When the SMMU receives a passive prefetching request, it can be considered that the automatic prefetching is interrupted. In this case, the total prefetch length can be set to an initial value, which can be a user-defined parameter.

[0109] The passive prefetch mechanism of the SMMU refers to the operation of prefetching page tables based on received page table prefetch requests. In response to each page table prefetch request, the SMMU stores a preset number of page tables from external memory into the page table cache. A page table prefetch request can include the starting address of the page tables to be prefetched and the number of page tables to be prefetched. For example, if the page table prefetch operation wants to retrieve n consecutive page tables starting from the starting address addr, it can send a page table prefetch request including addr and n to the SMMU. The SMMU can then read n consecutive page tables starting from the addr address in external memory and store the retrieved page tables in the page table cache (TLB) to achieve the page table prefetch operation.

[0110] In one optional implementation, the page table prefetch request may be configured in the SMMU by software, and the SMMU may perform the corresponding page table prefetch operation upon receiving the page table prefetch request. In another optional implementation, the page table prefetch request may be sent to the SMMU by a functional module, and the passive prefetch request includes the starting address of the page table to be prefetched and the number of page tables to be prefetched.

[0111] In one implementation, the software can specify the starting address of the SMMU prefetch and the number of page tables to be prefetched by writing to the SMMU register. The SMMU will then perform the prefetch operation immediately upon receiving the command.

[0112] In another implementation, the functional module can specify the starting address of the SMMU prefetch and the number of page tables to be prefetched by sending commands through the hardware prefetch interface. The SMMU will then perform the prefetch operation immediately upon receiving the command. In many scenarios, the execution of the functional module and the configuration of the functional module by the software are asynchronous, and the delay in configuring the SMMU registers by the software may be significant. Therefore, the passive prefetch mechanism triggered by the functional module can more precisely control the timing of the passive prefetch mechanism, thereby providing sufficient time margin for SMMU prefetch execution and preventing premature prefetching that could lead to the replacement of page tables currently in use in the TLB.

[0113] Optionally, the SMMU can also set relevant parameters for the automatic prefetch mechanism based on the passive prefetch request, including but not limited to at least one of preset thresholds, prefetch direction, address boundaries, and jump length, to determine the trigger address range and the set range. The SMMU can also set the value of the automatic prefetch enable signal based on the passive prefetch request. When the automatic prefetch conditions are met, the SMMU can update the trigger address range and the set range of the page table after each page table prefetch operation is completed, thereby realizing dynamic automatic prefetching of the page table until the total prefetch length decreases to 0. For details on the automatic prefetch process, please refer to the description above.

[0114] Figure 11 This is a schematic diagram of the structure of a page table prefetching device shown as an exemplary embodiment of the present disclosure.

[0115] like Figure 11 As shown, the page table prefetching device 1100 provided in this disclosure includes:

[0116] Receiving unit 1110 is used to receive virtual addresses;

[0117] The acquisition unit 1120 is used to acquire the trigger address range for prefetching the page table;

[0118] The prefetch unit 1130 is used to store the page table within the set range into the page table cache if the received virtual address belongs to the trigger address range;

[0119] The update unit 1140 is used to update the set range, and the updated set range is used for the next prefetch page table.

[0120] Figure 12 This is a schematic diagram of the structure of a page table prefetching device, which is another exemplary embodiment of the present disclosure.

[0121] like Figure 12 As shown, the page table prefetching device 1200 provided in this disclosure, based on the above embodiments, further includes an acquisition unit 1120 used for:

[0122] The trigger address range is determined based on the preset threshold, prefetch direction, and address boundaries.

[0123] Optionally, the acquisition unit 1120 includes an increment trigger module 1121, used for:

[0124] If the prefetch direction is increasing, then the value of the address boundary minus the threshold is used as the starting address, and the address boundary is used as the ending address;

[0125] The trigger address range is determined based on the start address and the end address.

[0126] Optionally, the prefetch unit 1130 includes an incremental prefetch module 1131, used for:

[0127] If the received virtual address belongs to the trigger address range, then the address boundary is used as the starting prefetch address, and the address boundary plus the prefetch length is used as the ending prefetch address.

[0128] Store the page table within the range from the start prefetch address to the end prefetch address in the page table cache.

[0129] The acquisition unit 1120 includes a decrement trigger module 1122, used for:

[0130] If the prefetch direction is decreasing, then the address boundary is used as the starting address, and the value of the threshold plus the address boundary is used as the ending address.

[0131] The trigger address range is determined based on the start address and the end address.

[0132] Optionally, the prefetch unit 1130 includes a decrementing prefetch module 1132, used for:

[0133] The value of the address boundary minus the prefetch length is used as the starting prefetch address, and the address boundary is used as the ending prefetch address;

[0134] Store the page table within the range from the start prefetch address to the end prefetch address in the page table cache.

[0135] Optionally, the updating unit 1140 is further configured to:

[0136] The trigger address range is updated based on the preset threshold, prefetch direction, and address boundaries.

[0137] Optionally, the update unit 1140 includes a first incremental update module 1141, used for:

[0138] When the prefetch direction is increasing, the address boundary is updated to the sum of the address boundary and the prefetch length; wherein, the prefetch length is used to determine the set range;

[0139] The trigger address range is updated based on the updated address boundaries, the preset threshold, and the prefetch direction.

[0140] Optionally, the update unit 1140 includes a first decrementing update module 1142, used for:

[0141] When the prefetch direction is decreasing, the address boundary is updated to the difference between the address boundary and the prefetch length; wherein, the prefetch length is used to determine the set range;

[0142] The trigger address range is updated based on the updated address boundaries and the preset threshold.

[0143] Optionally, the updating unit 1140 is further configured to:

[0144] The trigger address range is updated based on the preset transition length, prefetch direction, and address boundaries.

[0145] Optionally, the update unit 1140 includes a second incremental update module 1143, used for:

[0146] When the prefetch direction is increasing, the address boundary is updated to the sum of the address boundary and the preset transition length;

[0147] The trigger address range is updated based on the updated address boundaries and the preset threshold.

[0148] Optionally, the update unit 1140 includes a second decrementing update module 1144, used for:

[0149] When the prefetch direction is decreasing, the address boundary is updated to the difference between the address boundary and the preset transition length;

[0150] The trigger address range is updated based on the updated address boundaries and the preset threshold.

[0151] Optionally, the update unit 1140 is specifically used for:

[0152] The set range is updated based on the prefetch length, prefetch direction, and address boundaries.

[0153] Optionally, the update unit 1140 is specifically used for:

[0154] When the prefetch direction is increasing, the address boundary is updated to the sum of the address boundary and the prefetch length.

[0155] The set address range is updated based on the updated address boundaries, prefetch length, and prefetch direction.

[0156] Optionally, the update unit 1140 is specifically used for:

[0157] When the prefetch direction is decreasing, the address boundary is updated to the difference between the address boundary and the prefetch length.

[0158] The set address range is updated based on the updated address boundaries, prefetch length, and prefetch direction.

[0159] Optionally, the update unit 1140 is specifically used for:

[0160] The preset range is updated based on the preset transition length, prefetch length, prefetch direction, and address boundaries.

[0161] Optionally, the update unit 1140 is specifically used for:

[0162] When the prefetch direction is increasing, the address boundary is updated to the sum of the address boundary and the preset transition length;

[0163] The set range is updated based on the updated address boundaries, prefetch length, and prefetch direction.

[0164] Optionally, the update unit 1140 is specifically used for:

[0165] When the prefetch direction is decreasing, the address boundary is updated to the difference between the address boundary and the preset transition length;

[0166] The set range is updated based on the updated address boundaries, prefetch length, and prefetch direction.

[0167] Optionally, prefetching conditions are also set;

[0168] The prefetching unit 1130 is specifically used for:

[0169] If the received virtual address belongs to the trigger address range and meets the prefetch condition, then the step of storing the page table within the set range into the page table cache is executed.

[0170] If the enable signal representation can be automatically prefetched and the total prefetch length is greater than 0, then the prefetching unit 1130 determines that the prefetching condition is met.

[0171] Optionally, the update unit 1140 further includes a length update module 1141. After the prefetch unit 1130 stores the page table within the set range into the page table cache, the length update module 1141 subtracts the prefetch length from the total prefetch length to obtain the updated total prefetch length; the prefetch length is used to determine the set range.

[0172] Optionally, the length update module 1141 is further configured to:

[0173] When a page table cache miss occurs, or when a passive prefetch request is received, the initial value of the total prefetch length is determined.

[0174] After storing the page tables within the set range into the page table cache, the total prefetch length is updated until the total prefetch length is reduced to 0.

[0175] Optionally, the receiving unit 1110 is further configured to determine prefetch conditions based on the received passive prefetch request.

[0176] Another embodiment of this disclosure also provides a storage management unit.

[0177] The storage management unit includes:

[0178] Page cache is used to store page tables;

[0179] The controller is used to receive virtual addresses and obtain the trigger address range of page tables. If the received virtual address belongs to the trigger address range, the prefetch length stores the page tables within the set range into the page table cache; and updates the set range, the updated set range is used for the next prefetch of page tables.

[0180] Another embodiment of this disclosure also provides an SMMU, comprising:

[0181] Memory;

[0182] Processor; and

[0183] Computer programs;

[0184] The computer program is stored in the memory and configured to be executed by the processor to implement any of the methods described above.

[0185] Another embodiment of this disclosure also provides a chip that includes a memory management unit as described above.

[0186] Another embodiment of the present invention is a computer-readable storage medium storing computer program instructions for data processing. When the computer program instructions are executed by a server, the server includes a processor and a memory. The memory stores the aforementioned computer program instructions, and the processor executes the computer program instructions in the memory to complete the data processing based on the technology.

[0187] In some implementation scenarios, the integrated unit described above can be implemented as a software program module. If implemented as a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable storage device (CMSD). Therefore, when the solution of this invention is embodied in the form of a software product (e.g., a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to cause a computer device (e.g., a personal computer, server, or network device) to execute some or all of the steps of the method described in the embodiments of this invention. When the solution of this invention is embodied in the form of a SMMU, the device includes a processor and a memory, the memory being used to store processor-executable instructions, and the processor being configured to invoke the instructions stored in the memory to perform data processing based on technology. The aforementioned memory may include, but is not limited to, various media capable of storing program code, such as USB flash drives, flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0188] Depending on the application scenario, the SMMU or device of the present invention may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, PC devices, IoT terminals, mobile terminals, mobile phones, dashcams, navigators, sensors, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, autonomous driving terminals, vehicles, home appliances, and / or medical devices. The vehicles include airplanes, ships, and / or vehicles; the home appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods; the medical devices include MRI scanners, ultrasound scanners, and / or electrocardiographs. The SMMU or device of the present invention can also be applied in fields such as the Internet, IoT, data centers, energy, transportation, public management, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, and healthcare. Furthermore, the SMMU or device of the present invention can also be used in application scenarios related to artificial intelligence, big data, and / or cloud computing, such as cloud computing, edge computing, and terminal computing. In one or more embodiments, the high-computing-power SMMU or device according to the present invention can be applied to cloud devices (e.g., cloud servers), while the low-power SMMU or device can be applied to terminal devices and / or edge devices (e.g., smartphones or cameras). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and / or edge device are compatible with each other, so that suitable hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and / or edge device according to the hardware information of the terminal device and / or edge device, so as to complete the unified management, scheduling and collaborative work of end-to-cloud or cloud-edge-end integration.

[0189] It should be noted that, for the sake of brevity, this invention describes some methods and their embodiments as a series of actions and combinations thereof. However, those skilled in the art will understand that the solution of this invention is not limited to the order of the described actions. Therefore, based on the disclosure or teachings of this invention, those skilled in the art will understand that some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art will understand that the embodiments described in this invention can be considered as optional embodiments, that is, the actions or modules involved are not necessarily essential for the implementation of one or more solutions of this invention. In addition, depending on the solution, the description of some embodiments of this invention also has different emphases. In view of this, those skilled in the art will understand that parts not described in detail in a certain embodiment of this invention can also refer to the relevant descriptions of other embodiments.

[0190] In terms of specific implementation, based on the disclosure and teachings of this invention, those skilled in the art will understand that the several embodiments disclosed herein can also be implemented in other ways not disclosed herein. For example, regarding the various units in the SMMU or device embodiments described above, this document has divided them based on logical functions, but in actual implementation, there may be other ways of division. As another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. Regarding the connection relationships between different units or components, the connections discussed above in conjunction with the accompanying drawings can be direct or indirect couplings between units or components. In some scenarios, the aforementioned direct or indirect couplings involve communication connections utilizing interfaces, where the communication interface can support electrical, optical, acoustic, magnetic, or other forms of signal transmission.

[0191] In this invention, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same position or distributed across multiple network units. Furthermore, depending on actual needs, some or all of the units can be selected to achieve the purpose of the solution described in the embodiments of this invention. Additionally, in some scenarios, multiple units in the embodiments of this invention may be integrated into one unit or each unit may exist physically independently.

[0192] In other implementation scenarios, the integrated units described above can also be implemented in hardware, i.e., as specific hardware circuits, which may include digital circuits and / or analog circuits. The physical implementation of the circuit's hardware structure may include, but is not limited to, physical devices, which may include, but are not limited to, transistors or memristors. Therefore, the various devices described herein (e.g., computing devices or other processing devices) can be implemented using appropriate hardware processors, such as central processing units, GPUs, FPGAs, DSPs, and ASICs. Furthermore, the aforementioned storage unit or storage device can be any suitable storage medium (including magnetic storage medium or magneto-optical storage medium, etc.), such as resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), ROM and RAM, etc.

[0193] The foregoing can be better understood in accordance with the following terms:

[0194] Clause 1. A page table prefetching method, comprising:

[0195] Receive the virtual address and obtain the trigger address range for prefetching the page table;

[0196] If the received virtual address falls within the trigger address range, then the page table within the set range is stored in the page table cache; and

[0197] Update the setting range; the updated setting range will be used for the next page table prefetch.

[0198] Clause 2. The method described in Clause 1, wherein the method comprises:

[0199] The trigger address range is determined based on the preset threshold, prefetch direction, and address boundaries.

[0200] 3. As described in Clause 2, determining the trigger address range based on a preset threshold, prefetch direction, and address boundaries includes:

[0201] If the prefetch direction is increasing, then the value of the address boundary minus the threshold is used as the starting address, and the address boundary is used as the ending address;

[0202] The trigger address range is determined based on the start address and the end address.

[0203] 4. According to the method described in Clause 3, the step of storing the page table within the set range into the page table cache if the received virtual address belongs to the trigger address range includes:

[0204] If the received virtual address belongs to the trigger address range, then the address boundary is used as the starting prefetch address, and the address boundary plus the prefetch length is used as the ending prefetch address.

[0205] Store the page table within the range from the start prefetch address to the end prefetch address in the page table cache.

[0206] 5. As described in Clause 2, determining the trigger address range based on a preset threshold, prefetch direction, and address boundaries includes:

[0207] If the prefetch direction is decreasing, then the address boundary is used as the starting address, and the value of the threshold plus the address boundary is used as the ending address.

[0208] The trigger address range is determined based on the start address and the end address.

[0209] 6. According to the method described in Clause 5, if the received virtual address belongs to the trigger address range, then storing the page table within the set range into the page table cache includes: using the address boundary minus the prefetch length as the starting prefetch address, and using the address boundary as the ending prefetch address;

[0210] Store the page table within the range from the start prefetch address to the end prefetch address in the page table cache.

[0211] 7. The method described in Clause 1 further includes:

[0212] The trigger address range is updated based on the preset threshold, prefetch direction, and address boundaries.

[0213] 8. As described in Clause 7, updating the trigger address range based on a preset threshold, prefetch direction, and address boundaries includes:

[0214] When the prefetch direction is increasing, the address boundary is updated to the sum of the address boundary and the prefetch length; wherein, the prefetch length is used to determine the set range;

[0215] The trigger address range is updated based on the updated address boundaries, the preset threshold, and the prefetch direction.

[0216] 9. As described in Clause 7, updating the trigger address range based on a preset threshold, prefetch direction, and address boundaries includes:

[0217] When the prefetch direction is decreasing, the address boundary is updated to the difference between the address boundary and the prefetch length; wherein, the prefetch length is used to determine the set range;

[0218] The trigger address range is updated based on the updated address boundaries and the preset threshold.

[0219] 10. The method described in Clause 1 further includes:

[0220] The trigger address range is updated based on the preset transition length, prefetch direction, and address boundaries.

[0221] 11. The method described in Clause 10, wherein updating the trigger address range based on a preset transition length, prefetch direction, and address boundary includes:

[0222] When the prefetch direction is increasing, the address boundary is updated to the sum of the address boundary and the preset transition length;

[0223] The trigger address range is updated based on the updated address boundaries and the preset threshold.

[0224] 12. The method described in Clause 10, wherein updating the trigger address range based on a preset threshold, prefetch direction, and address boundary includes:

[0225] When the prefetch direction is decreasing, the address boundary is updated to the difference between the address boundary and the preset transition length;

[0226] The trigger address range is updated based on the updated address boundaries and the preset threshold.

[0227] 13. The method described according to any one of clauses 1-12, wherein updating the set range includes:

[0228] The set range is updated based on the prefetch length, prefetch direction, and address boundaries.

[0229] 14. The method described according to any one of clauses 1-12 further includes prefetching conditions;

[0230] If the received virtual address belongs to the trigger address range and meets the prefetch condition, then the step of storing the page table within the set range into the page table cache is executed.

[0231] If the enable signal representation can be automatically prefetched and the total prefetch length is greater than 0, then the prefetch condition is determined to be satisfied.

[0232] 15. The method according to Clause 14, further comprising:

[0233] When a page table cache miss occurs, or when a passive prefetch request is received, the initial value of the total prefetch length is determined.

[0234] After storing the page tables within the set range into the page table cache, the total prefetch length is updated until the total prefetch length is reduced to 0.

[0235] 16. The method according to Clause 1, further comprising:

[0236] Determine the prefetch conditions based on the received passive prefetch request.

[0237] 17. A storage management unit,

[0238] The storage management unit includes:

[0239] Page table cache is used to store page tables;

[0240] The controller is used to receive virtual addresses and obtain the trigger address range of page tables. If the received virtual address belongs to the trigger address range, the prefetch length stores the page tables within the set range into the page table cache; and updates the set range, the updated set range is used for the next prefetch of page tables.

[0241] 18. A chip comprising the memory management unit described in Clause 17.

[0242] 19. A computer-readable storage medium having a computer program stored thereon,

[0243] The computer program is executed by a processor to implement the method as described in any one of Clauses 1-16.

[0244] 20. A computer program product comprising a computer program that, when executed by a processor, implements the method according to any one of claims 1-16.

[0245] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0246] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A page table prefetching method, characterized in that, include: Receive a virtual address and obtain a trigger address range for prefetching page tables; wherein the trigger address range is determined based on a preset threshold, prefetch direction, and address boundaries; If the received virtual address falls within the trigger address range, then the page table within the set range is stored in the page table cache; and Update the address boundaries to update the set range, and the updated set range is used for the next prefetch page table; If the received virtual address falls within the trigger address range, then the page tables within the set range are stored in the page table cache, including: When the prefetch direction is incremental, if the received virtual address belongs to the trigger address range, the address boundary is used as the starting prefetch address, and the value of the address boundary plus the prefetch length is used as the ending prefetch address; the page table within the range from the starting prefetch address to the ending prefetch address is stored in the page table cache; When the prefetch direction is decreasing, the value of the address boundary minus the prefetch length is used as the starting prefetch address, and the address boundary is used as the ending prefetch address; the page table within the range of the starting prefetch address to the ending prefetch address is stored in the page table cache.

2. The method according to claim 1, characterized in that, Determining the trigger address range based on a preset threshold, prefetch direction, and address boundaries includes: If the prefetch direction is increasing, then the value of the address boundary minus the threshold is used as the starting address, and the address boundary is used as the ending address; The trigger address range is determined based on the start address and the end address.

3. The method according to claim 1, characterized in that, Determining the trigger address range based on a preset threshold, prefetch direction, and address boundaries includes: If the prefetch direction is decreasing, then the address boundary is used as the starting address, and the value of the threshold plus the address boundary is used as the ending address. The trigger address range is determined based on the start address and the end address.

4. The method according to claim 1, characterized in that, Also includes: The trigger address range is updated based on the preset threshold, prefetch direction, and address boundaries.

5. The method according to claim 4, characterized in that, The trigger address range is updated based on a preset threshold, prefetch direction, and address boundaries, including: When the prefetch direction is increasing, the address boundary is updated to the sum of the address boundary and the prefetch length; wherein, the prefetch length is used to determine the set range; The trigger address range is updated based on the updated address boundaries, the preset threshold, and the prefetch direction.

6. The method according to claim 4, characterized in that, The trigger address range is updated based on a preset threshold, prefetch direction, and address boundaries, including: When the prefetch direction is decreasing, the address boundary is updated to the difference between the address boundary and the prefetch length; wherein, the prefetch length is used to determine the set range; The trigger address range is updated based on the updated address boundaries and the preset threshold.

7. The method according to claim 1, characterized in that, Also includes: The trigger address range is updated based on the preset transition length, prefetch direction, and address boundaries.

8. The method according to claim 7, characterized in that, The step of updating the trigger address range based on the preset transition length, prefetch direction, and address boundaries includes: When the prefetch direction is increasing, the address boundary is updated to the sum of the address boundary and the preset transition length; The trigger address range is updated based on the updated address boundaries and the preset threshold.

9. The method according to claim 7, characterized in that, The step of updating the trigger address range based on the preset transition length, prefetch direction, and address boundaries includes: When the prefetch direction is decreasing, the address boundary is updated to the difference between the address boundary and the preset transition length; The trigger address range is updated based on the updated address boundaries and the preset threshold.

10. The method according to any one of claims 1-9, characterized in that, Updating the set range includes: The set range is updated based on the prefetch length, prefetch direction, and address boundaries.

11. The method according to any one of claims 1-9, characterized in that, It also has prefetching conditions set; If the received virtual address belongs to the trigger address range and meets the prefetch condition, then the step of storing the page table within the set range into the page table cache is executed. If the enable signal representation can be automatically prefetched and the total prefetch length is greater than 0, then the prefetch condition is determined to be satisfied.

12. The method according to claim 11, characterized in that, The method further includes: When a page table cache miss occurs, or when a passive prefetch request is received, the initial value of the total prefetch length is determined. After storing the page tables within the set range into the page table cache, the total prefetch length is updated until the total prefetch length is reduced to 0.

13. The method according to claim 1, characterized in that, The method further includes: Determine the prefetch conditions based on the received passive prefetch request.

14. A storage management unit, characterized in that, The storage management unit includes: Page table cache is used to store page tables; The controller is used to receive virtual addresses and obtain the trigger address range of page tables. If the received virtual address belongs to the trigger address range, the controller stores the page tables within the set range into the page table cache. The controller also updates the address boundaries to update the set range. The updated set range is used for the next page table prefetch. The trigger address range is determined based on a preset threshold, prefetch direction, and address boundaries. Specifically, when the prefetch direction is increasing, if the received virtual address belongs to the trigger address range, the controller uses the address boundary as the starting prefetch address and adds the prefetch length to the address boundary as the ending prefetch address; and stores the page table within the range from the starting prefetch address to the ending prefetch address in the page table cache. When the prefetch direction is decreasing, the controller uses the address boundary minus the prefetch length as the starting prefetch address and uses the address boundary as the ending prefetch address; and stores the page table within the range from the starting prefetch address to the ending prefetch address in the page table cache.

15. A chip, characterized in that, The chip includes the memory management unit as described in claim 14.

16. A computer-readable storage medium, characterized in that, It contains computer programs. The computer program is executed by a processor to implement the method as described in any one of claims 1-13.

17. A computer program product comprising a computer program that, when executed by a processor, implements the method according to any one of claims 1-13.

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