Chip layout method and device, electronic equipment and storage medium

Abstract

The application provides a chip layout method, a chip layout device, an electronic device and a computer readable storage medium. The method comprises the following steps: determining a function module corresponding to a target unit according to the name of the target unit; searching units of a chip to find associated units associated with the target unit; and laying out the target unit and the associated units in a region corresponding to the function module. According to the application, the units associated with each other can be laid out in the same region, the overall performance is improved, and the delay is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip design, and in particular, to a chip layout method, a chip layout device, an electronic device, and a computer readable storage medium. BACKGROUND

[0002] It is known in the art of chip design to layout cells in a chip. In existing layout operations, only cells that can be identified as belonging to a certain functional module are placed in a certain area, without considering their associated cells. This often results in associated cells being placed far apart, causing an increase in overall latency. SUMMARY

[0003] To this end, the present application provides a chip layout method, a chip layout device, an electronic device, and a computer readable storage medium, which can place associated cells in the same area, reducing overall latency.

[0004] In one aspect, the present application provides a chip layout method, comprising: determining a functional module corresponding to a target cell according to a name of the target cell; searching cells of a chip to find associated cells associated with the target cell; and placing the target cell and the associated cells in an area corresponding to the functional module.

[0005] According to a particular embodiment of the present application, searching cells of a chip to find associated cells associated with a target cell comprises: performing a first-level search on the cells of the chip to find a plurality of first-level associated cells directly associated with the target cell; and performing a second-level search on the cells of the chip to find a plurality of second-level associated cells directly associated with each of the first-level associated cells.

[0006] According to a particular embodiment of the present application, performing a second-level search on the cells of the chip to find a plurality of second-level associated cells directly associated with each of the first-level associated cells comprises: when the number of second-level associated cells found by the second-level search for a first-level associated cell exceeds a certain value, discarding the second-level search result for the first-level associated cell.

[0007] According to a particular embodiment of the present application, the certain value is between 5 and 15.

[0008] According to a particular embodiment of the present application, the certain value is 10.

[0009] According to a particular embodiment of the present application, the target cell comprises a register.

[0010] According to a particular embodiment of the present application, the associated cells comprise one or more of a register, a lookup table, an adder, and a multiplexer.

[0011] In another aspect, the present application provides a chip layout device, comprising: a determining module configured to determine a function module corresponding to a target cell according to a name of the target cell; a searching module configured to search cells of a chip to find associated cells associated with the target cell; and a layout module configured to layout the target cell and the associated cells in an area corresponding to the function module.

[0012] In another aspect, the present application provides an electronic device, comprising: a processor; a memory; and an application stored in the memory and configured to be executed by the processor, the application comprising instructions for executing the chip layout method.

[0013] In another aspect, the present application provides a computer readable storage medium storing a computer program for executing the chip layout method.

[0014] According to the present application, the area where a target cell is placed is determined by easily identifying the function module of the target cell, and the cells associated with the target cell are also placed in the area by searching, so that the cells associated with each other are placed in the same area, which is beneficial to reduce delay and improve overall performance. BRIEF DESCRIPTION OF DRAWINGS

[0015] Hereinafter, a specific embodiment of the present application will be described in detail with reference to the accompanying drawings, in which:

[0016] Figure 1 Fig. 1 shows a flowchart of a chip layout method according to an embodiment of the present application;

[0017] Figure 2 Fig. 3 shows a schematic diagram of a search result according to an embodiment of the present application; Figure 1

[0018] Figure 3 Fig. 5 shows a schematic diagram of a chip layout device according to an embodiment of the present application;

[0019] Figure 4 Fig. 6 shows a schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0020] In order to make those skilled in the art more clearly understand the concepts and ideas of the present application, the present application will be described in detail below in conjunction with specific embodiments. It should be understood that the embodiments given herein are only a part of all possible embodiments of the present application. Those skilled in the art can make improvements, modifications or replacements to part or all of the following embodiments after reading the description of the present application, and these improvements, modifications or replacements are also included in the scope of protection of the present application.

[0021] ​In this document, the terms "a," "an," and "the" are not intended to refer to only a singular entity, but include the general class of which a specific example can be used for illustration. The terms "comprising," "including," and "having" are intended to be open-ended transitional phrases that are not intended to limit the scope of the claims to the elements or steps listed. For example, a process, method, implementation, or apparatus that "comprises," "includes," or "has" a list of elements or steps is not necessarily limited to those elements or steps. Additional elements or steps can be included.

[0022] In this document, the terms "first," "second," and other similar referents are used to distinguish one element from another, and are not intended to imply any order or priority. In this document, the terms "example," "exemplary," and "exemplification" are used to illustrate at least one example of an implementation, and are not intended to limit the scope of the claims to the specific example. One of ordinary skill in the art will understand that any of the descriptions of one implementation can be replaced, combined, or otherwise combined with any of the descriptions of another implementation, and that the resulting new implementation is within the scope of the claims.

[0023] In the embodiments of the present application, a chip can refer to an integrated circuit, or a microcircuit, a microchip, a wafer / chip, which is a way of miniaturizing an electronic circuit (mainly including semiconductor devices, and also including passive components, etc.), and is often manufactured on the surface of a semiconductor wafer. For example, a chip can include a central processing unit (CPU), a graphics processing unit (GPU), a memory, a field programmable gate array (FPGA), etc.

[0024] In embodiments of the present application, chip layout can refer to a step in chip design. Chip design usually includes front-end design and back-end design; front-end design can include RTL (Register Transfer Level) design, verification, static timing analysis, coverage, and logic synthesis; back-end design can include logic synthesis, formal verification, physical implementation (including floor plan, place, and route), clock tree synthesis, parasitic extraction, and layout physical verification. For example, chip design can include main steps such as function definition, device selection, design input, functional simulation, synthesis optimization, post-synthesis simulation, layout, routing, post-simulation, board-level simulation, and chip programming and debugging.

[0025] In embodiments of the present application, chip layout can refer to placing standard cells, I / O pads, and macro cells to implement the entire circuit logic. For example, chip layout can refer to placing macro cell modules of the chip, and generally determining the placement positions of various functional circuits, such as IP modules, RAM, I / O pins, and the like, and layout can directly affect the final area of the chip. The input of layout can be the netlist information after packaging, the constraint information of the chip, and the user-defined constraint information, including the physical constraints written in the user constraint file and the delay constraints written in the design constraint file, and the output of layout can be the netlist after layout, for automatic router to route. Chip layout can usually include input / output layout, global clock layout, initial layout, overall layout, legalization layout, and detailed layout. For example, the process of layout generally includes global layout, legalization layout, and detailed layout. In some layout processes, layout also includes region layout, that is, region division is performed on some specified functional modules in the design.

[0026] In EDA (Electronic Design Automation, electronic design automation) design engineering, some units are often regionally laid out, the purpose of which is to divide some specified functional modules in the design into regions, so that the positions of the units in a group of functional modules are relatively close to each other, so that the work is more stable, and the performance can also achieve the expected effect. The REG (register) units in the netlist generated in the synthesis step can basically be identified by the name of the corresponding functional module. If regional layout is used in the layout process after synthesis, the REG units of the easily distinguishable functional modules are often constrained to a specified region. For some designs, by specifying some REGs for regional layout, the result is sometimes not ideal, and the root cause is that some other non-REG units associated with the REGs in the region are placed far apart, resulting in a large delay between them. In view of this situation, the method of region extension search is adopted to regard the units associated with the REGs in the region as units in the region.

[0027] Figure 1 A flowchart of a chip layout method according to an embodiment of the application is shown.

[0028] According to the embodiment, the chip layout method includes steps S110 to S130, and each step is described in detail below.

[0029] S110, according to the name of the target unit, determine the functional module corresponding to the target unit.

[0030] The target unit can refer to a chip unit that can be used to identify the functional module to which it belongs. In the chip design process, before the chip layout step, the netlist generated by logic synthesis gives each unit or unit certain information. For example, each register is assigned a name. According to the name of the register, the corresponding functional module can be determined.

[0031] As an example, the target unit includes a register.

[0032] S120, search for units of the chip to find associated units associated with the target unit.

[0033] Searching for units of the chip can mean performing a search operation in the netlist file to find a specific unit. The associated units associated with the target unit can refer to units directly associated with the target unit (directly connected, as an input source or output object), or can refer to units indirectly associated with the target unit (there are other units in between, as the associated units of the units directly associated with the target unit).

[0034] As an example, the association unit comprises one or more of a register, a look-up table, an adder, a multiplexer.

[0035] The register can refer to a commonly used sequential logic circuit, but such a sequential logic circuit only contains a storage circuit. The storage circuit of the register is composed of a latch or a flip-flop, because a latch or a flip-flop can store a 1-bit binary number, so N latches or flip-flops can be used to form an N-bit register.

[0036] The look-up table (LUT) can refer to a data structure that replaces an array of runtime calculations with a simple query operation.

[0037] The adder (ADD) can refer to a device that generates the sum of numbers. The adder is a half adder, which takes the summand and the addend as input, and the sum and the carry as output. If the addend, the summand, and the low-bit carry are input, and the sum and the carry are output, it is a full adder. It is commonly used as a computer arithmetic logic unit to perform logical operations, shifting, and instruction calls.

[0038] The multiplexer (MUX) can refer to a circuit that can select any one of the multiple data transmission paths as needed during multi-path data transmission, used to achieve channel expansion or multiplexing purposes.

[0039] As an example, S120 can include a primary search and a secondary search, wherein the primary search can refer to a primary search on the units of the chip to find a plurality of primary association units directly associated with the target unit, and the secondary search can refer to a secondary search on the units of the chip to find a plurality of secondary association units directly associated with each of the plurality of primary association units.

[0040] As an example, when the number of the plurality of secondary association units found by the secondary search for the primary association unit exceeds a specific value, the secondary search result for the primary association unit is abandoned.

[0041] As an example, the specific value is between 5 and 15, for example, the specific value is 10.

[0042] In the embodiment, the method of area expansion search can be used to treat the cells associated with the REG in the area as the cells in the area. The area expansion search is divided into two levels of search. The user and the developer can set the first level of search or the second level of search by controlling the variable. The first level of search is to find the cells associated with the REG before and after the area and treat the cells as the cells in the area layout. The second level of search is to find the cells associated with the cells before and after the cells based on the first level of search (the cells before and after the REG) and treat the cells in the first level of search and the cells in the second level of search as the cells in the area layout. In the second level of search, the number of fanout can be limited to control the search range. For example, the number of fanout is limited to 10. If the number of cells reached by the output signal of a cell in the first level of search is greater than 10, the second level of search of the output of the cell is ignored.

[0043] As an example, Figure 2 The cells in the first level of search and the second level of search corresponding to a REG in the area are shown in the area. The cell in the middle of the first row is the REG. In each cell, in represents the input port and out represents the output port. The cell marked 1 is the result cell in the first level of search. The cell marked 2 is the result cell in the second level of search. The advantage of this method is that the overall performance after the area layout can be improved.

[0044] S130, the target cell and the associated cell are laid out in the area corresponding to the functional module.

[0045] In the embodiment, the specific functional module has a specific chip area. After the name of the target cell is determined, the target cell and the searched associated cell are arranged in the area corresponding to the functional module, which is beneficial to reduce the delay.

[0046] Figure 3 The structure schematic diagram of the chip layout device according to an embodiment of the application is shown.

[0047] According to the embodiment, the chip layout device 300 comprises:

[0048] The determining module 310 is configured to determine the functional module corresponding to the target cell according to the name of the target cell.

[0049] The searching module 320 is configured to search the cells of the chip and find the associated cells associated with the target cell.

[0050] The layout module 330 is configured to lay out the target cell and the associated cell in the area corresponding to the functional module.

[0051] In an embodiment, the searching module 320 is further configured to:

[0052] Perform a first-level search on the chip's cells to find multiple first-level related cells that are directly associated with the target cell;

[0053] A secondary search is performed on the chip's cells to find multiple secondary related cells that are directly associated with each of the multiple primary related cells.

[0054] In one embodiment, the search module 320 is further configured to:

[0055] If the number of secondary related units found by a secondary search for a primary related unit exceeds a certain value, the secondary search results for the primary related unit are abandoned.

[0056] In one embodiment, the specific value is between 5 and 15.

[0057] In one embodiment, the specific value is 10.

[0058] In one embodiment, the target unit includes a register.

[0059] In one embodiment, the associated unit includes one or more of a register, a lookup table, an adder, and a multiplexer.

[0060] The following combination Figure 4 This application describes an electronic device according to an embodiment of the present application.

[0061] like Figure 4 As shown, the electronic device 400 includes one or more processors 410 and memory 420.

[0062] The processor 410 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 400 to perform desired functions.

[0063] The memory 420 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 410 may execute the program instructions to implement the chip layout methods of the various embodiments of this application described above and / or other desired functions.

[0064] In one example, the electronic device 400 can further include an input device 430 and an output device 440, which are interconnected through a bus system and / or other form of connection mechanism (not shown).

[0065] For example, the input device 430 can be a microphone or microphone array for capturing voice input signals; can be a communication network connector for receiving captured input signals from the cloud or other devices; and can further include, for example, a keyboard, a mouse, and the like.

[0066] The output device 440 can output various information, including determined distance information, direction information, and the like, to the outside. The output device 440 can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0067] Of course, in order to simplify, Figure 4 In the figure, only some of the components related to the present application among the components of the electronic device 400 are shown, and components such as buses, input / output interfaces, and the like are omitted. In addition to this, the electronic device 400 can further include any other appropriate components according to the specific application.

[0068] Embodiments of the present application can also be a computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, cause the processor to perform the steps described above in the chip layout method according to various embodiments of the present application.

[0069] The computer readable storage medium can be any combination of one or more computer readable medium(s). The computer readable medium can be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination of the above. More specific examples (a non-exhaustive list) of the computer readable storage medium include an electrical connection having one or more wires, a portable disc, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0070] The concepts, principles and ideas of the present application are described in detail above in combination with specific implementation manners (including examples and instances). It should be understood by those skilled in the art that the implementation manners of the present application are not limited to the above-mentioned forms, and those skilled in the art can make any possible improvements, replacements and equivalent forms to the steps, methods, devices and components in the above-mentioned implementation manners after reading the present application file, and these improvements, replacements and equivalent forms should be considered to fall within the scope of the present application. The protection scope of the present application is only subject to the claims.

Claims

1. A chip layout method, comprising: determining a function module corresponding to a target cell according to a name of the target cell; the function module has a corresponding chip area; searching cells of the chip to find associated cells associated with the target cell; laying out the target cell and the associated cells in the area corresponding to the function module; wherein the target cell refers to a register that can be used to identify the function module to which it belongs; the associated cell refers to one or more of a lookup table, an adder, and a multiplexer that is directly or indirectly associated with the target cell.

2. The chip layout method of claim 1, wherein, The searching cells of the chip to find associated cells associated with the target cell comprises: performing a first-level search on the cells of the chip to find a plurality of first-level associated cells directly associated with the target cell; performing a second-level search on the cells of the chip to find a plurality of second-level associated cells directly associated with each of the plurality of first-level associated cells.

3. The chip layout method of claim 2, wherein, The performing a second-level search on the cells of the chip to find a plurality of second-level associated cells directly associated with each of the plurality of first-level associated cells comprises: when the number of the plurality of second-level associated cells found by the second-level search for the first-level associated cell exceeds a specific value, abandoning the second-level search result for the first-level associated cell.

4. The chip layout method of claim 3, wherein, The specific value is between 5 and 15.

5. The chip layout method of claim 4, wherein, The specific value is 10. 6.A chip layout apparatus, comprising: a determining module configured to determine a function module corresponding to a target cell according to a name of the target cell; the function module has a corresponding chip area; a searching module configured to search cells of the chip to find associated cells associated with the target cell; a layout module configured to lay out the target cell and the associated cells in the area corresponding to the function module; wherein the target cell refers to a register that can be used to identify the function module to which it belongs; the associated cell refers to one or more of a lookup table, an adder, and a multiplexer that is directly or indirectly associated with the target cell. 7.An electronic device, comprising: a processor; a memory; an application stored in the memory and configured to be executed by the processor, the application comprising instructions for performing the chip layout method according to any one of claims 1 to 5. 8.A computer-readable storage medium storing a computer program for performing the chip layout method according to any one of claims 1 to 5.

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