Memory devices and their operation methods

Abstract

This disclosure provides a memory device and its operation method, wherein the operation method includes the following steps: Multiple input values ​​for model operation are received via multiple first word lines of a memory array. Inverted logic values ​​of these input values ​​are received via multiple second word lines. These input values ​​are received via multiple first bit lines. Inverted logic values ​​are received via multiple second bit lines. An XOR operation is performed on each input value and each inverted logic value to obtain a first operation result, which is then multiplied by one of the self-multiplication coefficients or one of the interaction coefficients of the model operation to obtain multiple output values. These output values ​​are output via multiple common-source lines.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a computational method performed using the semiconductor device, and more particularly to a memory device and a computational method for processing model computations using the memory device. Background Technology

[0002] In today's era of rapid technological advancement, daily life is inextricably linked to big data. Models can be constructed based on various parameters within big data, and then these models can be used to provide solutions to specific problems. For example, for the common problem of travel route planning, model calculations can be used to locate the shortest travel route.

[0003] On the other hand, in the fields of electronics and semiconductors, model calculations are often used to adjust the process parameters or condition factors of electronic devices or semiconductor components. However, complex electronic devices or semiconductor components involve a large number of parameters or factors, thus requiring complex model calculations, which are time-consuming, energy-intensive, or costly in terms of hardware. Therefore, those skilled in the art are dedicated to developing technical solutions for more efficient model calculations.

[0004] Public content

[0005] This disclosure provides a memory device including a memory array for processing a model operation, the model operation having multiple input values, multiple multiplication coefficients, multiple interaction coefficients, and multiple output values. The memory array includes multiple first word lines and multiple second word lines, multiple first bit lines and multiple second bit lines, multiple common-source lines, and multiple memory cells. Each memory cell receives input values ​​via the first word lines, receives inverted logic values ​​of the input values ​​via the second word lines, receives input values ​​via the first bit lines, receives inverted logic values ​​via the second bit lines, and outputs these output values ​​via the common-source lines. Each memory cell performs an XNOR operation on each input value and each inverted logic value to obtain a first operation result, and multiplies the first operation result by one of the multiplication coefficients or one of the interaction coefficients to obtain an output value.

[0006] This disclosure also provides a computation method, comprising the following steps: Input values ​​for a model operation are received via multiple first word lines of a memory array. Inverted logic values ​​of the input values ​​are received via multiple second word lines of the memory array. These input values ​​are received via multiple first bit lines of the memory array. These inverted logic values ​​are received via multiple second bit lines of the memory array. An XOR operation is performed on each input value and each inverted logic value to obtain a first operation result. The first operation result is multiplied by one of a plurality of self-multiplication coefficients or one of a plurality of interaction coefficients of the model operation to obtain a plurality of output values ​​of the model operation. These output values ​​are output via multiple common-source lines of the memory array.

[0007] Other aspects and advantages of this disclosure will become apparent from the following figures and detailed description. Attached Figure Description

[0008] Figure 1A , 1B This is a schematic diagram of the Ising model with input values.

[0009] Figure 2A This is a schematic diagram for calculating energy using the Ising model.

[0010] Figure 2B A schematic diagram illustrating the use of the Ising model to simulate quantum annealing.

[0011] Figure 3A This is a block diagram of the computing device disclosed herein for processing Ising model operations.

[0012] Figure 3B This is a circuit diagram of a memory device for processing Ising model operations according to an embodiment of the present disclosure.

[0013] Figure 3C for Figure 3B The circuit diagram of one of the memory cells in the memory array.

[0014] Figure 3D for Figure 3B The circuit diagram of another storage cell in the memory array.

[0015] Figure 4A for Figure 3B A simplified diagram illustrating the processing of Ising model operations by a memory device.

[0016] Figure 4B , 4C for Figure 3B An example of a computational implementation of a memory device for processing Ising model operations.

[0017] Figure 5AThis is a circuit diagram of a memory device for processing Ising model operations according to another embodiment of the present disclosure.

[0018] Figure 5B for Figure 5A A simplified diagram illustrating the processing of Ising model operations by a memory device.

[0019] Figure 6A , 6B for Figure 5A An example of a computational implementation of a memory device for processing Ising model operations.

[0020] Figure 7 This is a circuit diagram of a memory device for processing Ising model operations according to yet another embodiment of the present disclosure.

[0021] Figure 8 This is a circuit diagram of a memory device for processing Ising model operations according to another embodiment of the present disclosure.

[0022] Figure 9 This is a circuit diagram of a memory device for processing Ising model operations according to another embodiment of the present disclosure.

[0023] Figure 10 This is a circuit diagram of a memory array for processing Ising model operations according to another embodiment of this disclosure.

[0024] Figure 11 This is a circuit diagram of a memory array for processing Ising model operations, according to yet another embodiment of this disclosure.

[0025] Figure 12 This is a circuit diagram of a memory device for processing Ising model operations according to another embodiment of the present disclosure.

[0026] Figures 13A-13D for Figure 3B A flowchart of the computation method for processing the Ising model operations using a memory device.

[0027] Explanation of reference numerals in the attached figures

[0028] 30(1,1)~30(4,4), 30(i,j): Storage units

[0029] 50(1,1)~50(5,4), 50(i,j): Storage units

[0030] 70(1,1)~70(1,6): Storage units

[0031] 80(1,1)~80(1,8): Storage units

[0032] 100(1,1): Storage unit

[0033] 110-1, 110-N, 902, 904: Memory subarrays

[0034] 122, 124, 126, 128, 130: Routing circuits

[0035] 200, 202, 204, 206: Configuration

[0036] 300: Computing device

[0037] 300B, 500, 700, 800, 900, 1200: Memory devices

[0038] 120-1, 120-4, 302, 502, 702, 802, 1002, 1102: Memory arrays

[0039] 304, 504: Summation circuit

[0040] 310: Spin State Calculator

[0041] 320: Circuit Update

[0042] 702, 704, 706, 712, 714, 716, 802: Analog-to-Digital Converters

[0043] 708, 718: Two-position translation device

[0044] 710, 720: One-digit translation device

[0045] Ma: First transistor

[0046] Mb: Second transistor

[0047] Ga: First gate

[0048] Da: First drain electrode

[0049] Sa: First Source Pole

[0050] Gb: Second gate

[0051] Db: Second drain electrode

[0052] Sb: Second source pole

[0053] V tha First threshold voltage

[0054] V thb First threshold voltage

[0055] V Ga First gate voltage

[0056] V Da First drain voltage

[0057] I Sa First source current

[0058] V Gb Second gate voltage

[0059] V Db Second drain voltage

[0060] I Sb Second source current

[0061] I S Common source current

[0062] WL1a~WL5a, WLia: First letter line

[0063] WL1b~WL5b, WLib: Second syllable line

[0064] BL1a~BL4a, BLja: First Line

[0065] BL1b~BL4b, BLjb: Second bit line

[0066] SL1~SL4, SLj: Common source lines

[0067] SL1-1, SL1-2, SL1-3: Common source lines

[0068] SL2-1, SL2-2, SL2-3: Common source lines

[0069] SA1~SA4, SAj: Induction amplifier

[0070] H1~H4, H j Total output value

[0071] H: Energy

[0072] H min Minimum Energy

[0073] H th Threshold

[0074] SP_IN(σ j ): Control signal

[0075] σ1~σ4, σ N , σ i , σ j Input value

[0076] σ1'~σ4', σ i ',σ j ': Reverse logical value

[0077] Pa ij Pbij P ij Output value

[0078] h1, h2, h3, h4, h i Self-multiplication coefficient

[0079] h1(1): First

[0080] h1(2): Second position

[0081] h1(3): Third position

[0082] h1(8): Eighth position

[0083] h1 + First component

[0084] h1 - Second component

[0085] J 12 J 13 J 14 J 23 J 24 J 34 J ij Interaction coefficient

[0086] J 12 (1): First

[0087] J 12 (2): Second position

[0088] J 12 (3): Third position

[0089] J 19 + First component

[0090] J 19 - Second component

[0091] T1: First Time

[0092] T2: Second Time

[0093] S110~S210, S161, S162, S161B, S162B, S163B: Steps Detailed Implementation

[0094] The technical terms used in this specification refer to those commonly used in the field. Where this specification provides further explanation or definition for certain terms, the interpretation of those terms shall be based on the explanation or definition provided in this specification. Each embodiment of this disclosure has one or more technical features. Where feasible, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

[0095] Figure 1A , 1B This is a schematic diagram of the Ising model, which has a spin state. Please refer to [link / reference needed]. Figure 1A The Ising model, for example, has two input values ​​σ1 and σ2. The first input value σ1 represents the first spin state of the Ising model, and the second input value σ2 represents the second spin state. The first input value σ1 is a logic value "1", indicating that the spin state is "positive spin". Figure 1A The upward arrow in the image indicates that the second input value σ2 is a logic value "0", which means the spin state is "reverse spin". Figure 1A (The downward arrow in the diagram). The first input value σ1 has a self-multiplying coefficient h1, the second input value σ2 has a self-multiplying coefficient h2, and there is an interaction coefficient J between the two input values ​​σ1 and σ2. 12 .

[0096] Furthermore, see Figure 1B Taking the Ising model with three input values ​​σ1, σ2, and σ3 as an example, the logical values ​​of the input values ​​σ1, σ2, and σ3 are, for example, "1, 0, 0". The input values ​​σ1, σ2, and σ3 have self-multiplication coefficients h1, h2, and h3, respectively; and the input values ​​σ1 and σ2 have an interaction coefficient J. 12 The input values ​​σ1 and σ3 have an interaction coefficient J. 13 The input values ​​σ2 and σ3 have an interaction coefficient J. 23 .

[0097] Figure 2A This is a schematic diagram illustrating the calculation of energy using the Ising model. Please refer to [link / reference]. Figure 2A The Ising model can be used to calculate the cost function and locate its minimum. For example, the Ising model uses the energy H of a specific material (e.g., a magnetic material) as the cost function and locates the minimum energy H. min .by Figure 1A Taking the Ising model with two input values ​​σ1 and σ2 as an example, according to the Ising model operation shown in equation (1), the energy H corresponding to different logic values ​​of the input values ​​σ1 and σ2 can be calculated:

[0098] H = ∑i＝1～2 h i σ i +∑ i＜j J ij (σ i *σ j )

[0099] =h1σ1+h2σ2+J 12 (σ1*σ2) (1)

[0100] The operator "*" in equation (1) represents the XNOR gate operation. If the input value σ i σ j If the input values ​​are the same (e.g., "1, 1" or "0, 0"), the result of the logical "XNOR" operation is "1". If the input value σ i σ j If the logical values ​​are distinct (e.g., "1, 0" or "0, 1"), the result of the logical "XNOR" operation is "0". Figure 2A In the embodiment shown, according to the operation of equation (1), it can be determined that the material has the lowest energy H when the input values ​​σ1 and σ2 are logic values ​​"1, 1". min Similarly, if the Ising model has three input values ​​σ1, σ2, and σ3, the energy H can be calculated according to the Ising model in equation (2):

[0101] H=h1σ1+h2σ2+h3σ3+J 12 (σ1*σ2)+J 13 (σ1*σ3)+J 23 (σ2*σ3) (2)

[0102] Figure 2B This is a schematic diagram illustrating the simulation of quantum annealing using the Ising model. Please see below. Figure 2B A computing device (e.g., a complementary metal-oxide-semiconductor (CMOS) semiconductor device) can perform operations based on the Ising model to simulate quantum annealing in order to locate the minimum value (lowest energy H) of the cost function (energy H). min ). Figure 2B The Ising model operation in the embodiment has, for example, N input values ​​σ1, σ2, ..., σ N And the input values ​​σ1, σ2, ..., σ for different logic values N This corresponds to different configurations: 200, 202, 204, and 206, etc. Configuration 200 represents the input values ​​σ1, σ2, ..., σ... N For logical values ​​"0, 1, ..., 1", a configuration of 204 represents the input values ​​σ1, σ2, ..., σN The logical values ​​are "1, 1, ..., 0", etc. The movement path in the Ising model operation is as follows: it can move from configuration 200 to configuration 202, then to configuration 204, and then locate configuration 204 which has the lowest energy H. min On the other hand, the quantum annealing operation moves from configuration 206 to configuration 204 to locate the lowest energy H. min Therefore, the result of the computational device performing the Ising model operation is the same as the result of the quantum annealing operation.

[0103] Figure 3A This is a block diagram of the computing device 300 for processing Ising model operations according to this disclosure. Please refer to [link / reference]. Figure 3A The arithmetic unit 300 includes a spin operator 310 and an update circuit 320. The spin operator 310, for example, performs Ising model operations on four input values ​​σ1 to σ4 to calculate the corresponding total output values ​​H1 to H4, which can be expressed as equation (3):

[0104] H j =h j σ j +∑ i，i＜j J ij (σ i *σ j j = 1, 2, 3, 4 (3)

[0105] Then, the updating circuit 320 can, according to the majority vote rule, compare each of the total output values ​​H1 to H4 with the threshold H. th Compare the values, if the j-th total output value H... j Greater than threshold H th Then the update circuit 320 sends back the control signal SP_IN(σ). j The j-th input value σ is updated by sending the spin state operator 310 to the spin state operator 310. j For example, input value σ j The logic value "1" is flipped to the logic value "0". Then, the spin state operator 310 adjusts the input value σ according to the updated input value. j The Ising model calculation is performed again for other input values ​​that retain their original logic values, and the update circuit 320 determines whether another update is needed until the lowest energy H is located. min .

[0106] In the technical solution disclosed herein, a semiconductor memory device can be used to implement a spin state arithmetic unit 310 to process Ising model calculations. Figure 3BThis is a circuit diagram of a memory device 300B for processing Ising model operations according to an embodiment of this disclosure. The memory device 300B of this embodiment is used, for example, to process an Ising model having four input values ​​σ1 to σ4 (i.e., four spin states). Please refer to... Figure 3B The memory device 300B includes a memory array 302, sensing amplifiers SA1 to SA4, and a summing circuit 304. The memory array 302 includes multiple memory cells 30(1,1) to 30(4,4), four first word lines WL1a to WL4a, four second word lines WL1b to WL4b, four first bit lines BL1a to BL4a, four second bit lines BL1b to BL4b, and four common source lines SL1 to SL4. Each of these memory cells 30(1,1) to 30(4,4) includes two transistors and is connected to one of the first word lines WL1a to WL4a, the second word lines WL1b to WL4b, the first bit lines BL1a to BL4a, the second bit lines BL1b to BL4b, and the common source lines SL1 to SL4.

[0107] Figure 3C for Figure 3B The circuit diagram of memory cells 30 (3, 4) of memory array 302 is shown in the attached diagram. Figure 3B , 3C The memory cell 30 (3, 4) includes a first transistor Ma and a second transistor Mb. The first gate Ga of the first transistor Ma is connected to the third first word line WL3a, the first drain Da is connected to the fourth first bit line BL4a, and the first source Sa is connected to the fourth common source line SL4. Similarly, the second gate Gb of the second transistor Mb is connected to the third second word line WL3b, the second drain Db is connected to the fourth second bit line BL4b, and the second source Sb is connected to the fourth common source line SL4. In this embodiment, the first source Sa of the first transistor Ma and the second source Sb of the second transistor Mb are directly interconnected in a common source configuration.

[0108] Figure 3D for Figure 3B The circuit diagram of memory cell 30(i, j) of memory array 302 is shown below. Figure 3B , 3D In operation, the first gate Ga of the first transistor Ma of memory cell 30(i,j) receives the first gate voltage V via the i-th first word line WLia. Ga The first drain Da receives the first drain voltage V via the j-th first bit line BLja.Da And the first source Sa outputs the first source current I. Sa To the j-th common source line SLj. Similarly, the second gate Gb of the second transistor Mb in memory cell 30(i,j) receives the second gate voltage V via the i-th second word line WLib. Gb The second drain Db receives the second drain voltage V via the j-th second bit line BLjb. Db And the second source Sb outputs the second source current I. Sb Up to the j-th common source line SLj. And, the first source current I of memory cell 30(i,j) Sa With the second source current I Sb The sum of these currents becomes the common source current I. S The output is on the common source line SLj.

[0109] Furthermore, the first transistor Ma has a first threshold voltage V. tha The first gate voltage V of the first transistor Ma. Ga First drain voltage V Da With the first source current I Sa The relationship between them can be expressed as in equation (4):

[0110]

[0111] According to equation (4), if the first gate voltage V Ga For a higher voltage value (e.g., 1.8V) and above the first threshold voltage V tha (For example, 0.6V) can turn on the channel of the first transistor Ma, and the first drain voltage V Da A higher voltage value (e.g., 1.5V) can drive the drain-source current, thus generating the first source current I. Sa First source current I Sa Positively correlated with the first gate voltage V Ga and the first threshold voltage V tha The difference between the first drain voltage V and the first drain voltage V Da The product of.

[0112] From a logical operation perspective, the first gate voltage V can be... Ga The input value σ corresponding to the Ising model i Where the independent variable "i" represents the i-th input value σ i (That is, the i-th spin state of the Ising model). This independent variable "i" also indicates that memory cell 30(i,j) is connected to the i-th first word line WLia. For example, the first gate voltage V of memory cell 30(3,4) GaCorresponding to the third input value σ3 of the Ising model, and the first transistor Ma of memory cell 30 (3, 4) is connected to the third first word line WL3a. If the first gate voltage V Ga For a higher voltage value (e.g., 1.8V) and above the first threshold voltage V tha (For example, 0.6V), then the first gate voltage V Ga The corresponding input value σ i The logic value is "1". If the first gate voltage V Ga For a lower voltage value (e.g., 0.3V) and below the first threshold voltage V tha Then the corresponding input value σ i It is the logical value "0".

[0113] Similarly, the first drain voltage V Da Corresponding to the input value σ j Where the independent variable "j" represents the j-th input value σ j (That is, the j-th spin state of the Ising model) This independent variable "j" also represents the connection of storage cell 30(i,j) to the j-th first bit line BLja. If the independent variable "j" is equal to the independent variable "i", then the input value σ j Same as input value σ i They are in the same spin state. If the first drain voltage V Da For higher voltage values ​​(e.g., 1.5V), the corresponding input value σ j = "1". If the first drain voltage V Da For a lower voltage value (e.g., 0.2V), the corresponding input value σ j = "0". Furthermore, the first source current I will also be set to "0". Sa The output value Pa corresponds to the logic value "1" or "0". ij .

[0114] According to equation (4), if the first gate voltage V Ga For higher voltage values ​​(input value σ) i = "1") and the first drain voltage V Da Also for higher voltage values ​​(input value σ) j = "1") can generate the first source current I Sa (Output value Pa) ij = "1"). From a logical operation perspective, the output value Pa ij For the input value σ i With input value σ j The result of the AND operation of the logical gate can be expressed as equation (5):

[0115] Pa ij =σ i ANDσj (5)

[0116] Furthermore, if the first transistor Ma is a floating gate transistor, then the first threshold voltage V tha It is adjustable. If the first threshold voltage V tha If the voltage is adjusted to a lower value (e.g., 0.2V), the input value σ i Input value σ j and output value Pa ij The relationship remains as equation (5). Conversely, if the first threshold voltage V... tha Adjusting to a higher voltage value (e.g., 2.0V) will affect the first gate voltage V. Ga A higher voltage value (e.g., 1.8V) or a lower voltage value (e.g., 0.3V) will not be able to turn on the channel of the first transistor Ma, and therefore the first source current I cannot be generated. Sa Therefore, the output value Pa ij It is always a logic value of "0". Therefore, the first threshold voltage V can be... tha One of the interaction coefficients J corresponding to the Ising model ij If the first threshold voltage V tha Adjusting to a lower voltage value (e.g., 0.2V) corresponds to the interaction coefficient J. ij = "1", if the first threshold voltage V tha Adjusting to a higher voltage value (e.g., 2.0V) corresponds to the interaction coefficient J. ij = "0". Furthermore, if the independent variables "i" and "j" are interchanged, the interaction coefficient J... ij Still equal to the interaction coefficient J ji The first threshold voltage V tha If the factors are taken into account, then the input value σ i Input value σ j and output value Pa ij The relationship between them can be expressed as equation (6):

[0117] Pa ij =J ij ×(σ i ANDσ j (6)

[0118] On the other hand, if the applied first gate voltage V Ga For a higher voltage value (e.g., 2.0V), the corresponding second gate voltage V applied to the second transistor Mb is... Gb This is a lower voltage value (e.g., 0.3V). From a logical operation perspective, the second gate voltage V of the second transistor Mb is... Gb Corresponding to the input value σ iThe inverse logic value σ i '.

[0119] Similarly, the second transistor Mb is subjected to a second drain voltage V. Db Corresponding to the input value σ j The inverse logic value σ j '. Furthermore, the second threshold voltage V of the second transistor Mb will also be... thb Corresponding to the interaction coefficient J ij And the second source current I Sb Corresponding to the output value Pb ij The output value Pbij is then the inverted logic value σ. i 'and the inverse logic value σ j The result of the logical AND operation is then multiplied by the interaction coefficient J. ij As shown in equation (7):

[0120] Pb ij =J ij ×(σ i 'ANDσ j ') (7)

[0121] Furthermore, the common-source current I output by storage cell 30(i,j) S The corresponding output value P ij Pa is the output value of the first transistor Ma. ij and the output value Pb of the second transistor Mb ij The sum. Output value P ij It can be expressed as equation (8):

[0122] P ij =Pa ij +Pb ij

[0123] =J ij ×(σ i ANDσ j )+J ij ×(σ i 'ANDσ j ')

[0124] =J ij ×(σ i XNORσ j ) = J ij ×(σ i *σ j (8)

[0125] From the above, the output value P of storage cell 30(i,j) on the common source line SLj is... ij For the input value σ i With input value σj The result of the logical "XNOR" operation and the interaction coefficient J ij The product of σ. That is, the first transistor Ma of memory cell 30(i,j) executes the input value σ. i With input value σ j The second transistor Mb performs an inverse logic value σ in the logical AND operation. i 'and the inverse logic value σ j The common-source line SLj performs a logical "OR" operation on the result of the logical "AND" operation of the first transistor Ma and the result of the logical "AND" operation of the second transistor Mb. The storage cell 30(i,j) performs two logical "AND" operations and one logical "OR" operation to achieve one logical "XNOR" operation.

[0126] Furthermore, the interaction coefficient J ij Not limited to logical "1" or logical "0" numbers, the interaction coefficient J ij It can also have simulated numerical values. As shown in Table 1, if the first threshold voltage V tha and the second threshold voltage V thb Set to any voltage value between zero (0V) and a high voltage value (e.g., 2.0V), then the corresponding interaction coefficient J ij It represents an analog value between the values ​​"0" and "1".

[0127] Table 1

[0128] <![CDATA[Interaction coefficient J ij > <![CDATA[First threshold voltage V tha > <![CDATA[Second threshold voltage V thb > 0 2.0V 2.0V 0.4 1.2V 1.2V 0.7 0.6V 0.6V 1 0V 0V

[0129] The above explains that a single storage unit 30(i, j) is used for a set of input values ​​σ. i σ j Performing one spin state operation, the following describes the overall operation of the entire memory array 302 for the four input values ​​σ1, σ2, σ3, and σ4. Please refer again. Figure 3B Common source lines SL1 to SL4 are respectively connected to inductive amplifiers SA1 to SA4. Taking the first inductive amplifier SA1 as an example, inductive amplifier SA1 can sum the common source currents output by all memory cells of the first common source line SL1 to sum all output values ​​of common source line SL1 into a total output value H1. Inductive amplifiers SA1 to SA4 are connected to summing circuit 304 to sum the total output values ​​H1 to H4 of common source lines SL1 to SL4 into energy H. Energy H is expressed as equation (9):

[0130] H = ∑ i＝1～4，i＜j [J ij ×(σ i *σ ij (9)

[0131] The energy H in equation (9) does not yet include the operation results of the memory cells 30(1,1), 30(2,2), 30(3,3), and 30(4,4) at the diagonal addresses of the memory array 302. For these memory cells at the diagonal addresses, taking memory cell 30(1,1) as an example, the input value σ1 received via the first word line WL1a is the same as the input value σ1 received via the first bit line BL1a. In this embodiment, the memory cells 30(1,1), 30(2,2), 30(3,3), and 30(4,4) at the diagonal addresses do not perform a logical "XNOR" operation on the input values ​​σ1 to σ4, but instead perform a logical "AND" operation. See again Figure 3D For example, the second threshold voltage V of the second transistor Mb of memory cell 30(i,j) (where i = j) can be... thb Setting a higher voltage value (e.g., 2.0V) keeps the channel of the second transistor Mb constantly off, thereby reducing the second source current I of the second transistor Mb. Sb The value is always zero, therefore the output value Pb of the second transistor Mb is zero. ii The value is always the logic value "0". At this time, the output value P of storage unit 30(i,j) (where i = j) is... ii Only includes the output value Pa of the first transistor Ma ii It can be expressed as equation (10):

[0132] P ii =Pa ii +Pb ii =Pa ii

[0133] =h i ×(σ i ANDσ i ) = h i *σ i (10)

[0134] In equation (10), the operational coefficients of the storage unit 30(i,j) at the diagonal address (where i = j) are not the interaction coefficients J. ij Instead, the self-multiplying coefficient h i According to equations (9) and (10), the sum of the operation results of all storage cells 30(1,1) to 30(4,4) of the memory array 302 is the energy H, which can be expressed as equation (11):

[0135] H = ∑ i＝1～4 (h i ×σ i )+∑ i＝1～4，i＜j [J ij ×(σ i *σj (11)

[0136] According to equation (11), the energy H calculated by the memory device 300B is consistent with the energy H calculated by the Ising model. Figure 4A for Figure 3B A simplified schematic diagram of the memory device 300B processing Ising model operations. Figure 4A The second character line and the second position line are omitted because only the first character line WL1a~WL4a and the first position line BL1a~BL4a are shown. For example... Figure 4A As shown, memory device 300B receives four input values ​​σ1 to σ4 via four first word lines WL1a to WL4a, and four input values ​​σ1 to σ4 via four first bit lines BL1a to BL4a. The operation coefficients for memory cells located at diagonal addresses in the memory array are multiplication coefficients h1, h2, h3, and h4. For memory cells outside the diagonal addresses, the operation coefficients for memory cells located at the first column address in the memory array are interaction coefficients J. 12 J 13 J 14 The operation coefficients of the second column address are the interaction coefficients J. 12 J 23 J 24 The operation coefficient of the third column address is the interaction coefficient J. 13 J 23 J 34 The operation coefficient of the fourth column address is the interaction coefficient J. 14 J 24 J 34 The memory device 300B in this embodiment can fully utilize the memory units with diagonal addresses for computation.

[0137] Figure 4B , 4C for Figure 3B An example of a computational operation performed by the memory device 300B on the Ising model. Figure 13A , 13B 13C is Figure 3B A flowchart illustrating the computational method for processing the Ising model using the memory device 300B. See also... Figure 4B and Figure 13A , 13B (and see also the supplementary reference) Figure 3D First, in step S110, at a first time T1, multiple input values ​​σ1 to σ4 from the Ising model operation are received via multiple first word lines WL1a to WL4a of the memory array 302. In this embodiment, the input values ​​σ1 to σ4 are "1, 1, 0, 1" respectively. More specifically, a first gate voltage V is applied via the i-th first word line WL1a. GaThe first transistor Ma in memory cell 30(i,j) has a first gate voltage V. Ga The input value σ corresponding to the i-th first word line WLia received i For example, a first gate voltage V is applied via the third first word line WL3a. Ga A first gate voltage V is applied to the first transistor Ma and the third first word line WL3a of memory cell 30 (3,1). Ga This corresponds to the third input value σ3 = "0".

[0138] Then, in step S120, the inverted logic values ​​σ1' to σ4' of the input values ​​σ1 to σ4 are respectively connected via the second word lines WL1b to WL4b. Figure 4B (Not shown in the image). For example, a second gate voltage V can be applied via the third second word line WL3b. Gb The second gate voltage V applied to the second transistor Mb in memory cell 30 (3, 1) Gb This corresponds to the inverted logic value σ3' received by the third second word line WL3b.

[0139] Next, in step S130, input values ​​σ1 to σ4 are received via the first bit lines BL1a to BL4a, respectively. More specifically, a first drain voltage V is applied via the j-th first bit line BLja. Da The first transistor Ma in memory cell 30(i,j). First drain voltage V. Da The input value σ corresponding to the first line BLja of the j-th line. j .

[0140] Next, in step S140, the inverted logic values ​​σ1' to σ4' of the input values ​​σ1 to σ4 are received via the second bit lines BL1b to BL4b, respectively. Figure 4B (Not shown in the image). For example, a second drain voltage V can be applied via the first second bit line BL1b. Db The second drain voltage V applied to the second transistor Mb in memory cell 30 (3, 1) Db This corresponds to the inverted logic value σ1' received by the first second bit line BL1b.

[0141] Next, in step S150, each storage unit 30(1,1) to 30(4,4) performs a logical "XNOR" operation based on each input value σ1 to σ4 and each inverse logic value σ1' to σ4' to obtain the first operation result. Next, in step S160, each storage unit 30(1,1) to 30(4,4) multiplies the first operation result by one of the self-multiplication coefficients h1 to h4 of the Ising model or by the interaction coefficient J. 12 ~J 34 One of them, to obtain multiple output values ​​P of the Ising model.ij .

[0142] Please also see Figure 13C In this embodiment, step S160 further includes steps S161 to S162. In step S161, the first threshold voltage V of the diagonal address storage cells 30(1,1), 30(3,3), and 30(4,4) is adjusted. tha With the second threshold voltage V thb The coefficients h1, h3, and h4, corresponding to the multiplication coefficients, are all "1". Figure 4B In the diagram, the cells 30(1,1), 30(3,3), and 30(4,4) are marked with "0 1" to indicate that the first threshold voltage V is stored in the memory. tha Set to a higher voltage value and set the second threshold voltage V thb Set to a lower voltage value.

[0143] Next, in step S162, the first threshold voltage V of the memory cells 30(1,2), 30(1,3), 30(1,4), 30(2,4), 30(3,1), and 30(4,2) outside the diagonal addresses is adjusted. tha With the second threshold voltage V thb With respect to the interaction coefficient J 12 J 13 J 14 J 24 J 31 J 42 All are "1". In Figure 4B In the memory cells 30(1,2), 30(1,3), 30(1,4), 30(2,4), 30(3,1), and 30(4,2), the first transistor Ma and the second transistor Mb are marked with "1 1" below them, indicating that the first threshold voltage V is applied. tha With the second threshold voltage V thb All are set to lower voltage values.

[0144] See also Figure 13B Then, in step S170, these output values ​​P are output via the common source lines SL1 to SL4 of the memory array 302, respectively. ij For example, the first source current I of the j-th common source line SLj. Sa With the second source current I Sb The sums are the common source current I S Corresponding to the output value P ij .

[0145] Then, in step S180, these output values ​​P of the common source lines SL1 to SL4 are amplified by inductive amplifiers SA1 to SA4. ijThe summation of these values ​​into the total output values ​​H1 to H4 can be expressed as equations (12) to (15):

[0146] H1=h1σ1+J 13 (σ3*σ1)=1+0=1 (12)

[0147] H2 = J 12 (σ1*σ2)+J 24 (σ4*σ2)=1+1=2 (13)

[0148] H3 = J 13 (σ1*σ3)+h3σ3=0+0=0 (14)

[0149] H4 = J 14 (σ1*σ4)+J 24 (σ2*σ4)+h4σ4=1+1+1=3 (15)

[0150] From the above, the sum of the total output values ​​H1 to H4 at the first time T1 is energy H = 6. Then, in step S190, a threshold H is set. th (For example, set to "2"), and compare each total output value H1~H4 with the threshold H th .

[0151] Then, in step S200, if the total output value H of the j-th common source line SLj is determined... j Greater than threshold H th Then proceed to step S210 to update the input value σ received by the first line BLja of the j-th line. j For example, the total output value H4 (value "3") of the fourth common-source line SL4 is greater than the threshold H. th Then the fourth input value σ4 will be updated from logic value "1" to logic value "0".

[0152] Next, see Figure 4C At the second time T2, steps S110 to S200 are re-executed based on the updated input value σ4 = "0". In step S180, which is re-executed at the second time T2, the total output values ​​H1 to H4 can be expressed as equations (16) to (19):

[0153] H1=h1σ1+J 13 (σ3*σ1)=1+0=1 (16)

[0154] H2 = J 12 (σ1*σ2)+J 24 (σ4*σ2)=1+0=1 (17)

[0155] H3 = J 13(σ1*σ3)+h3σ3=0+0=0 (18)

[0156] H4 = J 14 (σ1*σ4)+J 24 (σ2*σ4)+h4σ4=0+0+0=0 (19)

[0157] From the above, the sum of the total output values ​​H1 to H4 at the second time T2 is energy H = 2; energy H shows a decreasing trend, based on which the minimum energy H can be located. min .

[0158] Figure 5A This is a circuit diagram of a memory device 500 for processing Ising model operations according to another embodiment of the present disclosure. Figure 5B for Figure 5A A simplified schematic diagram of the memory device 500 processing Ising model operations. Please refer to [link / reference]. Figure 5A The memory device 500 in this embodiment is similar to Figure 3B The memory device 300B differs in that the memory array 502 in this embodiment further includes a fifth first word line WL5a and a fifth second word line WL5b, and the first first word line WL1a of the memory array 502 does not receive the input value σ1 but is always receiving the logic value "1". Accordingly, the memory array 502 of this embodiment shifts down a set of word lines to receive input values. For example, the second to fifth first word lines WL2a receive the first to fourth input values ​​σ4, respectively. Correspondingly, the second to fifth second word lines WL2b receive the inverted logic values ​​σ1' to σ4', respectively.

[0159] Please see next. Figure 5B The first threshold voltage V of the memory cells 50(1,1), 50(1,2), 50(1,3), and 50(1,4) located at the first column address of the memory device 500 tha With the second threshold voltage V thb Corresponding to the multiplication coefficients h1 to h4. Furthermore, these memory cells 50(1,1), 50(1,2), 50(1,3), and 50(1,4) respectively perform a logical "XNOR" operation between the input values ​​σ1 to σ4 and the constant logic value "1" and multiply by the multiplication coefficients h1 to h4. On the other hand, memory cells 50(2,2) to 50(5,3) located at the second to fifth column addresses of the memory device 500 perform a logical "XNOR" operation on the input values ​​σ1 to σ4 and multiply by the interaction coefficient J. 12 ~J 34As for the operation coefficients of the shifted diagonal address storage units 50(2,1), 50(3,2), 50(4,3), and 50(5,4), they are set to "0", so the output value of the storage units is always "0". In other words, the memory device 500 of this embodiment does not use the shifted diagonal address storage units 50(2,1), 50(3,2), 50(4,3), and 50(5,4) for operations.

[0160] See also Figure 5A In this embodiment, the memory device 500 sums the total output values ​​H1 to H4 of the inductive amplifiers SA1 to SA4 along the common source lines SL1 to SL4 via the summing circuit 504 to obtain the energy H. The energy H calculated by the memory device 500 in this embodiment is equal to... Figure 3B The energy H obtained by the memory device 300B (as shown in Equation (11)).

[0161] Please see below Figure 6A , 6B , it is Figure 5A A computational embodiment of the memory device 500 processing the Ising model operation, and also see... Figure 13A , 13B The 13D operation method. The operation embodiment and operation method of the memory device 500 are similar to those of the 13D operation method. Figure 4B , 4C The memory device 300B differs from the memory device 500 in that it executes... Figure 13D Steps S161B to S163B.

[0162] First see Figure 6A , and see Figure 13D In step S161B, the first threshold voltage V of the memory cells 50(1,1), 50(1,3), and 50(1,4) at the first column address of the memory array 502 of the memory device 500 is adjusted. tha With the second threshold voltage V thb The coefficients h1, h3, and h4 corresponding to the multiplication coefficients are all "1".

[0163] Then, in step S162B, the first threshold voltage V of the memory cells 50(2,2), 50(2,3), 50(2,4), 50(3,4), 50(4,1), and 50(5,2) other than the first column address is adjusted. tha With the second threshold voltage V thb With respect to the interaction coefficient J 12 J 13 J 14 J 24 J 13 J 24 All are "1".

[0164] Then, in step S163B, among the memory cells outside the first column address, the common source current of the shifted diagonal address memory cell 50(i, i-1) is zero. Therefore, at the first time T1, the total output values ​​H1 to H4 of the sensing amplifiers SA1 to SA4 of the memory array 502 can be expressed as equations (20) to (23):

[0165] H1=h1σ1+J 13 (σ3*σ1)=1+0=1 (20)

[0166] H2 = J 12 (σ1*σ2)+J 24 (σ4*σ2)=1+1=2 (21)

[0167] H3=h3σ3+J 13 (σ1*σ3)=0+0=0 (22)

[0168] H4=h4σ4+J 14 (σ1*σ4)+J 24 (σ²*σ⁴)=1+1+1=3 (23)

[0169] At the first time point T1, the sum of the total output values ​​H1 to H4 is energy H = 6. Then, execution... Figure 13B In step S200, it is determined that the total output value H4 (value "3") of the fourth common source line SL4 is greater than the threshold H. th (The value is "2"), therefore proceed. Figure 13B Step S210 updates the fourth input value σ4 (i.e., the fourth spin state) received by the fourth first bit line BL4a from the logic value "1" to the logic value "0".

[0170] Next, see Figure 6B At the second time T2, the process is re-executed based on the updated input value σ4 = "0". Figure 13A , 13B Steps S110 to S200. In step S180, which is re-executed at the second time T2, the total output values ​​H1 to H4 can be expressed as equations (24) to (27):

[0171] H1=h1σ1+J 13 (σ3*σ1)=1+0=1 (24)

[0172] H2 = J 12 (σ1*σ2)+J 24 (σ4*σ2)=1+0=1 (25)

[0173] H3=h3σ3+J 13σ1*σ3=0+0=0 (26)

[0174] H4=h4σ4+J 14 σ1*σ4+J 24 σ²*σ⁴=0+0+0=0 (27)

[0175] At the second time T2, the sum of the total output values ​​H1 to H4 equals energy H = 2, and energy H shows a decreasing trend. Based on this, the minimum energy H can be located. min .

[0176] Figure 7 This is a circuit diagram of a memory device 700 for processing Ising model operations, according to yet another embodiment of this disclosure. Please refer to... Figure 7 In the memory array 730 of the memory device 700, three memory cells are grouped together to operate on the same input value σ. i For example, memory cells 70(1,1), 70(1,2), and 70(1,3) in the same group receive the input value σ1 via the first bit line BL1a-1, the first bit line BL1a-2, and the first bit line BL1a-3, respectively, and receive the inverted logic value σ1' (not shown in the figure) via the second bit line BL1b-1, the second bit line BL1b-2, and the second bit line BL1b-3, respectively. Furthermore, the multiplication coefficient h1 is encoded into the first bit h1(1), the second bit h1(2), and the third bit h1(3) using binary coding, corresponding to an eighth-order value. The first threshold voltage V of memory cell 70(1,1) can be adjusted. th a and the second threshold voltage V thb (Not shown in the diagram) to set the first bit h1(1) (i.e., the most significant bit "MSB"). Similarly, the first threshold voltage V of the memory cells 70(1,2) can be adjusted. tha With the second threshold voltage V thb By setting the second bit h1(2), the first threshold voltage V of the storage cell 70(1,3) is adjusted. tha With the second threshold voltage V thb Set the third bit h1(3) (i.e., the least significant bit "LSB"). If the first bit h1(1), the second bit h1(2), and the third bit h1(3) are set to "0, 0, 0", then the multiplication coefficient h1 is the value of the first order (e.g., "0"). If the first bit h1(1), the second bit h1(2), and the third bit h1(3) are set to "1, 1, 1", then the multiplication coefficient h1 is the value of the eighth order (e.g., "7").

[0177] Furthermore, the common-source line SL1-1 of storage cell 70 (1,1) is connected to analog-to-digital converter (ADC) 702 to convert the analog signal of the common-source current output by storage cell 70 (1,1) into a digital signal. The ADC 702 is also connected to a 2-bit shifter 708 to shift the digital signal two bits higher. Similarly, the common-source line SL1-2 of storage cell 70 (1,2) is connected to ADC 704 to convert the analog signal of the common-source current into a digital signal, and then shifts it one bit higher via a 1-bit shifter 710. However, the digital signal output by ADC 706 from the common-source line SL1-3 of storage cell 70 (1,3) is not shifted. The outputs of the 2-bit shifter 708, the 1-bit shifter 710, and the ADC 706 can be integrated into a total output value H1 = h1σ1.

[0178] Similarly, storage cells 70(1,4), 70(1,5), and 70(1,6) of another group collectively correspond to the interaction coefficient J. 12 Interaction coefficient J 12 It can be encoded as the first J 12 (1) The second J 12 (2) and the third J 12 (3). The first threshold voltage V of the adjustable storage cells 70(1,4), 70(1,5) and 70(1,6) is adjustable. tha With the second threshold voltage V thb To set the first J respectively 12 (1) The second J 12 (2) and the third J 12 (3). The analog common-source currents output from common-source lines SL2-1, SL2-2, and SL2-3 are converted into digital signals via analog-to-digital converters 712, 714, and 716, two-bit shifter 718, and one-bit shifter 720, and integrated into a total output value H2 = J. 12 σ1*σ2.

[0179] Figure 8 This is a circuit diagram of a memory device 800 for processing Ising model operations according to another embodiment of this disclosure. See also Figure 8 The memory device 800 uses unary coding to encode the multiplication coefficient h1 as the first bit h1(1) to the eighth bit h1(8). Eight memory cells 80(1,1) to 80(1,8) in the same group correspond to the same multiplication coefficient h1, and the first threshold voltage V of the memory cells 80(1,1) to 80(1,8) can be adjusted. tha With the second threshold voltage V thbThe first bit h1(1) to the eighth bit h1(8) of the multiplication coefficient h1 are set respectively. Furthermore, the storage cells 80(1,1) to 80(1,8) receive the same input value σ1 via the first bit line BL1a-1 to BL1a-8. Moreover, the common source currents output by the common source lines SL1-1 to SL1-8 of the storage cells 80(1,1) to 80(1,8) are summed and converted into digital signals by the analog-to-digital converter 802 to obtain the output value H1=h1σ1.

[0180] Figure 9 This is a circuit diagram of a memory device 900 for processing Ising model operations according to another embodiment of the present disclosure. Figure 9 The Ising model, for example, has nine input values ​​σ1 to σ9. The memory device 900 performs the Ising model operation using two memory subarrays 902 and 904. Specifically, the first threshold voltage V of the memory cells 92(1,1) to 92(9,1) at the first row address of memory subarray 902... tha With the second threshold voltage V thb The first component h1 corresponding to the self-multiplication coefficient h1 + On the other hand, the first threshold voltage V of the memory cells 94(1,1) to 94(9,1) of the first row address of the memory subarray 904 tha With the second threshold voltage V thb The second component h1 corresponding to the self-multiplication coefficient h1 - The first component h1 can be... + With the second component h1 - The self-multiplication coefficients h1 = h1 + -h1 - .

[0181] Similarly, the first threshold voltage V of the memory cells 92(1,9) to 92(9,9) at the ninth row address of the memory subarray 902 tha With the second threshold voltage V thb Corresponding to the interaction coefficient J 19 First component J19 + The first threshold voltage V of memory cells 94(1,9) to 94(9,9) at the ninth row address of memory subarray 904. tha With the second threshold voltage V thb Corresponding to the interaction coefficient J 19 The second component J 19 - The first component J can be... 19 + With the second component J 19 - Composition of interaction coefficient J 19 =J 19+ -J 19 - .

[0182] Figure 10 This is a circuit diagram of a memory array 1002 for processing Ising model operations according to another embodiment of this disclosure. See also Figure 10 In this embodiment, the memory array 1002 is a planar NOR gate memory array. The sources of the two transistors in the same memory cell of the memory array 1002 do not need to be directly connected to each other in a common-source configuration. For example, taking memory cell 100(1,1) as an example, the first source Sa of the first transistor Ma does not need to be directly connected to the second source Sb of the second transistor Mb in a common-source configuration; they only need to be connected to the common-source line SL1. The result of the operation on the input value σ1 in memory cell 100(1,1) is output as the total output value H1 via the common-source line SL1.

[0183] Figure 11 This is a circuit diagram of a memory array 1102 for processing Ising model operations, according to yet another embodiment of this disclosure. See also... Figure 11 In this embodiment, the memory array 1102 is a three-dimensional stacked AND gate-type memory array. The memory array 1102 includes multiple stacked memory subarrays 110-1 to 110-N. Each memory subarray 110-1 to 110-N can independently process Ising model operations.

[0184] Figure 12 This is a circuit diagram of a memory device 1200 for processing Ising model operations according to another embodiment of this disclosure. See also Figure 12 In this embodiment, the input value of the memory device 1200 can be transmitted and distributed to multiple memory arrays via a routing circuit. For example, the input value σ1 of memory array 120-1 can be transmitted to memory array 120-4 in sequence via routing circuits 122, 124, 126, 128, and 130.

[0185] Based on the memory devices 300B-1200 and corresponding calculation methods described in the above embodiments, the technical solution of this disclosure processes the Ising model calculation using the semiconductor memory devices 300B-1200, and can handle multiple input values ​​σ. i Multiple self-multiplication coefficients h i With interaction coefficient J ij The energy H is obtained through calculation. Furthermore, an update mechanism based on majority voting is used to locate the lowest energy H of the Ising model. minThe technical solution disclosed herein can rapidly calculate the energy H by simulating quantum annealing operations using a semiconductor memory device of 300B to 1200, and obtain the optimal solution (lowest energy H). min The input value σ i .

[0186] While this disclosure has been given in detail above with reference to preferred embodiments and examples, it is understood that these examples are intended to be illustrative rather than limiting. It is anticipated that various modifications and combinations will arise in the hands of those skilled in the art, all of which fall within the spirit of the invention and the scope of the appended claims.

Claims

1. A memory device, comprising: a memory array configured to process a model operation having a plurality of input values, a plurality of self-multiplication coefficients, a plurality of interaction coefficients, and a plurality of output values, the memory array comprising: a plurality of first word lines and a plurality of second word lines; a plurality of first bit lines and a plurality of second bit lines; a plurality of common source lines; and a plurality of memory cells configured to receive the input values via the first word lines, respectively, receive inverse logic values of the input values via the second word lines, respectively, receive the input values via the first bit lines, respectively, receive the inverse logic values via the second bit lines, respectively, and output the output values via the common source lines, respectively, wherein each of the memory cells is configured to perform a logical XNOR operation on each of the input value and the inverse logic value to obtain a first operation result, and multiply each of the first operation result by one of the self-multiplication coefficients or one of the interaction coefficients to obtain the output value.

2. The memory device of claim 1, wherein each of the memory cells comprises: a first transistor having a gate connected to an i-th of the first word lines to be applied with a first gate voltage, a drain connected to a j-th of the first bit lines to be applied with a first drain voltage, and a source connected to a j-th of the common source lines to output a first source current; and a second transistor having a gate connected to an i-th of the second word lines to be applied with a second gate voltage, a drain connected to a j-th of the second bit lines to be applied with a second drain voltage, and a source connected to the j-th of the common source lines to output a second source current, the second source current being summed with the first source current to be a common source current, wherein the first gate voltage corresponds to an i-th of the input values, the second gate voltage corresponds to an inverse logic value of the i-th of the input values, the first drain voltage corresponds to a j-th of the input values, the second drain voltage corresponds to an inverse logic value of the j-th of the input values, and the common source current corresponds to the output value outputted by the j-th of the common source lines.

3. The memory device of claim 2, wherein if i equals j, the i-th of the input values received by the i-th of the first word lines is equal to the j-th of the input values received by the j-th of the first bit lines, the i-th of the input values being an i-th of a plurality of spin states.

4. The memory device of claim 3, wherein the first transistor has a first threshold voltage, the second transistor has a second threshold voltage, and if i equals j, the first threshold voltage and the second threshold voltage correspond to one of the self-multiplication coefficients.

5. The memory device of claim 4, wherein if i does not equal j, the first threshold voltage and the second threshold voltage correspond to one of the interaction coefficients.

6. A method of operating a memory device, comprising: ​ receiving a plurality of input values of a model operation via a plurality of first word lines of a memory array, respectively; receiving inverse logic values of the input values via a plurality of second word lines of the memory array, respectively; receiving the input values via a plurality of first bit lines of the memory array, respectively; receiving the inverse logic values via a plurality of second bit lines of the memory array, respectively; performing an exclusive NOR operation according to each of the input values and each of the inverse logic values to obtain a first operation result; multiplying each of the first operation results by one of a plurality of self-multiplication coefficients of the model operation or one of a plurality of interaction coefficients of the model operation to obtain a plurality of output values of the model operation; and outputting the output values via a plurality of common source lines of the memory array, respectively.

7. The operation method of claim 6, wherein the memory array comprises a plurality of memory cells, each of the memory cells comprising a first transistor and a second transistor, the operation method comprising: applying a first gate voltage to a gate of the first transistor via an i-th first word line of the first word lines, the first gate voltage corresponding to an i-th input value of the input values; applying a first drain voltage to a drain of the first transistor via a j-th first bit line of the first bit lines, the first drain voltage corresponding to a j-th input value of the input values; outputting a first source current provided by a source of the first transistor via a j-th common source line of the common source lines; applying a second gate voltage to a gate of the second transistor via an i-th second word line of the second word lines, the second gate voltage corresponding to an inverse logic value of the i-th input value; applying a second drain voltage to a drain of the second transistor via a j-th second bit line of the second bit lines, the second drain voltage corresponding to an inverse logic value of the j-th input value; outputting a second source current provided by a source of the second transistor via the j-th common source line; summing the second source current and the first source current to be a common source current, the common source current corresponding to the output value outputted by the j-th common source line.

8. The operation method of claim 7, wherein if i equals j, the i-th input value received by the i-th first word line is equal to the j-th input value received by the j-th first bit line, the i-th input value being an i-th spin state of a plurality of spin states.

9. The operation method of claim 8, further comprising: adjusting a first threshold voltage of the first transistor; and adjusting a second threshold voltage of the second transistor, wherein if i equals j, the first threshold voltage and the second threshold voltage correspond to one of the self-multiplication coefficients.

10. The operation method of claim 9, wherein if i does not equal j, the first threshold voltage and the second threshold voltage correspond to one of the interaction coefficients. ​ ​ ​

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