A low-power data dormancy and recoverable 11T-SRAM unit circuit and module

Abstract

The present invention relates to the technical field of static random access memory (SRAM), and more specifically, to a low-power data dormancy and recoverable 11T-SRAM unit circuit, as well as a module using such a circuit layout. In the 11T-SRAM unit circuit of the present invention, N1, N2, P4, and P5 constitute a feedback branch, and the stored data at the storage node QB is used to turn off N1 or P5 through N2 or P4, so that the unit circuit enters a dormant state. The present invention uses the stored data "0" or "1" of the circuit itself to turn off N1 or P5 through a feedback branch, thereby cutting off the connection between the unit circuit and VDD or GND, causing the circuit to enter a dormant state, thereby reducing the static power consumption of the storage unit; and the data after dormancy can be adjusted by signals to restore the levels of the storage nodes Q and QB to their original states, without causing functional errors.

Description

Technical Field

[0001] The present invention relates to the technical field of static random access memory (SRAM), and more specifically to a low-power data dormancy and recoverable 11T-SRAM unit circuit, and a module using the circuit layout. Background Art

[0002] In recent years, with advances in MOSFET manufacturing processes and the widespread adoption of SOC systems, including high-speed mobile network communications, GPS global satellite navigation, and wireless sensor technologies, the demand for low power consumption in SOC systems has increased significantly. In current integrated circuit designs, SRAM accounts for over 50% of the SOC module area, and memory power consumption accounts for 25% to 50% of the entire SOC module. This proportion is expected to increase with continued process advancements. Consequently, SRAM power consumption is attracting increasing attention. Reducing SRAM power consumption can effectively improve overall system performance, reliability, and cost.

[0003] In recent years, many methods have been developed to reduce SRAM power consumption. For example: 1. Bias voltage adjustment technology: Intel's SRAM uses the method of increasing the N-well bias voltage to reduce subthreshold leakage. Similarly, the P-well bias can be adjusted, or the N-well and P-well bias can be adjusted simultaneously; 2. Leakage current suppression technology: Using different threshold voltages for transistors in the cell to suppress subthreshold leakage current, or using multiple gate oxide thicknesses (T_OX) to suppress gate current; 3. Subthreshold circuit design technology: This technology achieves extremely low total system power consumption by reducing the system power supply voltage to the subthreshold region of the device.

[0004] Among them, for method 3, as the power supply voltage is greatly reduced, the impact of environmental parameters and process deviations on the performance of subthreshold circuits also changes exponentially, which can easily lead to fatal functional errors in the circuit. Summary of the Invention

[0005] Based on this, it is necessary to provide a low-power data dormancy and recoverable 11T-SRAM unit circuit and module to address the problem that the existing method of reducing the total system power consumption by reducing the power supply voltage is prone to fatal functional errors in the circuit.

[0006] The present invention is achieved by adopting the following technical solutions:

[0007] In a first aspect, the present invention provides a low-power data dormancy and recoverable 11T-SRAM unit circuit, including six NMOS transistors N1, N2, N3, N4, N5, N6 and five PMOS transistors P1, P2, P3, P4, P5.

[0008] The drain of N1 is electrically connected to power supply VDD. The drain of N2 is electrically connected to the gate of N1, and the gate of N2 is electrically connected to feedback control signal CA1. The source of N4 is electrically connected to the source of N3, the drain of N4 is electrically connected to the gate of N3, and the gate of N4 is electrically connected to the drain of N3. The source of N5 is electrically connected to bit line BL, the gate of N5 is electrically connected to word line WL, and the drain of N5 is electrically connected to the drain of N3. The source of N6 is electrically connected to restore signal B, and the gate of N6 is electrically connected to restore control signal CB2. The source of P1 is electrically connected to restore signal A, the gate of P1 is electrically connected to restore control signal CA2, and the drain of P1 is electrically connected to the gate of N1. The source of P2 is electrically connected to the source of N1, the gate of P2 is electrically connected to the gate of N3, and the drain of P2 is electrically connected to the drain of N3. Storage node Q is also provided. The source of P3 is electrically connected to the source of N1, the gate of P3 is electrically connected to the drain of P2, and the drain of P3 is electrically connected to the drain of N4, with storage node QB being provided. The source of P4 is electrically connected to the source of N2, the drain of P4 is electrically connected to the source of N6, and the gate of P4 is electrically connected to feedback control signal CB1. The source of P5 is electrically connected to the source of N3, the gate of P5 is electrically connected to the drain of N6, and the drain of P5 is electrically connected to GND.

[0009] The 11T-SRAM unit circuit realizes sleep and recovery through signal adjustment.

[0010] The implementation of the low-power data dormancy and recoverable 11T-SRAM unit circuit is based on the method or process of the embodiment of the present disclosure.

[0011] In a second aspect, the present invention discloses a low-power data dormancy and recoverable 11T-SRAM unit module, which adopts the low-power data dormancy and recoverable 11T-SRAM unit circuit layout disclosed in the first aspect.

[0012] The implementation of the low-power data dormancy and recoverable 11T-SRAM unit module is based on the method or process of the embodiment of the present disclosure.

[0013] Compared with the prior art, the present invention has the following beneficial effects:

[0014] The 11T-SRAM unit circuit of the present invention utilizes the stored data "0" or "1" in the circuit itself to turn off N1 or P5 through a feedback branch, thereby disconnecting the unit circuit from VDD or GND, causing the circuit to enter a dormant (power-off) state and reducing the static power consumption of the storage unit. Furthermore, the data after dormancy can be adjusted by signals to restore the levels of the storage nodes Q and QB to their original states, without causing functional errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 This is a structural diagram of a low-power data dormant and recoverable 11T-SRAM unit circuit provided by an embodiment of the present invention.

[0017] Figure 2 for Figure 1 The timing waveform of the 11T-SRAM unit circuit;

[0018] Figure 3 for Figure 1 Comparison data of static power consumption of 11T-SRAM unit circuit and other unit circuits;

[0019] Figure 4 In the embodiment of the present invention, Figure 1 Module interface diagram of the 11T-SRAM unit circuit layout. DETAILED DESCRIPTION

[0020] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0021] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component. When a component is considered to be "fixed to" another component, it may be directly fixed to the other component or there may be a central component.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0023] See Figure 1, a structural diagram of a low-power data dormancy and recoverable 11T-SRAM unit circuit disclosed in the present invention. This 11T-SRAM unit circuit includes five PMOS transistors and six NMOS transistors. The five PMOS transistors are sequentially denoted as P1 to P5, and the six NMOS transistors are sequentially denoted as N1 to N6.

[0024] Specifically, the connection relationship between the MOS transistors is:

[0025] The drain of N1 is electrically connected to power supply VDD. The drain of N2 is electrically connected to the gate of N1, and the gate of N2 is electrically connected to feedback control signal CA1. The source of N4 is electrically connected to the source of N3, the drain of N4 is electrically connected to the gate of N3, and the gate of N4 is electrically connected to the drain of N3. The source of N5 is electrically connected to bit line BL, the gate of N5 is electrically connected to word line WL, and the drain of N5 is electrically connected to the drain of N3. The source of N6 is electrically connected to restore signal B, and the gate of N6 is electrically connected to restore control signal CB2. The source of P1 is electrically connected to restore signal A, the gate of P1 is electrically connected to restore control signal CA2, and the drain of P1 is electrically connected to the gate of N1. The source of P2 is electrically connected to the source of N1, the gate of P2 is electrically connected to the gate of N3, and the drain of P2 is electrically connected to the drain of N3. Storage node Q is also provided. The source of P3 is electrically connected to the source of N1, the gate of P3 is electrically connected to the drain of P2, and the drain of P3 is electrically connected to the drain of N4, with storage node QB being provided. The source of P4 is electrically connected to the source of N2, the drain of P4 is electrically connected to the source of N6, and the gate of P4 is electrically connected to feedback control signal CB1. The source of P5 is electrically connected to the source of N3, the gate of P5 is electrically connected to the drain of N6, and the drain of P5 is electrically connected to GND.

[0026] Based on the above circuit structure, P2 and N3 form an inverter, P3 and N4 form another inverter, and the two inverters form a latch circuit.

[0027] P2 and P3 serve as the pull-up circuit structure for write operations. Read operations are implemented by N5. N1, N2, P4, and P5 form the feedback branch. Using the stored data at storage node QB, N2 or P4 turns off N1 or P5, putting the unit circuit into a dormant state. N5, N6, and P4 form the write transfer transistor.

[0028] In order to verify the function of the 11T-SRAM unit circuit in the embodiment of the present invention, a simulation is performed on it. The simulation conditions are: Corner: TT; Temperature: 27° C.; VDD: 0.9V.

[0029] like Figure 2 As shown in FIG, it is a timing waveform diagram of the 11T-SRAM unit circuit in an embodiment of the present invention. Figure 2The figure shows that when the 11T-SRAM cells form a 64*1 array, the data stored in the 63rd row is "1" and the data stored in the 0th row is "0", and the corresponding signal changes when performing "hold", "sleep", "restore 0", "restore 1", write "0", "hold", read "0", "hold", write "1", "hold", read "1", "hold".

[0030] Depend on Figure 2 It can be seen that the unit circuit has completed the functions of writing "hold", "sleep", "restore 0", "restore 1", writing "0", reading "0", writing "1", and reading "1" in succession. Therefore, this unit circuit can complete the read and write functions required by the SRAM unit. In addition, since the initial state QB <63> =0, Q <63> =1 (i.e. the data stored in row 63 is "1"), QB <0> =1, Q <0> =0 (i.e., row 0 stores "0") indicates that for different rows, "0" / "1" can be restored at the same time.

[0031] The 11T-SRAM unit circuit realizes sleep and recovery through signal adjustment.

[0032] Specifically:

[0033] (1) In the 11T-SRAM unit circuit, when the bit line BL is in the hold state, the word line WL is in the low level, and N5 is in the off state; the feedback signal CA1 is in the low level, the feedback control signal CB1 is in the high level, and N2 and P4 are in the off state; the restore control signal CA2 is in the low level, the restore control signal CB2 is in the high level, and P1 and N6 are in the on state; the restore signal A is in the high level, and the restore signal B is in the low level, so that the latch formed by P2, P3, N3, and N4 is in the latched state, thereby ensuring the stability of the unit circuit in the hold state.

[0034] (2) When the 11T-SRAM unit circuit is in a dormant state, the bit line BL is high, the word line WL is low, and N5 is in a closed state; the feedback signal CA1 is high, the feedback control signal CB1 is low, N2 and P4 are in an open state; the restore control signal CA2 is high, the restore control signal CB2 is low, P1 and N6 are in a closed state; the restore signal A is low, the restore signal B is high, and if the voltage of the storage node Q is "0" and the voltage of the storage node QB is "1", P5 is closed, and the unit circuit enters a dormant state; if the voltage of the storage node Q is "1" and the voltage of the storage node QB is "0", N1 is closed, and the unit circuit enters a dormant state; this reduces the static power consumption of the circuit.

[0035] (3) In the recovery operation phase of the 11T-SRAM unit circuit, when the unit circuit is in a dormant state, if the storage data before the dormant state is "0", the voltage of the storage node Q will gradually increase in level, but its voltage is lower than the voltage of the storage node QB. More specifically, the voltage of the storage node Q is slightly lower than the voltage of the storage node QB. If the storage data before the unit is dormant state is "1", the voltage of the storage node Q will gradually decrease in level, but its voltage is higher than the voltage of the storage node QB. More specifically, the voltage of the storage node Q is slightly higher than the voltage of the storage node QB.

[0036] The unit circuit operates in the order of restoring "0" first and then "1". The state of the control signal varies depending on the restored data. In this way, the levels of the storage nodes Q and QB can be restored to their original states without causing functional errors.

[0037] Specifically, when restoring "0", the bit line BL is pre-charged to a low level, and then the word line WL is high, so that N5 is in an open state, the storage node Q is discharged to a low level through N5, and the storage node QB is still at a high level in the dormant state; then the bit line BL becomes high and the word line WL becomes low, so that N5 is in a closed state; the feedback signal CA1 is low, and the feedback control signal CB1 is high, so that N2 and P4 are respectively in a closed state; the recovery control signal CA2 is high to make P1 in a closed state, and the recovery signal A is low; finally, the recovery control signal CB2 changes from low level to high level, so that N6 is in an open state, and at the same time, the recovery signal B changes from high level to low level, so that P5 is turned on through N6, so that the unit circuit is connected to GND, and the recovery of "0" is completed.

[0038] When restoring "1", the bit line BL is precharged to a high level, and then the word line WL is high, turning N5 on. The bit line BL charges node Q through N5, making the voltage of storage node Q higher than the voltage of QB. Then the word line WL goes low, turning N5 off. The restore control signal CA2 changes from high to low, turning P1 on. At the same time, the restore signal A changes from low to high, turning N1 on through P1, connecting the unit circuit to VDD. The storage node QB remains low, P2 is open, and the voltage of storage node Q is pulled up to a high level, completing the restoration of "1". It should be noted that the feedback signal CA1, the restore control signals CB1 and CB2, and the restore signal B remain unchanged at the level when restoring "0".

[0039] (IV) In the write operation phase of the 11T-SRAM unit circuit, the restore control signal CA2 is at a low level, and the restore control signal CB2 is at a high level; the restore signal A is at a high level, and the restore signal B is at a low level; the states of the control signals are different depending on the write data.

[0040] Specifically, when writing "0", the bit line BL is precharged to a low level, the word line WL is a high level, the storage node Q is discharged to a low level through N5, P3 is turned on, and the storage node QB is pulled up to a high level, completing the write "0" operation.

[0041] When writing "1", the bit line BL is precharged to a high level, the word line WL is a high level, the feedback control signal CB1 is a low level, P4 is turned on, the storage node QB is discharged to a low level through P4 and N6, P2 is turned on, and the storage node Q is pulled up to a high level to complete the write "1" operation.

[0042] (5) In the read operation phase of the 11T-SRAM cell circuit, the word line WL is at a high level, the feedback signal CA1 is at a low level, the feedback control signal CB1 is at a high level, the restore control signal CA2 is at a low level, the restore control signal CB2 is at a high level, the restore signal A is at a high level, the restore signal B is at a low level, and the bit line BL is precharged to a high level.

[0043] The word line WL is turned on for a read operation. If "1" is stored, the voltage of the bit line BL remains unchanged; if "0" is stored, the voltage of the bit line BL decreases.

[0044] Specifically, the bit line BL is connected to the sense amplifier SA, and the sense amplifier SA detects the level change of the bit line BL to read the data stored in the 11T-SRAM.

[0045] It should be noted that the bit line BL is electrically connected to the first input terminal of the sense amplifier SA, the second input terminal of the sense amplifier SA is connected to the reference voltage, and the output terminal of the sense amplifier SA outputs the result: if it is stored as "1", the sense amplifier SA outputs "1"; if it is stored as "0", the sense amplifier SA outputs "0".

[0046] Of course, in order to more clearly show the power consumption advantage of the T-SRAM unit circuit of the embodiment of the present invention, see Figure 3 , comparing the 11T-SRAM cell circuit of the present invention with the standard 6T-SRAM cell circuit:

[0047] The simulation conditions are: Corner: TT; Temperature: 27°C; VDD: 0.6V~0.9V.

[0048] Because the sleep power consumption of the 11T-SRAM unit circuit of the present invention is slightly different when storing "0" and storing "1", the final data is the sum of the sleep power consumption of the 11T-SRAM unit circuit when storing "0" and storing "1", and then taking the average result.

[0049] The simulation results show that in the dormant state, the power consumption of the 11T-SRAM unit circuit proposed in the present invention is reduced by 77%, 80%, 82%, and 83% respectively compared with the static power consumption (hold state) of the traditional 6T-SRAM unit circuit at power supply voltages of 0.6V, 0.7V, 0.8V, and 0.9V.

[0050] Furthermore, based on the aforementioned low-power data dormancy and recoverable 11T-SRAM cell circuit, this embodiment also discloses a low-power data dormancy and recoverable 11T-SRAM cell module, which utilizes the aforementioned low-power data dormancy and recoverable 11T-SRAM cell circuit layout. This modular packaging facilitates the promotion and application of the low-power data dormancy and recoverable 11T-SRAM cell circuit.

[0051] For details, see Figure 4 The interfaces of the low-power data dormancy and recoverable 11T-SRAM unit module include: a first interface, a second interface, a third interface, a fourth interface, a fifth interface, a sixth interface, a seventh interface, an eighth interface, a ninth interface, and a tenth interface.

[0052] The first interface is electrically connected to the source of P1 for transmitting a recovery signal A. The second interface is electrically connected to the source of N6 for transmitting a recovery signal B. The third interface is electrically connected to the gate of N2 for transmitting a feedback signal CA1. The fourth interface is electrically connected to the gate of P1 for transmitting a feedback signal CA2. The fifth interface is electrically connected to the gate of P4 for transmitting a feedback control signal CB1. The sixth interface is electrically connected to the gate of N6 for transmitting a recovery control signal CB2. The seventh interface is electrically connected to the source of N5 via a bit line BL. The eighth interface is electrically connected to the gate of N5 via a word line WL. The ninth interface is electrically connected to VDD. The tenth interface is electrically connected to GND.

[0053] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0054] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A low-power data dormancy and recoverable 11T-SRAM unit circuit, characterized in that: include: The NMOS transistor N1 has a drain electrically connected to a power supply VDD; NMOS transistor N2, the drain of N2 is electrically connected to the gate of N1, and the gate of N2 is electrically connected to the feedback control signal CA1. NMOS transistor N3; an NMOS transistor N4, wherein a source of N4 is electrically connected to a source of N3, a drain of N4 is electrically connected to a gate of N3, and a gate of N4 is electrically connected to a drain of N3; an NMOS transistor N5, wherein a source of N5 is electrically connected to the bit line BL, a gate of N5 is electrically connected to the word line WL, and a drain of N5 is electrically connected to the drain of N3; NMOS transistor N6, the source of N6 is electrically connected to the recovery signal B, and the gate of N6 is electrically connected to the recovery control signal CB2; A PMOS transistor P1, wherein the source of P1 is electrically connected to the restoration signal A, the gate of P1 is electrically connected to the restoration control signal CA2, and the drain of P1 is electrically connected to the gate of N1; A PMOS transistor P2, wherein the source of P2 is electrically connected to the source of N1, the gate of P2 is electrically connected to the gate of N3, the drain of P2 is electrically connected to the drain of N3, and a storage node Q is provided; A PMOS transistor P3, wherein the source of P3 is electrically connected to the source of N1, the gate of P3 is electrically connected to the drain of P2, the drain of P3 is electrically connected to the drain of N4, and a storage node QB is set; A PMOS transistor P4, wherein the source of P4 is electrically connected to the source of N2 and the drain of P3, the drain of P4 is electrically connected to the drain of N6, and the gate of P4 is electrically connected to the feedback control signal CB1; A PMOS transistor P5, wherein the source of P5 is electrically connected to the source of N3, the gate of P5 is electrically connected to the drain of N6, and the drain of P5 is electrically connected to GND; The 11T-SRAM unit circuit realizes sleep and recovery through signal adjustment.

2. The low-power data dormancy and recoverable 11T-SRAM unit circuit according to claim 1, characterized in that: In the hold state of the 11T-SRAM unit circuit, the bit line BL is at a high level, the word line WL is at a low level, and N5 is in a closed state; the feedback signal CA1 is at a low level, the feedback control signal CB1 is at a high level, and N2 and P4 are in a closed state; the restore control signal CA2 is at a low level, the restore control signal CB2 is at a high level, and P1 and N6 are in a conductive state; the restore signal A is at a high level, and the restore signal B is at a low level, so that the latch composed of P2, P3, N3, and N4 is in a latched state.

3. The low-power data dormancy and recoverable 11T-SRAM unit circuit according to claim 1, characterized in that: In the dormant state of the 11T-SRAM unit circuit, the bit line BL is high, the word line WL is low, and N5 is closed; the feedback signal CA1 is high, the feedback control signal CB1 is low, N2 and P4 are open; the restore control signal CA2 is high, the restore control signal CB2 is low, P1 and N6 are closed; the restore signal A is low, the restore signal B is high, and if the voltage of the storage node Q is "0" and the voltage of the storage node QB is "1", P5 is closed and the unit circuit enters the dormant state; If the voltage of the storage node Q is “1” and the voltage of the storage node QB is “0”, N1 is turned off and the unit circuit enters a dormant state.

4. The low-power data dormancy and recoverable 11T-SRAM unit circuit according to claim 1, characterized in that: The 11T-SRAM cell circuit is in the recovery operation phase. When the unit circuit is in a dormant state, if the storage data before dormancy is "0", the voltage of the storage node Q will gradually increase, but its voltage is lower than the voltage of the storage node QB; If the storage data before the cell goes into sleep mode is "1", the voltage of the storage node Q will gradually decrease, but its voltage will be higher than the voltage of the storage node QB. The unit circuit operates in the order of restoring "0" first and then restoring "1". The state of the control signal is different according to the different restored data.

5. The low-power data dormancy and recoverable 11T-SRAM unit circuit according to claim 4, characterized in that: When restoring "0", the bit line BL is precharged to a low level, and then the word line WL is high, so that N5 is in the open state, and the storage node Q is discharged to a low level through N5, and the storage node QB is still at a high level in the dormant state; then the bit line BL is changed to a high level and the word line WL is changed to a low level, so that N5 is in the closed state; the feedback signal CA1 is low level, and the feedback control signal CB1 is high level, respectively turning N2 and P4 into the closed state; the restore control signal CA2 is high level, turning P1 into the closed state, and the restore signal A is low level; finally, the restore control signal CB2 changes from low level to high level, turning N6 into the open state, and at the same time, the restore signal B changes from high level to low level, turning P5 into the open state through N6, so that the unit circuit is connected to GND, and the restoration of "0" is completed; When restoring "1", the bit line BL is pre-charged to a high level, and then the word line WL is high, so that N5 is in an open state. The bit line BL charges the node Q through N5, so that the voltage of the storage node Q is higher than the voltage of QB, and then the word line WL becomes a low level, so that N5 is in a closed state; the recovery control signal CA2 changes from a high level to a low level, so that P1 is in an open state, and at the same time the recovery signal A changes from a low level to a high level, turning N1 on through P1, so that the unit circuit is connected to VDD; the storage node QB is always at a low level, P2 is in an open state, and the voltage of the storage node Q is pulled up to a high level, and the recovery of "1" is completed.

6. The low-power data dormancy and recoverable 11T-SRAM unit circuit according to claim 1, characterized in that: In the write operation phase of the 11T-SRAM unit circuit, the recovery control signal CA2 is low, the recovery control signal CB2 is high; the recovery signal A is high, the recovery signal B is low; the state of the control signal is different according to the different write data.

7. The low-power data dormancy and recoverable 11T-SRAM unit circuit according to claim 6, characterized in that: When writing "0", the bit line BL is precharged to a low level, the word line WL is at a high level, the storage node Q is discharged to a low level through N5, P3 is turned on, and the storage node QB is pulled up to a high level, completing the write "0" operation; When writing "1", the bit line BL is precharged to a high level, the word line WL is high, the feedback control signal CB1 is low, P4 is turned on, the storage node QB is discharged to a low level through P4 and N6, P2 is turned on, and the storage node Q is pulled up to a high level, completing the write "1" operation.

8. The low-power data dormancy and recoverable 11T-SRAM unit circuit according to claim 7, characterized in that: In the read operation phase of the 11T-SRAM cell circuit, the word line WL is at a high level, the feedback signal CA1 is at a low level, the feedback control signal CB1 is at a high level, the restore control signal CA2 is at a low level, the restore control signal CB2 is at a high level, the restore signal A is at a high level, the restore signal B is at a low level, and the bit line BL is precharged to a high level; When the voltage of the storage node Q is "0" and the voltage of the storage node QB is "1", the bit line BL is discharged through N5, the voltage of the bit line BL is reduced, and the read "0" operation is completed; When the voltage of the storage node Q is "1" and the voltage of the storage node QB is "0", the bit line BL remains at a high level, completing the read "1" operation.

9. Low-power data dormancy and recoverable 11T-SRAM unit module, characterized by: The low-power data dormancy and recoverable 11T-SRAM unit circuit layout according to any one of claims 1 to 8 is adopted.

10. The low-power data dormancy and recoverable 11T-SRAM unit module according to claim 9, characterized in that: The interface of the low-power data dormancy and recoverable 11T-SRAM unit module includes: A first interface, electrically connected to the source of P1 and used for transmitting a recovery signal A; A second interface, electrically connected to the source of N6, for transmitting a recovery signal B; A third interface, electrically connected to the gate of N2, for transmitting a feedback signal CA1; A fourth interface, electrically connected to the gate of P1 and configured to transmit a feedback signal CA2; A fifth interface, electrically connected to the gate of P4, for transmitting a feedback control signal CB1; a sixth interface electrically connected to the gate of N6 and configured to transmit a recovery control signal CB2; a seventh interface electrically connected to the source of N5 via the bit line BL; an eighth interface electrically connected to the gate of N5 via a word line WL; a ninth interface configured to be electrically connected to VDD; and The tenth interface is used for electrical connection to GND.

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