Semiconductor devices and their fabrication methods

Abstract

This application discloses a semiconductor device and a method for forming the same. The method includes: providing a substrate comprising a plurality of protrusions with a groove between adjacent protrusions; forming an undoped first semiconductor layer at the bottom of each groove; doping the first semiconductor layer; forming a doped first conductive structure on the surface of the doped first semiconductor layer; and heat-treating the first semiconductor layer to form a second conductive structure, wherein the second conductive structure and the first conductive structure form a contact structure at the bottom of the groove. This application avoids the problem of excessive diffusion of impurity elements such as phosphorus (P), thereby improving the reliability of the resulting semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device and a forming method thereof. BACKGROUND

[0002] The semiconductor structure usually adopts a conductive structure such as a pad or a contact plug to couple two functional structures above and below, so as to realize the electrical connection between the two functional structures. Figure 1a For example, the semiconductor structure shown in the figure, Figure 1b is a sectional view along the direction of line AA’, Figure 1c is a sectional view along the direction of line BB’, the semiconductor structure can include a substrate 110 and a plurality of convex columns 121 located on the surface of the substrate 110, the substrate 110 is provided with an isolation region 111 and a plurality of active regions 112 isolated by the isolation region 111; there is a groove 122 between two adjacent convex columns 121, and the groove 122 exposes the isolation region 111 and part of the active region 112. The inventors have found that in some semiconductor structures, after a contact plug (such as 123) is formed at the bottom of the groove 122, short circuit is prone to occur between the conductive structures, which affects the performance of the semiconductor structure. Figure 1b SUMMARY

[0003] In view of this, the present application provides a semiconductor device and a forming method thereof, so as to solve the problem that after a conductive structure such as a pad or a contact plug is formed at the bottom of the groove, short circuit is prone to occur between the active regions inside the substrate, which affects the performance of the semiconductor structure.

[0004] The present application provides a forming method of a semiconductor device, comprising:

[0005] providing a substrate, the substrate includes a plurality of convex columns, and there is a groove between two adjacent convex columns;

[0006] forming an undoped first semiconductor layer at the bottom of each groove;

[0007] doping treatment is performed on the first semiconductor layer;

[0008] forming a doped first conductive structure on the surface of the doped first semiconductor layer;

[0009] heat treatment is performed on the first semiconductor layer, so that the doped first semiconductor layer forms a second conductive structure, and the second conductive structure and the first conductive structure form a contact structure at the bottom of the groove.

[0010] Optionally, the forming of the undoped first semiconductor layer at the bottom of each groove includes: epitaxial growth is performed at the bottom of each groove by a first silicon-containing gas to obtain the first semiconductor layer.

[0011] ​Optionally, the first semiconductor layer has a plurality of pores.

[0012] Optionally, the first silicon-containing gas includes silane.

[0013] Optionally, the thickness of the first semiconductor layer ranges from 30 Å to 45 Å.

[0014] Optionally, doping the first semiconductor layer includes: introducing a phosphorus-containing gas into the first semiconductor layer to cause the phosphorus-containing gas to react with the first semiconductor layer.

[0015] Optionally, forming a doped first conductive structure on the surface of the doped first semiconductor layer includes: growing at least one doped layer on the surface of the doped first semiconductor layer; and growing a second semiconductor layer on the surface of the doped layer.

[0016] Optionally, growing at least one doped layer on the surface of the first doped semiconductor layer includes: sequentially growing two phosphorus-containing semiconductor layers on the surface of the first doped semiconductor layer, wherein the phosphorus concentration of the first phosphorus-containing semiconductor layer is higher than the phosphorus concentration of the second phosphorus-containing semiconductor layer.

[0017] Optionally, the step of sequentially growing two phosphorus-containing semiconductor layers on the surface of the first doped semiconductor layer includes: performing epitaxial growth using a second silicon-containing gas and a phosphorus-containing gas to obtain the corresponding phosphorus-containing semiconductor layer.

[0018] Optionally, growing a second semiconductor layer on the surface of the doped layer includes: performing epitaxial growth on the surface of the doped layer using a second silicon-containing gas to obtain the second semiconductor layer.

[0019] Optionally, the second silicon-containing gas includes silane; the phosphorus-containing gas includes phosphine.

[0020] Optionally, the thickness of the phosphorus-containing semiconductor layer ranges from 220 Å to 280 Å; the thickness of the second semiconductor layer ranges from 80 Å to 120 Å.

[0021] Optionally, the second conductive structure has a concentration gradient structure.

[0022] This application also provides a semiconductor device, including:

[0023] A substrate, the substrate comprising a plurality of protrusions, wherein a groove is provided between two adjacent protrusions;

[0024] The contact structure located at the bottom of the groove includes a second conductive structure and a first conductive structure stacked in sequence. The second conductive structure is obtained by doping an undoped first semiconductor layer and then heat-treating it.

[0025] Optionally, the second conductive structure has a concentration gradient structure.

[0026] Optionally, the first conductive structure includes at least one doped layer and a second semiconductor layer stacked sequentially.

[0027] Optionally, the at least one doped layer comprises two phosphorus-containing semiconductor layers with decreasing concentration from bottom to top.

[0028] The aforementioned semiconductor device and its formation method first form an undoped first semiconductor layer at the bottom of a groove, and then dope the first semiconductor layer. Because the first semiconductor layer has pin holes, most impurity elements such as phosphorus (P) diffuse through these pin holes during the doping process, preventing excessive diffusion of P and other impurity elements to the active region at the bottom of the groove. A doped first conductive structure is then formed on the surface of the doped first semiconductor layer. The first semiconductor layer is then heat-treated to form a second conductive structure. This second conductive structure and the first conductive structure form a contact structure at the bottom of the groove, electrically leading out the active region and other functional structures at the bottom of the groove. In the process of forming the contact structure, this application avoids the problem of excessive diffusion of impurity elements such as P, meaning that P and other impurity elements are less likely to diffuse excessively to the active region at the bottom of the groove. This avoids short circuits between the bit line structure and conductive structures such as capacitor contacts, thereby improving the reliability of the resulting semiconductor device. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1a , Figure 1b , Figure 1c , Figure 1d and Figure 1e This is a schematic diagram of the semiconductor structure during the inventor's research process;

[0031] Figure 2 This is a flowchart of a method for forming a semiconductor device according to an embodiment of this application;

[0032] Figure 3a , Figure 3b , Figure 3c , Figure 3d , Figure 3e , Figure 3f , Figure 3g , Figure 3h , Figure 3i ,and Figure 3jThis is a schematic diagram of the structure obtained in each step of an embodiment of this application;

[0033] Figure 4 This is a flowchart of a partial method for forming a semiconductor device in one embodiment of this application;

[0034] Figure 5a , Figure 5b , Figure 5c , Figure 5d , Figure 5e and Figure 5f This is a schematic diagram of the structure obtained in each step of an embodiment of this application. Detailed Implementation

[0035] The inventor Figures 1a to 1c The semiconductor shown is studied, wherein the protrusion 121 in the cross-sectional view along the AA' direction has a bit line structure BL, which may include components such as bit line plugs, bit lines and / or bit line masks, and the protrusion 125 in the cross-sectional view along the BB' direction may include an isolation structure. The inventors have discovered that some methods typically use selective epitaxial growth (SEG) to generate the conductive structure 123, for example, SEG SiP can be formed using phosphorus-containing gas and silicon-containing gas to obtain the conductive structure 123. During the formation of SEG SiP, such as... Figure 1d and Figure 1e As shown, P element tends to diffuse excessively in the active region 112, which can easily lead to short circuits between the bit line structure BL and conductive structures such as capacitor contact plugs.

[0036] To address the aforementioned issues, this application first forms an undoped first semiconductor layer at the bottom of the groove, and then performs a doping process on the first semiconductor layer. Because the first semiconductor layer has pin holes, most impurity elements such as phosphorus (P) diffuse through these pin holes during the doping process, preventing excessive diffusion of P and other impurity elements to the active region at the bottom of the groove. A doped first conductive structure is formed on the surface of the doped first semiconductor layer, and the first semiconductor layer is then heat-treated to form a second conductive structure. This second conductive structure and the first conductive structure form a contact structure at the bottom of the groove, electrically leading out the active region and other functional structures at the bottom of the groove. During the formation of the contact structure, this application avoids the problem of excessive diffusion of impurity elements such as P, meaning that P and other impurity elements are less likely to diffuse excessively to the active region at the bottom of the groove. This avoids short circuits between the bit line structure and conductive structures such as capacitor contacts, thereby improving the reliability of the resulting semiconductor device.

[0037] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0038] This application provides a method for forming a semiconductor device in its first aspect, with reference to... Figure 2 As shown, the forming method includes steps S210 to S250.

[0039] S210, Reference Figure 3a and Figure 3b As shown, a substrate 310 is provided, the substrate 310 including a plurality of protrusions, such as Figure 3a As shown, the cross-section of substrate 310 in the AA' direction includes a first protrusion 321, as... Figure 3b As shown, the cross-section of the substrate 310 in the BB' direction includes a second protrusion 325, and a groove 322 is provided between two adjacent first protrusions 321 or second protrusions 325.

[0040] The substrate 310 may include semiconductor materials, such as silicon substrate, silicon-germanium substrate, or silicon-on-insulator substrate, etc. A plurality of spaced-apart isolation structures 311 and a plurality of active regions 312 isolated by the respective isolation structures 311 are formed within the substrate 310; at least a portion of the bottom of the exposed groove 322 exposes the active regions 312. The isolation structures 311 can be formed using a shallow trench isolation process; specifically, the isolation structures 311 can be formed in corresponding trenches, which may be referred to as "isolation trenches". The active regions 312 can form corresponding functional regions within the substrate 310, and contact structures are formed at the bottom of the groove 322 to contact the active regions 312, allowing the corresponding active regions 312 to be electrically led out.

[0041] The first protrusion 321 may contain functional structures such as bit line structures, which may be covered by a corresponding insulating layer for isolation and protection. Optionally, the bit line structure BL may include components such as bit line plugs, bit lines, and / or bit line masks. The second protrusion 325 may include an isolation structure.

[0042] S220, Reference Figure 3c and Figure 3d As shown, an undoped first semiconductor layer 341 is formed at the bottom of each of the grooves 322.

[0043] Optionally, the first semiconductor layer 341 can be made of materials such as DCS (silicon dichlorodihydrogen). The above step S220 first forms an undoped first semiconductor layer 341 at the bottom of the groove 322, which can prevent excessive diffusion of impurity elements such as P to the active region 312 at the bottom of the groove 322.

[0044] S230, Reference Figure 3e and Figure 3f As shown, the first semiconductor layer 341 is doped.

[0045] Optionally, doping the first semiconductor layer 341 includes: introducing a phosphorus-containing gas into the first semiconductor layer 341, causing the phosphorus-containing gas to react with the first semiconductor layer 341, thereby achieving the purpose of doping the first semiconductor layer 341. Optionally, the phosphorus-containing gas may include gases such as phosphine (PH3).

[0046] S240, Reference Figure 3g and Figure 3h As shown, a doped first conductive structure 342 is formed on the surface of the first semiconductor layer 341 after doping. Optionally, the first conductive structure 342 may include a P-doped semiconductor structure, which may be obtained by reacting SiH4 and PH3 together.

[0047] S250, reference Figure 3i and Figure 3j As shown, the first semiconductor layer 341 is heat-treated to activate the doped phosphorus element, so that the doped first semiconductor layer 341 forms a second conductive structure 343. The second conductive structure 343 and the first conductive structure 342 form a contact structure at the bottom of the groove 322. This contact structure can electrically lead out the active region 312 and other structures at the bottom of the groove 322.

[0048] Optionally, the contact structure described above may include conductive structures such as solder pads or contact plugs.

[0049] Optionally, in step S250 above, the heat treatment may include processes such as annealing that can activate the doped elements and form the corresponding second conductive structure 343 in the doped first semiconductor layer 341. The temperature range of the heat treatment may include 380°C to 450°C, for example, the temperature of the heat treatment may be 380°C, 400°C, 420°C or 450°C, etc.

[0050] The above-mentioned method for forming semiconductor devices can form Figure 1a The semiconductor structures shown, such as memory chips, have contact structures that are consistent in cross-sectional views in all directions, for example... Figure 3i for Figure 1a Cross-sectional view along line AA'. Figure 3j for Figure 1aA cross-sectional view along line BB'.

[0051] The above-described method for forming a semiconductor device involves first forming an undoped first semiconductor layer 341 at the bottom of the groove 322, and then performing a doping treatment on the first semiconductor layer 341. This process utilizes the pores (pins) within the first semiconductor layer. The pores allow most impurity elements, such as phosphorus (P), to diffuse through the pores during doping, preventing excessive diffusion of P to the active region 312 at the bottom of the groove 322. A first conductive structure 342 is then formed on the surface of the first semiconductor layer 341 after doping. The first semiconductor layer 341 is then heat-treated to form a second conductive structure 343. This second conductive structure 343 and the first conductive structure 342 form a contact structure at the bottom of the groove 322, electrically leading out the active region 312 and other functional structures at the bottom of the groove 322. During the formation of the contact structure, excessive diffusion of P and other impurity elements is avoided, preventing excessive diffusion to the active region 312 at the bottom of the groove 322. This avoids short circuits between the bit line structure and conductive structures such as capacitor contacts, thereby improving the reliability of the resulting semiconductor device.

[0052] In one embodiment, forming an undoped first semiconductor layer 341 at the bottom of each of the grooves 322 includes: performing epitaxial growth at the bottom of each of the grooves 322 using a first silicon-containing gas to obtain the first semiconductor layer 341. Optionally, this embodiment can utilize a first silicon-containing gas and an additional gas to perform epitaxial growth to form the first semiconductor layer 341. Optionally, the first silicon-containing gas may include at least one of silane (SiH4), dichlorosilane (SiH4), silane (SiH2Cl2, DCS), and dichlorosilane (Si2H6). The additional gas may include HCl. Performing epitaxial growth to obtain the first semiconductor layer 341 in this embodiment simplifies the formation process.

[0053] Preferably, the first silicon-containing gas includes silane (Si2H6).

[0054] Optionally, the thickness of the first semiconductor layer ranges from 30 Å to 45 Å. For example, the thickness of the first semiconductor layer can be 30 Å, 35 Å, 40 Å or 45 Å, etc., to effectively prevent excessive diffusion of impurity elements such as P, and also to facilitate control of the size of the second conductive structure 343 to be formed, thereby facilitating control of the size of the contact structure to be formed.

[0055] In one example, the first semiconductor layer 341 has multiple pores to allow for sufficient doping and improved doping effect when phosphorus-containing gas is subsequently introduced.

[0056] In one example, the first semiconductor layer 341 has a low doping concentration at the bottom and a higher doping concentration from bottom to top, which can further prevent phosphorus diffusion. Correspondingly, the second conductive structure 343 has a concentration gradient structure with a low phosphorus concentration at the bottom and a high phosphorus concentration at the top, which can improve the overall conductivity of the second conductive structure 343.

[0057] In one embodiment, reference Figure 4 As shown, in step S240, a doped first conductive structure 342 is formed on the surface of the doped first semiconductor layer 341, including steps S241 and S242.

[0058] S241, at least one doped layer is grown on the surface of the first semiconductor layer 341 after doping; wherein the number of doped layers can be determined according to relevant process conditions and interconnection requirements, for example, referring to... Figure 5a and Figure 5b As shown, the doped layer on the surface of the first semiconductor layer 341 includes two doped layers: doped layer 342a and doped layer 342b.

[0059] S242, Reference Figure 5c and Figure 5d As shown, an undoped second semiconductor layer 342c is grown on the surface of the doped layer, and together with the doped layers 342a and 342b, forms a first conductive structure 342. Since the top layer of the first conductive structure 342 is formed by the undoped second semiconductor layer 342c, excessive diffusion of impurity elements such as P can be prevented on the top layer of the first conductive structure 342, further improving the performance of the resulting semiconductor device.

[0060] Further, refer to Figure 5e and Figure 5f As shown, the first semiconductor layer 341 is heat-treated to activate the doped phosphorus element, so that the doped first semiconductor layer 341 forms a second conductive structure 343.

[0061] In one example, growing at least one doped layer on the surface of the doped first semiconductor layer 341 includes: sequentially growing two phosphorus-containing semiconductor layers on the surface of the doped first semiconductor layer 341, such as... Figures 5a to 5d As shown, the phosphorus concentration of the first phosphorus-containing semiconductor layer 342a is higher than that of the second phosphorus-containing semiconductor layer 342b. This higher phosphorus concentration in the first layer 342a effectively prevents excessive phosphorus diffusion and also improves the conductivity of the formed first conductive structure 342.

[0062] In one example, the sequential growth of two phosphorus-containing semiconductor layers on the surface of the doped first semiconductor layer 341 includes: performing epitaxial growth using a second silicon-containing gas and a phosphorus-containing gas to obtain the corresponding phosphorus-containing semiconductor layer. This example, using a second silicon-containing gas and a phosphorus-containing gas for epitaxial growth, ensures selectivity relative to the dielectric material. Specifically, this example can also use a second silicon-containing gas, a phosphorus-containing gas, and a chlorine-containing gas to perform epitaxial growth to obtain the corresponding phosphorus-containing semiconductor layer. By controlling the chlorine functional groups on the epitaxial growth surface, the growth rate can be increased as adsorption accelerates. Optionally, the second silicon-containing gas includes silane (SiH4); the phosphorus-containing gas includes phosphine (PH3); and the chlorine-containing gas may include HCl. Optionally, the thickness of each phosphorus-containing semiconductor layer ranges from 220 Å to 280 Å, for example, the thickness of each phosphorus-containing semiconductor layer can be 220 Å, 250 Å, or 280 Å, etc. Optionally, the temperature range for generating the phosphorus-containing semiconductor layer includes 450°C to 550°C, for example, the temperature for generating the phosphorus-containing semiconductor layer can be 450°C, 470°C, 500°C, 530°C or 550°C.

[0063] Specifically, in this example, a first phosphorus-containing semiconductor layer 342a can be grown on the surface of the doped first semiconductor layer 341, and then a second phosphorus-containing semiconductor layer 342b can be grown on the surface of the first phosphorus-containing semiconductor layer 342a. Optionally, the temperature for growing the second phosphorus-containing semiconductor layer 342b can be higher than the temperature for growing the first phosphorus-containing semiconductor layer 342a. For example, the temperature for growing the first phosphorus-containing semiconductor layer 342a can be 470°C, and the temperature for growing the second phosphorus-containing semiconductor layer 342b can be 530°C.

[0064] In one example, growing a second semiconductor layer 342c on the surface of the doped layer includes: performing epitaxial growth on the surface of the doped layer using a second silicon-containing gas to obtain the second semiconductor layer 342c. Optionally, this example can utilize a second silicon-containing gas and an additional gas to perform epitaxial growth to form the second semiconductor layer 342c. Optionally, the second silicon-containing gas may include silane (SiH4); the additional gas may include HCl. Optionally, the thickness of the second semiconductor layer 342c ranges from 80 Å to 120 Å, for example, the thickness of the second semiconductor layer 342c may be 80 Å, 100 Å, or 120 Å. Optionally, the temperature range for growing the second semiconductor layer 342c ranges from 500°C to 550°C, for example, the temperature for growing the second semiconductor layer 342c may be 500°C, 530°C, or 550°C.

[0065] The above method for forming a semiconductor device first forms an undoped first semiconductor layer 341 at the bottom of the groove 322, which can prevent excessive diffusion of impurity elements such as P to the active region 312 at the bottom of the groove 322. Then, the first semiconductor layer 341 is doped, and a doped first conductive structure 342 is formed on the surface of the doped first semiconductor layer 341. The first semiconductor layer 341 is then heat-treated to form a second conductive structure 343. In this way, the second conductive structure 343 and the first conductive structure 342 can form a contact structure at the bottom of the groove 322 to electrically lead out functional structures such as the active region 312 at the bottom of the groove 322. During the formation of the contact structure, the problem of excessive diffusion of impurity elements such as P can be avoided, that is, impurity elements such as P are difficult to diffuse excessively to the active region 312 at the bottom of the groove 322. This can avoid the problem of short circuit between the bit line structure and conductive structures such as capacitor contact plugs, thereby improving the reliability of the obtained semiconductor device.

[0066] This application provides a semiconductor device in a second aspect, as referenced... Figure 3i and Figure 3j As shown, the above-mentioned semiconductor device includes:

[0067] Substrate 310, the substrate 310 including a plurality of protrusions, wherein a groove 322 is provided between two adjacent protrusions; as Figure 3i As shown, the cross-section of substrate 310 in the AA' direction includes a first protrusion 321, as... Figure 3j As shown, the cross-section of the substrate 310 in the BB' direction includes a second protrusion 325, and a groove 322 is provided between two adjacent first protrusions 321 or second protrusions 325.

[0068] The contact structure located at the bottom of the groove 322 includes a second conductive structure 343 and a first conductive structure 342 stacked in sequence. The second conductive structure 343 is obtained by doping an undoped first semiconductor layer 341 and then heat-treating it.

[0069] In one embodiment, the second conductive structure 343 has a concentration gradient structure with a low phosphorus concentration at the bottom and a high phosphorus concentration at the top, which can improve the conductivity of the entire second conductive structure 343 while preventing excessive diffusion of phosphorus.

[0070] In one embodiment, the first conductive structure 342 includes at least one doped layer and a second semiconductor layer 342c stacked sequentially.

[0071] Optionally, the at least one doped layer comprises two phosphorus-containing semiconductor layers with decreasing concentration from bottom to top. For example, the at least one doped layer comprises two doped layers from bottom to top: doped layer 342a and doped layer 342b, with the phosphorus concentration of doped layer 342a being higher than that of doped layer 342b.

[0072] The semiconductor device described above can be formed using the semiconductor device formation method described in any of the above embodiments, and has all the beneficial effects of the semiconductor device formation method described in any of the above embodiments, which will not be repeated here.

[0073] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if it is not necessarily structurally equivalent to the disclosed structure that performs the functions in the exemplary implementations of this specification shown herein.

[0074] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0075] Furthermore, it should be understood that in the description of this application, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Additionally, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. Moreover, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0076] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to implement and use it. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A method of forming a semiconductor device, characterized by, The forming method comprises: providing a substrate comprising a plurality of protrusions, and a plurality of grooves between two adjacent protrusions; forming an undoped first semiconductor layer at the bottom of each groove, the first semiconductor layer having a plurality of pores; doping the first semiconductor layer; forming a doped first conductive structure on the surface of the doped first semiconductor layer; heat treating the first semiconductor layer to form a second conductive structure, the second conductive structure and the first conductive structure forming a contact structure at the bottom of the groove.

2. The method of forming a semiconductor device according to claim 1, wherein The forming an undoped first semiconductor layer at the bottom of each groove comprises: performing epitaxial growth at the bottom of each groove by a first silicon-containing gas to obtain the first semiconductor layer.

3. The method of forming a semiconductor device according to claim 2, wherein The first silicon-containing gas comprises disilane.

4. The method of forming a semiconductor device according to claim 2, wherein The thickness of the first semiconductor layer ranges from 30 Å to 45 Å.

5. The method of forming a semiconductor device of claim 1, wherein, The doping the first semiconductor layer comprises: introducing a phosphorus-containing gas into the first semiconductor layer to react the phosphorus-containing gas with the first semiconductor layer.

6. The method of forming a semiconductor device of claim 1, wherein, The forming a doped first conductive structure on the surface of the doped first semiconductor layer comprises: growing at least one doped layer on the surface of the doped first semiconductor layer; growing a second semiconductor layer on the surface of the doped layer.

7. The method of forming a semiconductor device according to claim 6, wherein The growing at least one doped layer on the surface of the doped first semiconductor layer comprises: sequentially growing two phosphorus-containing semiconductor layers on the surface of the doped first semiconductor layer, the first phosphorus-containing semiconductor layer having a higher phosphorus concentration than the second phosphorus-containing semiconductor layer.

8. The method of forming a semiconductor device according to claim 7, wherein The sequentially growing two phosphorus-containing semiconductor layers on the surface of the doped first semiconductor layer comprises: performing epitaxial growth by a second silicon-containing gas and a phosphorus-containing gas to obtain the corresponding phosphorus-containing semiconductor layer.

9. The method of claim 8, wherein The growing a second semiconductor layer on the surface of the doped layer comprises: performing epitaxial growth on the surface of the doped layer by a second silicon-containing gas to obtain the second semiconductor layer.

10. The method of claim 8, wherein The second silicon-containing gas comprises silane; and the phosphorus-containing gas comprises phosphine.

11. The method of claim 9, wherein The thickness of the phosphorus-containing semiconductor layer ranges from 220 Å to 280 Å; and the thickness of the second semiconductor layer ranges from 80 Å to 120 Å.

12. The method of forming a semiconductor device of claim 1, wherein, The second conductive structure has a concentration gradient structure.

13. A semiconductor device, characterized by comprising: The forming method comprises: providing a substrate comprising a plurality of protrusions, and a plurality of grooves between two adjacent protrusions; a contact structure at the bottom of the groove, the contact structure comprising a second conductive structure and a first conductive structure stacked in sequence, the second conductive structure being obtained by doping an undoped first semiconductor layer and heat treating, the first semiconductor layer having a plurality of pores.

14. The semiconductor device of claim 13, wherein, The second conductive structure has a concentration gradient structure.

15. The semiconductor device of claim 13, wherein, The first conductive structure comprises at least one doped layer and a second semiconductor layer stacked in sequence.

16. The semiconductor device of claim 15, wherein, The at least one doped layer comprises two phosphorus-containing semiconductor layers with decreasing concentration from bottom to top. The two phosphorus-containing semiconductor layers have different phosphorus concentrations.

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