Wiring substrate, method for manufacturing the same, and display panel

Abstract

The embodiment of the present disclosure provides a wiring substrate, a preparation method thereof and a display panel. The wiring substrate comprises a substrate, a plurality of metal wiring layers and a plurality of metal bonding points. The plurality of metal wiring layers are located above the substrate, and an insulating layer is arranged between two adjacent metal wiring layers. Each metal wiring layer comprises a plurality of metal bumps and a plurality of metal lines connected to the metal bumps respectively. The plurality of metal bumps are located in a chip bonding area of the wiring substrate. The plurality of metal bonding points are located above the plurality of metal wiring layers and fall within the chip bonding area. An insulating layer is arranged between the plurality of metal bonding points and the plurality of metal wiring layers. Each metal bonding point corresponds to one metal bump respectively. Each metal bonding point is connected to the corresponding metal bump through a metal via. The embodiment of the present disclosure can increase the number of channels of the wiring substrate.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a wiring substrate and its preparation method, as well as a display panel. Background Technology

[0002] Large-sized electronic products such as LCD monitors, LCD TVs, and plasma TVs, as well as small and medium-sized electronic products such as mobile phones and digital cameras, are all trending towards being thin, light, and compact. This necessitates a new generation of packaging technologies that are high-density, small-volume, and can be freely installed to meet these requirements.

[0003] With the continuous development of 3D (3D) display technology, the market demand for 3D display products is rapidly increasing. Among the main development trends, increasing the resolution of 3D products (16K, 32K, etc.) to support the amount of information displayed is a key focus. To support technologies such as multi-viewpoints and X-Zones, 3D display products require a significantly increased number of data channels. For example, a 4K, 32View 3D light field display product requires 32K channels, a substantial increase compared to traditional 2D display products. Therefore, higher resolution IC packaging technology is needed to handle the massive data transmission. High-channel-count IC packaging technology, supporting more functions, has become a limiting factor for the future development of 3D display products. Summary of the Invention

[0004] This disclosure provides a wiring substrate and a method for preparing the same, as well as a display panel, to solve or alleviate one or more technical problems in the prior art.

[0005] As a first aspect of the present disclosure, an embodiment of the present disclosure provides a wiring substrate, comprising:

[0006] Substrate;

[0007] A multilayer metal wiring layer is located above a substrate, with an insulating layer between adjacent metal wiring layers. Each metal wiring layer includes multiple metal bumps and metal lines connected to each of the metal bumps. The multiple metal bumps are located in the chip bonding area of ​​the wiring substrate.

[0008] Multiple metal bonding points are located above the multilayer metal wiring layer and fall within the chip bonding area. An insulating layer is provided between the metal bonding points and the multilayer metal wiring layer. Each metal bonding point corresponds to a metal bump. Each metal bonding point is connected to its corresponding metal bump through a metal via.

[0009] As a second aspect of this disclosure, this disclosure provides a method for fabricating a wiring substrate, comprising:

[0010] Multiple metal wiring layers are formed on a substrate, wherein an insulating layer is provided between two adjacent metal wiring layers, and each metal wiring layer includes multiple metal bumps and metal lines connected to each of the multiple metal bumps, wherein the multiple metal bumps are located in the chip bonding area of ​​the wiring substrate.

[0011] Multiple metal bonding points are formed above the multilayer metal wiring layer and within the chip bonding area. An insulating layer is provided between the multiple metal bonding points and the multilayer metal wiring layer. Each metal bonding point corresponds to a metal bump. Each metal bonding point is connected to its corresponding metal bump through a metal via.

[0012] As a third aspect of the present disclosure, the present disclosure provides a substrate reel including a plurality of wiring substrates whose ends are added together sequentially, wherein the wiring substrate is the wiring substrate provided in any embodiment of the present disclosure.

[0013] As a fourth aspect of the present disclosure, the present disclosure provides a display panel including a wiring substrate provided in any embodiment of the present disclosure.

[0014] The technical solution provided in this disclosure provides a multi-layer metal wiring layer, in which the metal bumps located in the chip bonding area of ​​each layer are connected to the metal bonding points of the top layer through metal vias, thereby increasing the number of wirings on the wiring substrate and increasing the number of output channels of the chip.

[0015] The above overview is for illustrative purposes only and is not intended to be limiting in any way. Further aspects, embodiments, and features of this disclosure will become readily apparent from the accompanying drawings and the following detailed description, in addition to the illustrative aspects, embodiments, and features described above. Attached Figure Description

[0016] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments according to this disclosure and should not be construed as limiting the scope of this disclosure.

[0017] Figure 1 This is a cross-sectional view of a wiring substrate according to an embodiment of the present disclosure;

[0018] Figure 2A This is an orthographic projection of a metal component in a wiring substrate according to an embodiment of the present disclosure onto a substrate;

[0019] Figure 2B This is an orthographic projection of a metal component on a substrate in a wiring substrate with metal layers having different data, according to an embodiment of the present disclosure.

[0020] Figure 3 This is a top view of a wiring substrate according to an embodiment of the present disclosure;

[0021] Figure 4 This is a top view of a wiring substrate according to another embodiment of the present disclosure;

[0022] Figure 5 This is a cross-sectional view of a wiring substrate according to another embodiment of the present disclosure;

[0023] Figure 6 This is a cross-sectional view of the bending region of a wiring substrate according to another embodiment of the present disclosure;

[0024] Figure 7 This is a cross-sectional view of the bending region of a wiring substrate according to another embodiment of the present disclosure;

[0025] Figure 8 This is a cross-sectional view of the bending region of a wiring substrate according to another embodiment of the present disclosure;

[0026] Figures 9A to 9C This is a cross-sectional view of a wiring substrate according to an embodiment of the present disclosure;

[0027] Figure 10 This is a top view of a wiring substrate according to another embodiment of the present disclosure;

[0028] Figure 11 This is an orthographic projection of the metal lines of a wiring substrate according to an embodiment of the present disclosure onto a substrate;

[0029] Figure 12 This is an orthographic projection of the metal lines of a wiring substrate according to another embodiment of the present disclosure onto a substrate;

[0030] Figure 13A This is a top view of a wiring substrate without green oil coating according to an embodiment of the present disclosure;

[0031] Figure 13B This is a top view of a wiring substrate coated with green oil according to an embodiment of the present disclosure;

[0032] Figure 14 This is a cross-sectional view of a wiring substrate coated with green oil according to an embodiment of this disclosure;

[0033] Figure 15 This is a flowchart of a method for fabricating a wiring substrate according to an embodiment of the present disclosure;

[0034] Figure 16 This is a top view of a large board including multiple wiring substrates according to an embodiment of the present disclosure;

[0035] Figure 17 This is a top view of a wiring substrate with positioning holes according to an embodiment of the present disclosure;

[0036] Figure 18 This is a top view of a wiring substrate having positioning holes and transmission holes according to an embodiment of the present disclosure;

[0037] Figure 19A This is a top view of a wiring substrate having a connection area according to an embodiment of the present disclosure;

[0038] Figure 19B This is a top view of a wiring substrate having a connection area according to another embodiment of the present disclosure;

[0039] Figure 20A This is a top view of two spliced ​​wiring substrates according to an embodiment of the present disclosure;

[0040] Figure 20B This is a cross-sectional view of two spliced ​​wiring substrates according to an embodiment of this disclosure;

[0041] Figure 21 This is a schematic diagram of the back membrane according to an embodiment of the present disclosure;

[0042] Figure 22 This is a schematic diagram of a tape reel according to an embodiment of the present disclosure. Detailed Implementation

[0043] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this disclosure. Therefore, the drawings and description are to be considered exemplary in nature and not restrictive.

[0044] Figure 1 This is a cross-sectional view of a wiring substrate according to an embodiment of the present disclosure. Figure 2A This is an orthographic projection of a metal component in a wiring substrate according to an embodiment of this disclosure onto a substrate. For example... Figure 1 As shown, the wiring substrate includes a substrate 101, a multilayer metal wiring layer 102, and multiple metal bonding points 103. Among them, Figure 1 Figure 2 illustrates a three-layer metal wiring layer, but this disclosure is not limited to three layers; it can be two, four, five, or more layers. Figure 1As shown, a multilayer metal wiring layer is located above the substrate 101. An insulating layer 104 is provided between adjacent metal wiring layers 102. Each metal wiring layer 102 includes multiple metal bumps 105 and metal lines 106 connected to each of the multiple metal bumps 105. The multiple metal bumps 105 are located in the chip bonding area of ​​the wiring substrate. Multiple metal bonding points 103 are located above the multilayer metal wiring layers 102 and fall within the chip bonding area. An insulating layer 104 is provided between them and the multilayer metal wiring layers 102. Each metal bonding point 103 corresponds to a metal bump 105. Each metal bonding point 103 is connected to its corresponding metal bump 105 through a metal via 107.

[0045] like Figure 2A As shown, the orthographic projections of the metal bonding points 103 on the substrate 101 do not overlap, the orthographic projections of the metal bumps 105 on the substrate 101 do not overlap, and the orthographic projections of the metal lines on the substrate 101 may or may not overlap, or may partially overlap. The orthographic projections of the metal bonding points 103 and their corresponding metal bumps 105 partially overlap.

[0046] Figure 2B This is a top perspective view comparing the chip bonding regions of wiring substrates with different numbers of metal wiring layers according to an embodiment of this disclosure. From Figure 2B It is known that for wiring substrates with the same planar area, the more layers there are, the more metal lines can be arranged, which can provide more output channels for the chip.

[0047] Figure 3 This is a top view of a wiring substrate according to an embodiment of the present disclosure. The wiring substrate may include a chip bonding area, a bending area, and a display panel bonding area, etc. Metal lines in each metal wiring layer 102 extend from the chip bonding area to the bending area of ​​the wiring substrate. The chip can be connected to the wiring substrate through the chip bonding area, and the wiring substrate is connected to the display panel through the display panel bonding area. Thus, the chip can transmit signals to the display panel through the wiring substrate.

[0048] In this configuration, all metal lines 106 extend from the same side along the length of the chip bonding area to the bending area of ​​the wiring substrate. For example... Figure 4 As shown, the metal line 106 can extend from either side of the chip bonding area along its length and enter the bending area.

[0049] Figure 5 This is a cross-sectional view of the bending region in a wiring substrate according to an embodiment of the present disclosure.

[0050] To improve the bending characteristics of the wiring substrate, such as Figure 5As shown, the insulating layer 104 may include an organic dielectric layer 108 and an inorganic composite layer 109, with the organic dielectric layer 108 disposed on the side of the inorganic composite layer 109 away from the substrate 101. The organic dielectric layer 108 is made of photosensitive polyimide (PSPI) and has a thickness of L1, where 2μm ≤ L1 ≤ 5μm. Figure 6 As shown, in the bending region, the thickness of the organic dielectric layer 108 can be greater than that of the inorganic composite layer 109. The inorganic composite layer 109 is made of silicon nitride (SiN) and has a thickness of L2, where 10nm ≤ L2 ≤ 200nm.

[0051] Therefore, to ensure the bending characteristics and excellent electrical properties of the substrate, prevent crosstalk between different metal layers, and avoid Cu oxidation, photosensitive polyimide can be used as the material of the organic dielectric layer 108, and SiN material can be used as the material of the inorganic composite layer 109 as the insulating layer 104 of the substrate. PSPI has a high elongation at break (>40%), a low Young's modulus (<10 GPa), which can meet the bending performance requirements of the substrate, and a low dielectric constant (≦3.0 / GHz) to reduce crosstalk between output signals.

[0052] To further improve the bending performance of the substrate, the inorganic composite layer 109 in the insulating layer 104 can be etched in the bending area to remove the inorganic composite layer 109 material between adjacent metal lines 106 in the same metal wiring layer 102, leaving only the inorganic composite layer 109 material on the sidewall of the metal line 106 and the side surface away from the substrate 101.

[0053] like Figure 7 As shown, it is a cross-sectional view of the bending region before the inorganic composite layer 109 is etched. Figure 8 As shown, it is a cross-sectional view of the bending region after pattern etching of the inorganic composite layer 109.

[0054] For example, such as Figure 8 As shown, in the bending region, for the insulating layer 104 between two adjacent metal wiring layers 102, the orthographic projection of the organic dielectric layer 108 in the insulating layer 104 onto the substrate 101 covers the bending region, and the orthographic projection of the inorganic composite layer 109 in the insulating layer 104 onto the bending region includes multiple sub-projections, and each sub-projection does not overlap with each other and covers its corresponding metal line 106.

[0055] In some embodiments, such as Figure 5 As shown, the wiring substrate may further include a flexible film 110 located between the substrate 101 and the multilayer metal wiring layer 102, and a water-insulating inorganic film 111 is provided on the side of the flexible film away from the substrate 101.

[0056] Among them, the material of the flexible film can be polyimide (PI), and the thickness is L3, where 10 μm ≤ L3 ≤ 40 μm.

[0057] Among them, the material of the water-insulating inorganic film can be silicon dioxide or silicon nitride, and the thickness is L4, where 10 nm ≤ L4 ≤ 200 nm. Thus, the flexible film on the wiring substrate can avoid water absorption of polyimide.

[0058] Exemplarily, in order to improve the bending performance of the substrate, the thickness L3 of the flexible film can be 20 μm, and the thickness L4 of the water-insulating inorganic film on the surface of the flexible film is 50 nm ≤ L4 ≤ 200 nm.

[0059] In some embodiments, for the metal in the wiring substrate, the materials of the metal bumps 105 and the metal wires 106 can be metal materials composed of at least one of aluminum, copper, titanium, molybdenum, and nickel, and the thickness is L5, where 300 nm ≤ L5 ≤ 1000 nm. The metal bumps 105 and the metal wires 106 can be multi-layer alloys composed of these metals, such as Ti / Al / Ti alloy, MoTiNi / Cu / MoTiNi alloy, etc. In order to improve the conductive performance of the metal, multi-layer copper alloys can be selected, such as Mo / Cu / Mo alloy, and its thickness can be 300 nm to 1000 nm. If copper alloy or copper metal is used, wet etching needs to be adopted when forming the metal wires 106 and the metal bumps 105. The interval between adjacent metal wires 106 can be between 1 and 2 μm.

[0060] Exemplarily, the line width of the metal wire 106 can be L6, where 5 μm ≤ L6 ≤ 7 μm.

[0061] As Figures 9A to 9C shown, the metals of different layers are transferred through the opening of the insulating layer 104 and connected to the metal bonding points 103 on the top layer. Among them, as Figure 9C shown, the metal bumps 105 (7, 8, 9) in the first-layer metal wiring layer are connected to the metal bonding points 103 on the top layer through 3 via holes. As Figure 9B shown, the metal bumps 105 (4, 5, 6) in the second-layer metal wiring layer are connected to the metal bonding points 103 on the top layer through 2 via holes. As Figure 9A shown, the metal bumps 105 (1, 2, 3) in the third-layer metal wiring layer are connected to the metal bonding points 103 on the top layer through 1 via hole.

[0062] In order to maximize the number of wirings, it is required that the diameter of the metal vias 107 is less than 3 μm. Exemplarily, the diameter of the metal vias 107 is L7, where 0 < L7 ≤ 3 μm. In order to determine the overlapping area, the metal vias 107 are set to be long strip-shaped, where the length is L8, and 10 μm ≤ L8 ≤ 30 μm.

[0063] In some embodiments, the metal bonding points 103 can be fabricated by electroplating. The thickness of the metal bonding points 103 is L9, where 5μm ≤ L9 ≤ 8μm. Since the bonding area requires a thick metal as the gold finger, this thickness meets the bonding requirements.

[0064] like Figure 10 As shown, the wiring substrate may also include a circuit board bonding area (PCB bonding area), which is connected to the chip bonding area via metal lines 106. The metal lines 106 in the PCB bonding area are also made of thick metal and have a line width greater than 16μm.

[0065] To ensure bonding effectiveness in the bonding region, the linewidth of the metal bonding point 103 in the top layer can be designed to be 6 μm, and the volume to be 15 μm. 3 The linewidth of the metal bumps 105 in the metal wiring layer 102 can be designed to be 12 μm, and the volume to be 9 μm. 3 .

[0066] The metal bonding point 103 can be made of copper. The surface of the metal bonding point 103 away from the substrate 101 is coated with a tin layer to prevent copper oxidation and facilitate the formation of gold-tin eutectic bonding with the chip. The thickness of the tin layer is L10, where 0.1μm≤L10≤0.2μm.

[0067] To reduce the overlap area of ​​the orthographic projections of the metal lines 106 on the substrate 101, the orthographic projections of the metal lines 106 from different layers can be staggered in terms of contrast. For example, as Figure 11 As shown, in the bending region, the orthographic projections of the metal lines 106 in the multilayer metal wiring layer 102 onto the substrate 101 do not overlap. Specifically, 210 represents the metal line 106 in the first metal wiring layer, 220 represents the metal line 106 in the second metal wiring layer, and 220 represents the metal line 106 in the third metal wiring layer.

[0068] Furthermore, as shown in Figure 9, the metal lines 106 in the metal wiring layer 102 extend from the chip bonding area to the bending area of ​​the wiring substrate, and from the bending area to the panel bonding area. For the mutually aligned metal lines 106 that fall within the panel bonding area and are located in different metal wiring layers 102, their orthographic projections on the substrate 101 completely overlap. Their projection patterns can be shown as follows: Figure 12 As shown. Among them, 210 is the metal line 106 in the first metal wiring layer, 220 is the metal line 106 in the second metal wiring layer, and 220 is the metal line 106 in the third metal wiring layer.

[0069] Similarly, in the PCB bonding area, the orthographic projections of the mutually aligned metal lines 106 located on different metal wiring layers 102 onto the substrate 101 completely overlap. This allows light to pass through the non-overlapping areas, facilitating the detection of signals after bonding.

[0070] Figure 13A This is a top view of the wiring substrate without the top layer of green solder mask applied. Figure 13B This is a top view of the wiring board with the top layer coated with green paint.

[0071] like Figure 13A and Figure 13B As shown, a layer of solder resist (SR) with a thickness of 10 to 20 μm is applied to the top layer of the wiring substrate, in the area outside the chip bonding area, panel bonding area, and PCB bonding area. To ensure film bending performance, the solder resist must be made of a high-bending-resistance adhesive, requiring high tensile strength at break and low Young's modulus.

[0072] For the aforementioned wiring substrate, film layer simulation was performed on the bending region. In this region, the inorganic SiN film is most prone to fracture. Therefore, the maximum strain force on the SiN is minimized by adjusting the film structure. Figure 14 As shown, for example, the flexible film 110 and the green oil SR have a thickness of 20 μm, the organic dielectric layer 108 has a thickness of 2 μm, and the inorganic composite layer 109 is as thin as possible while ensuring complete coverage of the metal bumps and metal lines on the side away from the substrate and the sidewalls, and its thickness can be 10 to 100 nm.

[0073] Figure 15 This is a flowchart of a method for fabricating a wiring substrate according to an embodiment of the present disclosure.

[0074] like Figure 1 and Figure 15 As shown, the preparation method may include:

[0075] S110, a multilayer metal wiring layer 102 is formed on the substrate 101, wherein an insulating layer 104 is provided between two adjacent metal wiring layers 102, and each metal wiring layer 102 includes a plurality of metal bumps 105 and a metal line 106 connected to each of the plurality of metal bumps 105, and the plurality of metal bumps 105 are located in the chip bonding area of ​​the wiring substrate.

[0076] S120, a plurality of metal bonding points 103 are formed above the multilayer metal wiring layer 102 and within the chip bonding area. An insulating layer 104 is provided between the plurality of metal bonding points 103 and the multilayer metal wiring layer 102. Each metal bonding point 103 is connected to its corresponding metal bump 105 through a metal via 107.

[0077] In some embodiments, the multilayer metal wiring layer 102 includes an M layer. For example... Figure 1 As shown, in step S110 above, forming a multilayer metal wiring layer 102 on the substrate 101 may include:

[0078] A first metal wiring layer 102 is formed on the substrate 101;

[0079] Starting from N=1, perform the following operations: form the Nth insulating layer 104 on the Nth metal wiring layer 102; make an opening in the Nth insulating layer 104 for the orthographic projection of the metal bump 105 in the Nth metal wiring layer 102 to expose the metal bump 105 in the Nth metal wiring layer 102; deposit metal on the Nth insulating layer 104 and perform pattern etching to form the (N+1)th metal wiring layer 102; increment N by one and return to continue the operation until N is greater than or equal to M-1 and then stop the operation; where N and M are both positive integers greater than 1.

[0080] In some embodiments, such as Figure 1 As shown, in step S120 above, forming a plurality of metal bonding points 103 above the multilayer metal wiring layer 102 and within the chip bonding region may include:

[0081] An Mth insulating layer 104 is formed on the Mth metal wiring layer 102;

[0082] An opening is made in the Mth insulating layer 104 to expose the metal bump 105 in the Mth metal wiring layer 102 by the orthogonal projection of the metal bump 105.

[0083] Metal is deposited on the Mth insulating layer 104 and patterned to form multiple metal bonding points 103.

[0084] In some embodiments, such as Figure 5 and Figure 8 As shown, the Nth insulating layer 104 includes an Nth organic dielectric layer 108 and an Nth inorganic composite layer 109. Metal lines 106 in the metal wiring layer 102 extend from the chip bonding region to the bending region of the wiring substrate. In the aforementioned cyclic operation, the formation of the Nth insulating layer 104 on the Nth metal wiring layer 102 may include:

[0085] An Nth inorganic composite layer 109 is formed on the Nth metal wiring layer 102;

[0086] In the bending region, the Nth inorganic composite layer 109 is etched and the inorganic composite layer 109 material between adjacent metal lines 106 located in the same metal wiring layer 102 is removed to expose the N-1th organic dielectric layer 108, and the sidewalls of the metal lines 106 are covered with the inorganic composite layer 109 material.

[0087] An organic dielectric is deposited on the side of the wiring substrate away from the substrate 101 to form the Nth organic dielectric layer 108.

[0088] After obtaining the above wiring substrate, as Figure 13B As shown, green solder mask is applied to the top layer of the substrate, excluding the panel bonding area, chip bonding area, and PCB board bonding area.

[0089] After obtaining the above wiring substrate, the substrate can be laser lifted-off (LLO) to remove the substrate, i.e., the glass substrate, to obtain a flexible substrate.

[0090] In practical applications, such as Figure 16 As shown, multiple wiring substrates as described above can be formed on the large board. The glass substrate of the large board is removed to obtain the following... Figure 16 The flexible substrate shown is then laser-cut. Specifically, the large flexible substrate is cut into strips along the direction of the conveying hole, and positioning holes are also cut. Its long side can be 1800 mm. Therefore, the maximum length of the strip flexible plate is less than 1800 mm. Figure 17 As shown, a positioning hole is formed at each of the four corners of the long, flexible sheet. The positioning hole has a diameter of 1mm to 3mm and can be used for punching positioning.

[0091] like Figure 18 As shown, in the aforementioned long flexible substrate, positioning holes are used for positioning, and transfer holes are punched on both sides of the long flexible substrate. The diameter of the transfer holes is 1.42 mm, and the spacing between the transfer holes is 4.75 mm, which can be matched with roll-to-roll equipment.

[0092] like Figure 19A and Figure 19B As shown, splicing areas are reserved at both ends of the long flexible panels. To ensure a strong connection between the long flexible panels, the width of the splicing area can be set to the width of 1 to 3 conveying holes.

[0093] like Figure 20A and Figure 20B As shown, the joint areas of two long flexible boards are spliced ​​or glued together to form a roll for easy rolling and packaging. An adhesive film with the same shape as the joint area is attached to the front or back of the joint area. The adhesive film can be made of PET (polyester film) or PI (polyimide), with a thickness of 20–100 μm, preferably a thinner 20 μm.

[0094] By using a splicing method, a sufficiently long flexible roll is obtained and packaged onto a roller for subsequent IC packaging and testing processes. This involves mounting IC chips one by one onto various substrates on the flexible roll.

[0095] In some embodiments, the flexible panels can be spliced ​​together on their back sides by a lamination process. The backsheet structure is as follows: Figure 21 As shown, the backing membrane includes conveying holes and a splicing area. The conveying holes in the long flexible sheet are aligned and bonded to the conveying holes in the backing membrane, and then sequentially spliced ​​together to form... Figure 22 The tape shown.

[0096] This disclosure also provides a display panel, including a wiring substrate according to any embodiment of this disclosure.

[0097] This disclosure also provides an electronic device, including a display panel according to any one of the embodiments of this disclosure. The electronic device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital camera, or navigator.

[0098] In this disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0099] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0100] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0101] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this disclosure. To simplify this disclosure, the components and arrangements of specific examples are described above. Of course, these are merely examples and are not intended to limit this disclosure. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0102] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this disclosure, and these should all be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A wiring substrate, characterized in that, include: Substrate; A multilayer metal wiring layer is located above a substrate. An insulating layer is provided between two adjacent metal wiring layers. Each metal wiring layer includes multiple metal bumps and metal lines connected to each of the multiple metal bumps. The multiple metal bumps are located in the chip bonding area of ​​the wiring substrate. as well as Multiple metal bonding points are located above the multilayer metal wiring layer and fall within the chip bonding area. An insulating layer is provided between the metal bonding points and the multilayer metal wiring layer. Each metal bonding point corresponds to a metal bump. Each metal bonding point is connected to its corresponding metal bump through a metal via. The insulating layer includes an organic dielectric layer and an inorganic composite layer, wherein the organic dielectric layer is disposed on the side of the inorganic composite layer away from the substrate; The metal lines in the metal wiring layer extend from the chip bonding area to the bending area of ​​the wiring substrate; for the insulating layer between two adjacent metal wiring layers, the orthographic projection of the organic dielectric layer in the insulating layer onto the substrate covers the bending area, and the orthographic projection of the inorganic composite layer in the insulating layer onto the bending area includes multiple sub-projections, and each sub-projection does not overlap with each other and covers its corresponding metal line.

2. The wiring substrate according to claim 1, characterized in that, The organic dielectric layer is made of photosensitive polyimide, and its thickness is [missing information]. , .

3. The wiring substrate according to claim 1, characterized in that, The inorganic composite layer is made of silicon nitride and has a thickness of [missing information]. , .

4. The wiring substrate according to claim 1, characterized in that, It also includes a flexible membrane located between the substrate and the multilayer metal wiring layer, and the flexible membrane has a water-insulating inorganic membrane on the side away from the substrate.

5. The wiring substrate according to claim 4, characterized in that, The flexible membrane is made of polyimide and has a thickness of [missing information]. , .

6. The wiring substrate according to claim 4, characterized in that, The water-resistant inorganic membrane is made of silicon dioxide or silicon nitride, and has a thickness of [missing information]. , .

7. The wiring substrate according to claim 1, characterized in that, The metal bumps and the metal wire are made of a metal material composed of at least one of aluminum, copper, titanium, molybdenum, and nickel, with a thickness of [missing information]. , .

8. The wiring substrate according to claim 1, characterized in that, The line width of the metal wire is , .

9. The wiring substrate according to claim 1, characterized in that, The diameter of the metal guide hole is The length is L8. , .

10. The wiring substrate according to claim 1, characterized in that, The thickness of the metal bonding point is , .

11. The wiring substrate according to claim 1, characterized in that, The metal bonding points are made of copper, and a tin layer is coated on the surface of the metal bonding points away from the substrate, the thickness of which is [missing information]. , .

12. The wiring substrate according to claim 1, characterized in that, In the bending region, the orthogonal projections of the metal lines in the multilayer metal wiring layer onto the substrate do not overlap.

13. The wiring substrate according to claim 1, characterized in that, The metal lines in the metal wiring layer extend from the chip bonding area to the bending area of ​​the wiring substrate, and from the bending area to the panel bonding area; for the metal lines that fall within the panel bonding area and are located in different metal wiring layers and are mutually aligned, their orthogonal projections on the substrate completely overlap.

14. A method for fabricating a wiring substrate, characterized in that, For preparing a wiring substrate as described in any one of claims 1 to 13, comprising: Multiple metal wiring layers are formed on a substrate, wherein an insulating layer is provided between two adjacent metal wiring layers, and each metal wiring layer includes multiple metal bumps and metal lines connected to each of the multiple metal bumps, wherein the multiple metal bumps are located in the chip bonding area of ​​the wiring substrate. Multiple metal bonding points are formed above the multilayer metal wiring layer and within the chip bonding area. An insulating layer is provided between the multiple metal bonding points and the multilayer metal wiring layer. Each metal bonding point corresponds to a metal bump. Each metal bonding point is connected to its corresponding metal bump through a metal via.

15. The method according to claim 14, characterized in that, The multilayer metal wiring layer includes an M layer, and the formation of the multilayer metal wiring layer on the substrate includes: A first metal wiring layer is formed on the substrate; Starting from N=1, perform the following operations: form the Nth insulating layer on the Nth metal wiring layer; make an opening in the Nth insulating layer for the orthogonal projection of the metal bumps in the Nth metal wiring layer to expose the metal bumps in the Nth metal wiring layer; deposit metal on the Nth insulating layer and perform pattern etching to form the (N+1)th metal wiring layer; increment N by one and return to continue the operation until N is greater than or equal to M-1 and then stop the operation; where N and M are both positive integers.

16. The method according to claim 15, characterized in that, The formation of multiple metal bonding points above the multilayer metal wiring layer and within the chip bonding region includes: The Mth insulating layer is formed on the Mth metal wiring layer; An opening is made in the Mth insulating layer to expose the metal bumps in the Mth metal wiring layer by projecting the metal bumps onto the Mth metal wiring layer. Metal is deposited on the Mth insulating layer and patterned by etching to form multiple metal bonding points.

17. The method according to claim 15, characterized in that, The Nth insulating layer comprises an Nth organic dielectric layer and an Nth inorganic composite layer. The metal lines in the metal wiring layer extend from the chip bonding region to the bending region of the wiring substrate. Forming the Nth insulating layer on the Nth metal wiring layer includes: An Nth inorganic composite layer is formed on the Nth metal wiring layer; In the bending region, the Nth inorganic composite layer is etched and the inorganic composite layer material between adjacent metal lines in the same metal wiring layer is removed to expose the N-1th organic dielectric layer, and the sidewalls of the metal lines are covered with inorganic composite layer material. An organic dielectric is deposited on the side of the wiring substrate away from the substrate to form the Nth organic dielectric layer.

18. A substrate roll, characterized in that, It includes multiple wiring substrates as described in any one of claims 1 to 13, which are connected end to end.

19. A display panel, characterized in that, Includes the wiring substrate according to any one of claims 1 to 13.

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