Semiconductor devices and their preparation methods and applications

Abstract

The embodiments of the present application relate to the field of semiconductor technology, and specifically disclose a semiconductor device, a preparation method thereof, and an application thereof. The semiconductor device comprises: a substrate; a semiconductor material layer, the semiconductor material layer being located on the substrate and covering a portion of the substrate; a gate, the gate being located on the semiconductor material layer and the substrate not covered by the semiconductor material layer; wherein, along the extension direction of the gate, the width of the semiconductor material layer is smaller than the width of the substrate, and the carrier mobility of the semiconductor material layer and the substrate is different. The present application provides a control device of at least three levels by forming a semiconductor material layer having a width smaller than the width of the substrate along the extension direction of the gate, and according to the difference in carrier mobility between the semiconductor material layer and the substrate, the control device comprises at least three states: off, half-conduction, and fully-conduction. In actual circuit applications, it is possible to switch between multiple working states according to voltage conditions to reduce GIDL current.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method and application thereof. Background Art

[0002] With the continuous development of the integrated circuit industry, silicon-based integrated circuit technology, driven by the proportional reduction of metal oxide semiconductor (MOS) devices, has entered the nanometer scale. However, further reducing the size of transistors has also affected transistor performance, such as the generation of gate-induced drain leakage (GIDL) current, which affects device performance. Summary of the Invention

[0003] In view of this, embodiments of the present application provide a semiconductor device, a manufacturing method, and an application thereof.

[0004] According to a first aspect of an embodiment of the present application, there is provided a semiconductor device, including:

[0005] substrate;

[0006] a semiconductor material layer, the semiconductor material layer being located on the substrate and covering a portion of the substrate;

[0007] a gate, the gate being located on the semiconductor material layer and the substrate not covered by the semiconductor material layer; wherein,

[0008] Along the extension direction of the gate, the width of the semiconductor material layer is smaller than the width of the substrate, and the carrier mobility of the semiconductor material layer and the material of the substrate are different.

[0009] In some embodiments, the material of the substrate includes a first element, and the material of the semiconductor material layer includes the first element and a second element different from the first element.

[0010] In some embodiments, the first element is silicon and the second element is germanium.

[0011] In some embodiments, the percentage content of the second element in the semiconductor material layer is in a range of 20%-40%.

[0012] In some embodiments, the semiconductor device includes three states. When the voltage applied to the semiconductor device is less than a first threshold, the semiconductor device is in an off state; when the voltage is greater than the first threshold and less than a second threshold, the semiconductor device is in a semi-on state; when the voltage is greater than the second threshold, the semiconductor device is in a fully-on state.

[0013] In some embodiments, further comprising:

[0014] A source electrode and a drain electrode are located on both sides of the gate electrode, penetrate the semiconductor material layer, and extend into the substrate.

[0015] According to a second aspect of an embodiment of the present application, a method for manufacturing a semiconductor device is provided, comprising:

[0016] providing a substrate;

[0017] forming a semiconductor material layer on the substrate, wherein the semiconductor material layer covers a portion of the substrate;

[0018] A gate is formed on the semiconductor material layer and the substrate not covered by the semiconductor material layer; wherein,

[0019] Along the extension direction of the gate, the width of the semiconductor material layer is smaller than the width of the substrate, and the carrier mobility of the semiconductor material layer and the material of the substrate are different.

[0020] In some embodiments, the material of the substrate includes a first element, and the material of the semiconductor material layer includes the first element and a second element different from the first element.

[0021] In some embodiments, the first element is silicon and the second element is germanium.

[0022] In some embodiments, the percentage content of the second element in the semiconductor material layer is in a range of 20%-40%.

[0023] In some embodiments, an in-situ doping epitaxial process is used to form a semiconductor material layer, and the growth rate of the semiconductor material layer in the middle and edge regions of the substrate is adjusted by controlling the flow rate of the growth gas so that the semiconductor material layer covers a portion of the substrate.

[0024] In some embodiments, a photoresist layer is formed on a mask layer covering the substrate;

[0025] exposing and developing the photoresist layer to transfer the preset pattern of the semiconductor material layer on the mask to the photoresist layer;

[0026] removing a portion of the mask layer that is opposite to the preset pattern of the semiconductor material layer, so as to expose a portion of the substrate;

[0027] A semiconductor material layer is formed on the exposed substrate.

[0028] In some embodiments, further comprising:

[0029] Ion doping is performed on the semiconductor material layer on both sides of the gate and the substrate located under the semiconductor material layer to form a source electrode and a drain electrode that penetrate the semiconductor material layer and extend into the substrate.

[0030] According to a third aspect of an embodiment of the present application, there is provided an application of a semiconductor device in a circuit, the circuit comprising:

[0031] A main word line, a sub-word line, a word line driving circuit and a voltage control module, wherein the voltage control module includes a semiconductor device as described in any one of the above embodiments, wherein:

[0032] The semiconductor device includes a source terminal, a drain terminal and a gate terminal; the source terminal is connected to a high level signal, the drain terminal is connected to a main word line, and the gate terminal is connected to a standby signal;

[0033] The word line driving circuit is connected between the main word line and the sub word line;

[0034] The voltage control module is configured to reduce a voltage output to the word line driving circuit when a standby state occurs.

[0035] In some embodiments, the word line driving circuit includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor; wherein the first PMOS transistor is connected to the gate of the first NMOS transistor and is connected to the main word line; the source of the first NMOS transistor is connected to the source of the second NMOS transistor and is grounded; the drain of the first PMOS transistor, the drain of the first NMOS transistor, and the drain of the second NMOS transistor are connected and connected to the sub-word line.

[0036] According to a fourth aspect of the embodiments of the present application, a circuit driving method is provided, the circuit driving method being applied to the circuit described in any one of the embodiments of the third aspect of the present application; the method comprising:

[0037] When the standby state does not occur, the semiconductor device is controlled to be in the off state;

[0038] When the standby state occurs, the semiconductor device is controlled to be in a semi-conducting state to increase the equivalent resistance of the semiconductor device and reduce the voltage output to the word line driving circuit.

[0039] In embodiments of the present application, by forming a semiconductor material layer with a width smaller than that of the substrate along the gate's extension direction and utilizing the difference in carrier mobility between the semiconductor material layer and the substrate, a control device with at least three levels is provided. This control device includes at least three states: off, half-on, and fully on. In actual circuit applications, this control device can switch between multiple operating states based on voltage conditions, thereby reducing GIDL current. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A top view of a semiconductor device provided in an embodiment of the present application;

[0041] Figure 2 For the Figure 1 A cross-sectional view along the dotted line A-A';

[0042] Figure 3 For the Figure 1 A cross-sectional view along the dotted line BB';

[0043] Figure 4 is a graph showing the relationship between gate voltage and drain current;

[0044] Figure 5 A schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0045] Figures 6a to 6g A schematic diagram of the structure of a semiconductor device during the manufacturing process provided in an embodiment of the present application;

[0046] Figure 7 A circuit diagram of a circuit provided in an embodiment of the present application.

[0047] Description of reference numerals:

[0048] 10-substrate;

[0049] 20-semiconductor material layer;

[0050] 30-gate;

[0051] 41-source; 42-drain;

[0052] 50-mask layer;

[0053] 60-photoresist layer;

[0054] 71-word line driving circuit; 711-first PMOS transistor; 712-first NMOS transistor; 713-second NMOS transistor;

[0055] 72- voltage control module; 721- semiconductor device. DETAILED DESCRIPTION

[0056] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0057] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0058] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0059] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. And when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present application.

[0060] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0061] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0062] In order to fully understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0063] An embodiment of the present application provides a semiconductor device. Figure 1 A top view of a semiconductor device provided in an embodiment of the present application, Figure 2 For the Figure 1 The cross-sectional view along the dotted line A-A' is shown in the figure. Figure 3 For the Figure 1 Cross-sectional view along the dotted line BB'.

[0064] See also Figures 1 to 3 , the semiconductor device comprising:

[0065] A substrate 10; a semiconductor material layer 20, wherein the semiconductor material layer 20 is located on the substrate 10 and covers a portion of the substrate 10; a gate 30, wherein the gate 30 is located on the semiconductor material layer 20 and on the portion of the substrate 10 not covered by the semiconductor material layer 20; wherein, along the extension direction of the gate 30, the width of the semiconductor material layer 20 is smaller than the width of the substrate 10, and the carrier mobility of the materials of the semiconductor material layer 20 and the substrate 10 is different.

[0066] In embodiments of the present application, by forming a semiconductor material layer with a width smaller than that of the substrate along the gate's extension direction and utilizing the difference in carrier mobility between the semiconductor material layer and the substrate, a control device with at least three levels is provided. This control device includes at least three states: off, half-on, and fully on. In actual circuit applications, this control device can switch between multiple operating states based on voltage conditions, thereby reducing GIDL current.

[0067] The substrate 10 may be a single semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. In the embodiment of the present application, the substrate 10 is a silicon substrate.

[0068] In one embodiment, the carrier mobility of the semiconductor material layer 20 is greater than the carrier mobility of the substrate 10 material, thereby increasing the carrier mobility of the channel region, optimizing the operating speed of the semiconductor device, and improving the electrical performance of the semiconductor device.

[0069] The gate structure 30 may include an oxide layer, a first gate conductive layer, and a second gate conductive layer stacked in sequence (not shown in the figure).

[0070] In one embodiment, if Figure 1 As shown, along the direction perpendicular to the gate 30, the width of the semiconductor material layer 20 is less than the width of the substrate 10. In other embodiments, along the direction perpendicular to the gate 30, the width of the semiconductor material layer 20 may also be equal to the width of the substrate 10.

[0071] In one embodiment, the material of the substrate 10 includes a first element, and the material of the semiconductor material layer 20 includes the first element and a second element different from the first element. Thus, the difference between the materials of the substrate and the semiconductor material layer can affect carrier mobility, thereby causing different threshold voltages of channel regions formed in the semiconductor material layer and the substrate, respectively.

[0072] In one embodiment, the first element is silicon, and the second element is germanium. Specifically, the substrate 10 is a silicon substrate, and the semiconductor material layer 20 is a silicon-germanium layer. The lattice difference between germanium and silicon can affect carrier mobility, thereby adjusting the channel region threshold voltage. In other embodiments, the first and second elements can also be selected from other elements that can affect carrier mobility, including, but not limited to, silicon, germanium, boron, tellurium, iodine, carbon, phosphorus, arsenic, and sulfur.

[0073] In some other embodiments, the substrate 10 is a silicon substrate, and the semiconductor material layer 20 is a carbon-containing silicon germanium layer.

[0074] In one embodiment, the percentage content of the second element in the semiconductor material layer 20 is in the range of 20%-40%. Within this range, the semiconductor material layer can better affect the carrier mobility and adjust the threshold voltage of the channel region, so that the formed three-stage control device can better reduce the GIDL current.

[0075] In one embodiment, the semiconductor material layer 20 includes a first semiconductor material layer and a second semiconductor material layer (not shown). The first semiconductor material layer and the second semiconductor material layer are arranged side by side, and both extend in a direction from the source to the drain. The mobility of the material of the first semiconductor material layer, the mobility of the material of the second semiconductor material layer, and the mobility of the material of the substrate are different. In this way, based on the difference in carrier mobility between the first semiconductor material layer, the second semiconductor material layer, and the substrate, the semiconductor device can be formed into a multi-level device.

[0076] In one embodiment, if Figure 3 As shown, along the direction in which the gate 30 extends, the length of the gate 30 is greater than the length of the substrate 10. That is, the gate 30 is also located on other structures, so the length of the gate 30 is greater than the length of the substrate 10. This can improve the control capability of the channel region, improve device leakage problems, and multiple device structures can share the same gate.

[0077] In one embodiment, the semiconductor device 20 includes three states. When the voltage applied to the semiconductor device 20 is less than a first threshold, the semiconductor device 20 is in an off state; when the voltage is greater than the first threshold and less than a second threshold, the semiconductor device 20 is in a semi-on state; when the voltage is greater than the second threshold, the semiconductor device 20 is in a fully on state.

[0078] Specifically, if Figure 1As shown, since the width of the semiconductor material layer 20 in the direction extending along the gate 30 is smaller than the width of the substrate 10, the channel region of the semiconductor device is divided into two parts, one part is the middle region covered by the semiconductor material layer 20, and the other part is the edge region not covered by the semiconductor material layer 20. Since the semiconductor material layer 20 is only partially grown on the substrate 10, the threshold voltage of the channel region in the middle region covered by the semiconductor material layer 20 is low, and the middle region will be turned on early. When the voltage reaches the threshold voltage of the edge region, the channel in the edge region will be turned on. The final voltage and current curve is shown as follows: Figure 4 shown.

[0079] See also Figure 4 In stage 0, the voltage of the semiconductor device is less than the first threshold value, and the middle area and the edge area have not reached the on state, so the semiconductor device is in the off state; in stage 1, the voltage of the semiconductor device is greater than the first threshold value and less than the second threshold value, the middle area reaches the on state, and the edge area is still in the off state, so the semiconductor device is in a semi-conducting state, and the redundancy of the gate voltage is high, and the drain current will not change due to slight fluctuations in the gate voltage; in stage 2, the voltage of the semiconductor device is greater than the second threshold value, and the middle area and the edge area both reach the on state, so the semiconductor device is in a fully conductive state and works in the saturation region. The three states of the semiconductor device are as follows: Figure 4 Thus, the semiconductor device provided in the embodiment of the present application is a three-stage control device.

[0080] In one embodiment, if Figure 2 As shown, the semiconductor device further includes a source 41 and a drain 42 . The source 41 and the drain 42 are located on both sides of the gate 30 , penetrate the semiconductor material layer 20 , and extend into the substrate 10 .

[0081] The present invention also provides a method for preparing a semiconductor device. Figure 5 , as shown in the figure, the method includes the following steps:

[0082] Step 501: providing a substrate;

[0083] Step 502: forming a semiconductor material layer on the substrate, wherein the semiconductor material layer covers a portion of the substrate;

[0084] Step 503: forming a gate on the semiconductor material layer and the substrate not covered by the semiconductor material layer; wherein, along the extension direction of the gate, the width of the semiconductor material layer is smaller than the width of the substrate, and the carrier mobility of the semiconductor material layer and the material of the substrate are different.

[0085] The following is a further detailed description of the method for preparing the semiconductor device provided in the embodiments of the present application in conjunction with specific embodiments.

[0086] Figures 6a to 6g A schematic diagram of the structure of a semiconductor device during the preparation process provided in an embodiment of the present application.

[0087] It should be noted that Figures 6a to 6e For the Figure 1 The cross-sectional view along the dotted line BB' is shown in the figure. Figures 6f to 6g For the Figure 1 Cross-sectional view along the dotted line AA'.

[0088] First, see Figure 6a , perform step 501 to provide a substrate 10. The substrate 10 can be a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (e.g., a silicon-germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. In the embodiment of the present application, the substrate 10 is a silicon substrate.

[0089] Next, see Figures 6b to 6d , execute step 502 . Form a semiconductor material layer 20 on the substrate 10 , wherein the semiconductor material layer 20 covers a portion of the substrate 10 .

[0090] In practice, see Figure 6b , a mask layer 50 may be formed on the substrate 10 first, and then a photoresist layer 60 may be formed on the mask layer 50 covering the substrate 10 .

[0091] In one embodiment, the mask layer 50 may be a composite material layer of silicon dioxide and silicon nitride.

[0092] Next, the photoresist layer 60 is exposed and developed to transfer the predetermined pattern of the semiconductor material layer on the mask (not shown) to the photoresist layer 60 to form a patterned photoresist layer.

[0093] See also Figure 6c Based on the patterned photoresist layer, the portion of the mask layer 50 corresponding to the predetermined pattern of the semiconductor material layer is etched away to expose a portion of the substrate 10. In one embodiment, the mask layer and the photoresist layer located in the middle region of the substrate 10 are removed to expose the middle region of the substrate 10.

[0094] Optionally, the photoresist layer 60 is a positive photoresist or a negative photoresist. The positive photoresist can form a soluble substance after being exposed to light, while the negative photoresist can form an insoluble substance after being exposed to light.

[0095] See also Figure 6d , a semiconductor material layer 20 is formed on the exposed substrate 10. After the semiconductor material layer 20 is formed, the remaining photoresist layer 60 and the mask layer 50 are removed.

[0096] In the embodiment of the present application, it is not necessary to add a new mask, but to modify the mask in the previous process, such as the PMOS mask, to form the mask for forming the semiconductor material layer. In this way, the process steps can be reduced and the cost can be saved.

[0097] exist Figures 6b to 6d In the illustrated embodiment, the semiconductor material layer 20 is formed by forming a photoresist layer. In other embodiments, the semiconductor material layer 20 may also be formed by an in-situ doping epitaxial process.

[0098] The semiconductor material layer 20 is formed by an in-situ doping epitaxial process. By controlling the flow rate of the growth gas, the growth rate of the semiconductor material layer 20 in the middle area and edge area of ​​the substrate 10 is adjusted so that the semiconductor material layer 20 covers a portion of the substrate 10.

[0099] Specifically, the growth gas includes HCl, SiH4, and GeH4. By adjusting the flow ratio of HCl, SiH4, and GeH4, different percentages of germanium atoms can be obtained, and the germanium atoms are evenly distributed, the process steps are simple, and the formed semiconductor material layer has good uniformity.

[0100] In one embodiment, the material of the substrate 10 includes a first element, and the material of the semiconductor material layer 20 includes the first element and a second element different from the first element. Thus, the difference between the materials of the substrate 10 and the semiconductor material layer 20 can affect carrier mobility, thereby causing a difference in threshold voltage of the channel region in the semiconductor material layer 20 and the substrate 10.

[0101] In one embodiment, the first element is silicon, and the second element is germanium. Specifically, the substrate 10 is a silicon substrate, and the semiconductor material layer 20 is a silicon-germanium layer. The lattice difference between germanium and silicon can affect carrier mobility, thereby adjusting the channel region threshold voltage. In other embodiments, the first and second elements can also be selected from other elements that can affect carrier mobility, including, but not limited to, silicon, germanium, boron, tellurium, iodine, carbon, phosphorus, arsenic, and sulfur.

[0102] In some other embodiments, the substrate 10 is a silicon substrate, and the semiconductor material layer 20 is a carbon-containing silicon germanium layer.

[0103] In one embodiment, the percentage content of the second element in the semiconductor material layer is in the range of 20%-40%. Within this range, the semiconductor material layer can better affect carrier mobility and adjust the threshold voltage of the channel region, thereby enabling the formed three-stage control device to better reduce GIDL current.

[0104] Next, see Figure 6e and Figure 6f , it should be noted that, Figure 6e For the Figure 1 The cross-sectional view along the dotted line BB' is shown in the figure. Figure 6f For the Figure 1 Cross-sectional view along the dashed line A-A'. Step 503 is performed to form a gate 30 on the semiconductor material layer 20 and the portion of the substrate 10 not covered by the semiconductor material layer 20. The width of the semiconductor material layer 20 along the extension direction of the gate 30 is smaller than the width of the substrate 10, and the semiconductor material layer 20 and the substrate 10 have different carrier mobilities.

[0105] In one embodiment, the carrier mobility of the semiconductor material layer 20 is greater than the carrier mobility of the substrate 10 material, thereby increasing the carrier mobility of the channel region, optimizing the operating speed of the semiconductor device, and improving the electrical performance of the semiconductor device.

[0106] In actual operation, the formation of the gate 30 specifically includes: first forming a mask layer (not shown in the figure) on the semiconductor material layer 20 and the substrate 10 not covered by the semiconductor material layer 20, and then patterning the mask layer to display the gate trench pattern to be etched on the mask layer, and the mask layer can be patterned by a photolithography process. The mask layer can be a photoresist mask or a hard mask patterned based on a photolithography mask; when the mask layer is a photoresist mask, the mask layer is patterned specifically through steps such as exposure, development, and stripping. Then, a gate trench with a certain depth is etched according to the gate trench pattern to be etched. Then, a gate is formed in the gate trench, and the excess mask layer is removed.

[0107] The gate structure 30 may include an oxide layer, a first gate conductive layer, and a second gate conductive layer stacked in sequence (not shown in the figure).

[0108] In one embodiment, the semiconductor device 20 includes three states. When the voltage applied to the semiconductor device 20 is less than a first threshold, the semiconductor device 20 is in an off state; when the voltage is greater than the first threshold and less than a second threshold, the semiconductor device 20 is in a semi-on state; when the voltage is greater than the second threshold, the semiconductor device 20 is in a fully on state.

[0109] Specifically, if Figure 1 As shown, since the width of the semiconductor material layer 20 in the direction extending along the gate 30 is smaller than the width of the substrate 10, the channel region of the semiconductor device is divided into two parts, one part is the middle region covered by the semiconductor material layer 20, and the other part is the edge region not covered by the semiconductor material layer 20. Since the semiconductor material layer 20 is only partially grown on the substrate 10, the threshold voltage of the channel region in the middle region covered by the semiconductor material layer 20 is low, and the middle region will be turned on early. When the voltage reaches the threshold voltage of the edge region, the channel in the edge region will be turned on. The final voltage and current curve is shown as follows: Figure 4 shown.

[0110] See also Figure 4 In stage 0, the voltage of the semiconductor device is less than the first threshold value, and the middle area and the edge area have not reached the on state, so the semiconductor device is in the off state; in stage 1, the voltage of the semiconductor device is greater than the first threshold value and less than the second threshold value, the middle area reaches the on state, and the edge area is still in the off state, so the semiconductor device is in a semi-conducting state, and the redundancy of the gate voltage is high, and the drain current will not change due to slight fluctuations in the gate voltage; in stage 2, the voltage of the semiconductor device is greater than the second threshold value, and the middle area and the edge area both reach the on state, so the semiconductor device is in a fully conductive state and works in the saturation region. The three states of the semiconductor device are as follows: Figure 4 Thus, the semiconductor device provided in the embodiment of the present application is a three-stage control device.

[0111] In one embodiment, if Figure 6e As shown, along the direction in which the gate 30 extends, the length of the gate 30 is greater than the length of the substrate 10. That is, the gate 30 is also located on other structures, so the length of the gate 30 is greater than the length of the substrate 10. This can improve the controllability of the channel region, improve device leakage issues, and multiple device structures can share the same gate.

[0112] Next, see Figure 6g The semiconductor material layer 20 on both sides of the gate 30 and the substrate 10 located under the semiconductor material layer 20 are ion-doped to form a source 41 and a drain 42 that penetrate the semiconductor material layer 20 and extend into the substrate 10.

[0113] Specifically, in one embodiment, a lightly doped drain region injection process (LDD), a source / drain region (S / D) ion injection, and an annealing process can be performed in sequence to form a source 41 and a drain 42 on both sides of the gate 30; the specific process parameters can be set according to actual process requirements, and this application is not limited to this.

[0114] In one embodiment, the semiconductor material layer 20 includes a first semiconductor material layer and a second semiconductor material layer (not shown). The first semiconductor material layer and the second semiconductor material layer are arranged side by side, and both extend in a direction from the source to the drain. The mobility of the material of the first semiconductor material layer, the mobility of the material of the second semiconductor material layer, and the mobility of the material of the substrate are different. In this way, based on the difference in carrier mobility between the first semiconductor material layer, the second semiconductor material layer, and the substrate, the semiconductor device can be formed into a multi-level device.

[0115] The embodiment of the present application further provides a circuit in which the above-mentioned semiconductor device is applied, such as Figure 7 As shown, the circuit includes:

[0116] A main word line MWL (Main word line), a sub-word line WL (Word line), a word line driving circuit 71 and a voltage control module 72, wherein the voltage control module 72 includes a semiconductor device 721 as described in any one of the above embodiments, wherein:

[0117] The semiconductor device 721 includes a source terminal, a drain terminal and a gate terminal; the source terminal is connected to the high level signal VPP, the drain terminal is connected to the main word line MWL, and the gate terminal is connected to the standby signal STBY;

[0118] The word line driving circuit 71 is connected between the main word line MWL and the sub word line WL;

[0119] The voltage control module 72 is configured to reduce the voltage output to the word line driving circuit 71 when the standby state occurs.

[0120] In a conventional circuit, the main word line MWL is at a high level and the sub-word line WL is at a low level. A voltage difference exists between the gate and the source or drain of the first PMOS transistor 711, which causes the first PMOS transistor 711 to be affected by the GIDL current. Therefore, in the embodiment of the present application, a voltage control module 72 is added to the main word line MWL. In this way, in the standby state, the semiconductor device can be controlled to be as follows: Figure 4 The stage 1 state shown, ie, the semi-conducting state, increases the equivalent resistance of the semiconductor device, thereby reducing the voltage output to the word line driving circuit 71 and reducing the GIDL current.

[0121] The semiconductor device 721 is a PMOS transistor.

[0122] In one embodiment, the word line driving circuit 71 includes a first PMOS transistor 711, a first NMOS transistor 712, and a second NMOS transistor 713; wherein the first PMOS transistor 711 is connected to the gate of the first NMOS transistor 712 and is connected to the main word line MWL; the source of the first NMOS transistor 712 is connected to the source of the second NMOS transistor 713 and is grounded; the drain of the first PMOS transistor 711, the drain of the first NMOS transistor 712, and the drain of the second NMOS transistor 713 are connected and are connected to the sub-word line WL.

[0123] In one embodiment, the first PMOS transistor 711 and the first NMOS transistor 712 form an inverter circuit having an input terminal connected to the main word line MWL and an output terminal connected to the sub-word line WL. The source of the first PMOS transistor 711 can be connected to the sub-word line drive signal PXID. The second NMOS transistor 713 is coupled between the output terminal of the inverter circuit and the ground terminal VSS. The gate of the second NMOS transistor 713 is connected to the inverted sub-word line drive signal PXIB and responds to the inverted sub-word line drive signal PXIB.

[0124] An embodiment of the present application further provides a circuit driving method, which is applied to the circuit described in any one of the above embodiments; the method includes:

[0125] When the standby state does not occur, the semiconductor device is controlled to be in the off state;

[0126] When the standby state occurs, the semiconductor device is controlled to be in a semi-conducting state to increase the equivalent resistance of the semiconductor device and reduce the voltage output to the word line driving circuit.

[0127] The above is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A semiconductor device, characterized in that: include: substrate; a semiconductor material layer, the semiconductor material layer being located on the substrate and covering a portion of the substrate; a gate, the gate being located on the semiconductor material layer and the substrate not covered by the semiconductor material layer; wherein, Along the extension direction of the gate, the width of the semiconductor material layer is smaller than the width of the substrate, and the carrier mobility of the semiconductor material layer and the material of the substrate is different; The semiconductor device includes three states. When the voltage applied to the semiconductor device is less than a first threshold, the semiconductor device is in an off state; when the voltage is greater than the first threshold and less than a second threshold, the semiconductor device is in a semi-on state; when the voltage is greater than the second threshold, the semiconductor device is in a fully on state.

2. The semiconductor device according to claim 1, wherein The material of the substrate includes a first element, and the material of the semiconductor material layer includes the first element and a second element different from the first element.

3. The semiconductor device according to claim 2, wherein The first element is silicon, and the second element is germanium.

4. The semiconductor device according to claim 2, wherein The percentage content of the second element in the semiconductor material layer is in the range of 20%-40%.

5. The semiconductor device according to claim 1, wherein Also includes: A source electrode and a drain electrode are located on both sides of the gate electrode, penetrate the semiconductor material layer, and extend into the substrate.

6. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; forming a semiconductor material layer on the substrate, wherein the semiconductor material layer covers a portion of the substrate; A gate is formed on the semiconductor material layer and the substrate not covered by the semiconductor material layer; wherein, Along the extension direction of the gate, the width of the semiconductor material layer is smaller than the width of the substrate, and the carrier mobility of the semiconductor material layer and the material of the substrate is different; The semiconductor device includes three states. When the voltage applied to the semiconductor device is less than a first threshold, the semiconductor device is in an off state; when the voltage is greater than the first threshold and less than a second threshold, the semiconductor device is in a semi-on state; when the voltage is greater than the second threshold, the semiconductor device is in a fully on state.

7. The method according to claim 6, characterized in that The material of the substrate includes a first element, and the material of the semiconductor material layer includes the first element and a second element different from the first element.

8. The method according to claim 7, characterized in that The first element is silicon, and the second element is germanium.

9. The method according to claim 7, characterized in that The percentage content of the second element in the semiconductor material layer is in the range of 20%-40%.

10. The method according to claim 6, characterized in that The semiconductor material layer is formed by adopting an in-situ doping epitaxial process. By controlling the flow rate of the growth gas, the growth rate of the semiconductor material layer in the middle area and the edge area of ​​the substrate is adjusted so that the semiconductor material layer covers part of the substrate.

11. The method according to claim 6, characterized in that forming a photoresist layer on the mask layer covering the substrate; exposing and developing the photoresist layer to transfer the preset pattern of the semiconductor material layer on the mask to the photoresist layer; removing a portion of the mask layer that is opposite to the preset pattern of the semiconductor material layer, so as to expose a portion of the substrate; A semiconductor material layer is formed on the exposed substrate.

12. The method according to claim 6, characterized in that Also includes: Ion doping is performed on the semiconductor material layer on both sides of the gate and the substrate located under the semiconductor material layer to form a source electrode and a drain electrode that penetrate the semiconductor material layer and extend into the substrate.

13. A circuit, characterized in that: The circuit comprises: A main word line, a sub-word line, a word line driving circuit and a voltage control module, wherein the voltage control module comprises a semiconductor device according to any one of claims 1 to 5, wherein: The semiconductor device includes a source terminal, a drain terminal and a gate terminal; the source terminal is connected to a high level signal, the drain terminal is connected to a main word line, and the gate terminal is connected to a standby signal; The word line driving circuit is connected between the main word line and the sub word line; The voltage control module is configured to reduce a voltage output to the word line driving circuit when a standby state occurs.

14. The circuit according to claim 13, characterized in that The word line driving circuit includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor; wherein the first PMOS transistor is connected to the gate of the first NMOS transistor and is connected to the main word line; the source of the first NMOS transistor is connected to the source of the second NMOS transistor and is grounded; the drain of the first PMOS transistor, the drain of the first NMOS transistor, and the drain of the second NMOS transistor are connected and are connected to the sub-word line.

15. A circuit driving method, characterized in that: The driving method of the circuit is applied to the circuit according to any one of claims 13 to 14; the method comprises: When the standby state does not occur, the semiconductor device is controlled to be in the off state; When the standby state occurs, the semiconductor device is controlled to be in a semi-conducting state to increase the equivalent resistance of the semiconductor device and reduce the voltage output to the word line driving circuit.

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