A ring voltage controlled oscillator and multimode receiver

Abstract

The application discloses a ring type voltage-controlled oscillator and a multi-mode receiver, the ring type voltage-controlled oscillator comprising three double-path structure delay units connected in sequence, adopting a new structure of double common-source stages plus NMOS tube source following feedback, so that output noise voltage or current can be offset, and phase noise is reduced; meanwhile, the ring type voltage-controlled oscillator adds a varactor pair and a capacitor switch array at an output end, frequency tuning of the circuit can be realized by introducing the varactor and a tuning voltage, and the tuning range of the ring type voltage-controlled oscillator can be further increased through the capacitor switch array; and the ring type voltage-controlled oscillator further adds a biased I-MOS varactor pair in parallel on the basis of the A-MOS varactor pair, so that the poor capacitance characteristic of the A-MOS varactor can be compensated by the I-MOS varactor, and the tuning linearity of the ring type voltage-controlled oscillator can be optimized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor integrated circuits, and in particular to a ring voltage-controlled oscillator and a multi-mode receiver. BACKGROUND

[0002] The core problem in the application of ubiquitous network, which is an advanced stage of Internet of Things, is to realize terminal reconfiguration. Multi-mode receiver is an important part of reconfigurable system, and in the multi-mode receiver of software defined radio, the design of Ring-VCO (Ring Voltage-Controlled Oscillator) is crucial.

[0003] In recent years, due to the large chip area occupied by inductance in inductance-capacitance voltage-controlled oscillator, which hinders the further improvement of chip integration, Ring-VCO, as the best alternative solution, has attracted the attention of many researchers, and the research on phase-locked loop based on Ring-VCO is also increasing. The application of Ring-VCO in multi-mode receiver mainly includes the formation of local oscillator in radio frequency frequency synthesizer and the generation of low frequency sampling clock. Ring-VCO has the advantages of small area, wide tuning range, not sensitive to magnetic coupling, easy integration, etc. compared with inductance-capacitance voltage-controlled oscillator, and has great development prospect in practical application. However, Ring-VCO has strong switching nonlinearity, and the phase noise performance is poor, which becomes the core factor restricting its application. SUMMARY

[0004] The present application aims to at least solve one of the technical problems in the related art. To this end, the first object of the present application is to provide a ring voltage-controlled oscillator which can improve the output phase noise and tuning linearity while realizing low power consumption.

[0005] The second object of the present application is to provide a multi-mode receiver.

[0006] In order to achieve the above-mentioned object, the present application realizes the following technical scheme:

[0007] A ring voltage-controlled oscillator comprises:

[0008] three double-path structure delay units connected in sequence, wherein the first differential output end and the second differential output end of the first double-path structure delay unit are connected with the first differential input end and the second differential input end of the second double-path structure delay unit respectively; the first differential output end and the second differential output end of the second double-path structure delay unit are connected with the first differential input end and the second differential input end of the third double-path structure delay unit respectively; the first differential output end and the second differential output end of the third double-path structure delay unit are connected with the second differential input end and the first differential input end of the first double-path structure delay unit respectively.

[0009] Optionally, each double-path structure delay unit comprises:

[0010] the gate of the first MOS transistor and the source of the fifth MOS transistor are connected with the corresponding first differential input end, the drain of the first MOS transistor is connected with the drain of the third MOS transistor, the gate of the third MOS transistor, the gate of the fourth MOS transistor and the gate of the fifth MOS transistor, the source of the third MOS transistor, the source of the fourth MOS transistor and the drain of the fifth MOS transistor are connected with the first power supply, the drain of the fourth MOS transistor and the drain of the second MOS transistor are connected with the corresponding first differential output end, the source of the first MOS transistor and the source of the second MOS transistor are grounded, the gate of the second MOS transistor is connected with the corresponding second differential input end;

[0011] the gate of the sixth MOS transistor and the source of the tenth MOS transistor are connected with the corresponding second differential input end, the drain of the sixth MOS transistor is connected with the drain of the eighth MOS transistor, the gate of the eighth MOS transistor, the gate of the ninth MOS transistor and the gate of the tenth MOS transistor, the source of the eighth MOS transistor, the source of the ninth MOS transistor and the drain of the tenth MOS transistor are connected with the first power supply, the drain of the ninth MOS transistor and the drain of the seventh MOS transistor are connected with the corresponding second differential output end, the source of the sixth MOS transistor and the source of the seventh MOS transistor are grounded, the gate of the seventh MOS transistor is connected with the corresponding first differential input end.

[0012] Optionally, each double-path structure delay unit further comprises:

[0013] a pair of A-MOS varactors connected in parallel between the corresponding first differential output end and the second differential output end.

[0014] Optionally, the pair of A-MOS varactors comprises:

[0015] a first adjustable capacitor and a second adjustable capacitor, which are connected in series and then connected in parallel between the corresponding first differential output end and second differential output end, wherein one end of the first adjustable capacitor and the second adjustable capacitor is further connected to a second power supply.

[0016] Optionally, each of the double-path structure delay units further comprises:

[0017] a capacitor switch array circuit connected in parallel between the corresponding first differential output end and second differential output end.

[0018] Optionally, the capacitor switch array circuit comprises:

[0019] a first capacitor and a second capacitor.

[0020] eleventh to thirteenth MOS transistors, a gate of the eleventh MOS transistor is connected to drains of a twelfth and thirteenth MOS transistors, a drain of the eleventh MOS transistor is connected to the corresponding first differential output end through the first capacitor, a source of the eleventh MOS transistor is connected to the corresponding second differential output end through the second capacitor, a source of the twelfth MOS transistor is connected to the first power supply, a source of the thirteenth MOS transistor is grounded, and gates of the twelfth and thirteenth MOS transistors are connected to a third power supply.

[0021] a first resistor and a second resistor, one end of the first resistor is connected to the drain of the eleventh MOS transistor, one end of the second resistor is connected to the source of the eleventh MOS transistor, and the other ends of the first and second resistors are connected to the third power supply.

[0022] Optionally, each of the double-path structure delay units further comprises:

[0023] an I-MOS varactor pair circuit connected in parallel between the corresponding first differential output end and second differential output end.

[0024] Optionally, the I-MOS varactor pair circuit comprises:

[0025] a third capacitor and a fourth capacitor.

[0026] fourteenth to sixteenth MOS transistors, a gate of the fourteenth MOS transistor is connected to the corresponding first differential output end through the third capacitor, a gate of the fifteenth MOS transistor is connected to the corresponding second differential output end through the fourth capacitor, and sources and drains of the fourteenth MOS transistor and sources and drains of the fifteenth MOS transistor are connected to the second power supply.

[0027] The third resistor and the fourth resistor have one end connected with the gate of the fourteenth MOS and the fifteenth MOS respectively, the other end of the third resistor and the fourth resistor, and one end of the fifth resistor and the sixth resistor are connected with the gate of the sixteenth MOS, the other end of the fifth resistor, the source and the drain of the sixteenth MOS are grounded, and the other end of the sixth resistor is connected with the first power supply.

[0028] Optionally, the first MOS, the second MOS, the fifth MOS, the sixth MOS, the seventh MOS, the tenth MOS, the eleventh MOS, the thirteenth MOS, and the fourteenth MOS to the sixteenth MOS are all NMOS, and the third MOS, the fourth MOS, the eighth MOS, the ninth MOS, and the twelfth MOS are all PMOS.

[0029] To achieve the above object, the second aspect of the present application provides a multi-mode receiver.

[0030] The present application has at least the following technical effects:

[0031] The present application proposes a three-stage Ring-VCO circuit structure with low power consumption and low phase noise aiming at the problem that power consumption and phase noise are mutually restricted in the existing widely used Ring-VCO, and specifically adopts a new structure of double common source stage plus NMOS source following feedback, so that the output noise voltage or current is offset, and then the phase noise is reduced. Meanwhile, the present application adds a varactor pair and a capacitor switch array at the output end, and through the introduction of varactor and tuning voltage, the frequency tuning of the circuit can be realized, and through the capacitor switch array, the tuning range of the Ring-VCO can be further increased. In addition, in order to realize small VCO gain change, the present application adds a biased I-MOS varactor pair in parallel on the basis of the traditional A-MOS varactor pair, so that the poor capacitance characteristics of the A-MOS varactor pair are compensated by the I-MOS varactor pair, thereby the tuning linearity of the VCO can be optimized.

[0032] Additional aspects and advantages of the present application will be made apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 The structure schematic diagram of the symmetric load structure delay unit provided by the prior art.

[0034] Figure 2 The structure schematic diagram of the pseudo-differential structure delay unit provided by the prior art.

[0035] Figure 3 This is a schematic diagram of a ring-shaped voltage-controlled oscillator provided in an embodiment of the present invention.

[0036] Figure 4 This is a schematic diagram of the structure of a dual-path delay unit provided in an embodiment of the present invention.

[0037] Figure 5 This is a schematic diagram of a capacitor switch array circuit structure provided in an embodiment of the present invention.

[0038] Figure 6 This is a schematic diagram of an I-MOS varactor pair circuit structure provided in an embodiment of the present invention.

[0039] Figure 7 This is a structural block diagram of a multimode receiver provided in an embodiment of the present invention. Detailed Implementation

[0040] The following describes this embodiment in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the invention, and should not be construed as limiting the invention.

[0041] In recent years, the large chip area occupied by inductors in inductor-capacitor voltage-controlled oscillators (VCOs) has hindered further improvements in chip integration. Ring-VCOs, as the optimal alternative, have attracted considerable attention from researchers, leading to a surge in research on Ring-VCO-based phase-locked loops (PLLs). The main applications of Ring-VCOs in multimode receivers include the formation of the local oscillator in RF frequency synthesizers and the generation of low-frequency sampling clocks. Compared to inductor-capacitor VCOs, Ring-VCOs offer advantages such as smaller area, wider tuning range, insensitivity to magnetic coupling, and ease of integration, making them highly promising for practical applications. However, the strong switching nonlinearity and poor phase noise performance of Ring-VCOs are key factors limiting their application.

[0042] Currently, the existing technology provides a Ring-VCO composed of delay units with a symmetrical load structure. For example... Figure 1 As shown, this delay unit consists of two sets of symmetrical PMOS load transistors, an NMOS differential input pair, and an NMOS tail current source. The tuning voltage Vc controls the oscillation frequency of the Ring-VCO by adjusting the load size. This symmetrical load structure can reduce phase noise by decreasing flicker noise. However, the degree to which this symmetrical load structure reduces phase noise is limited, the voltage swing of the output signal is small, and the power consumption of the circuit is relatively high.

[0043] The Ring-VCO provided by the prior art is a Ring-VCO designed by using a traditional pseudo-differential structure. Figure 2 As shown in the figure, by using the low flicker noise characteristics of PMOS, a pair of PMOS is used as an input pair, which can reduce the phase noise of the whole circuit. Among them, two groups of cross-coupled NMOS form the load of the delay unit, realizing the differential output of the circuit. Moreover, positive feedback is introduced at the cross-coupled pair, which can improve the slope of the output waveform and reduce the transition time, thereby reducing the phase noise. However, the oscillation frequency of the circuit is low and the power consumption is high.

[0044] Therefore, the present application proposes a ring voltage-controlled oscillator aiming at the problem of mutual restriction between power consumption and phase noise existing in the widely used Ring-VCO. The ring voltage-controlled oscillator is a three-stage Ring-VCO circuit structure with low power consumption and low phase noise. Meanwhile, a coarse strip and a fine tuning capacitor array are used to expand the tuning range. In view of the linearity problem of fine tuning, technical means of using I-MOS (Inversion-Mode Metal-Oxide-Semiconductor) varactor pair to suppress the tuning nonlinearity of A-MOS (Accumulation-Mode Metal-Oxide-Semiconductor) varactor pair are given. Moreover, an innovative structure of double-loop plus NMOS feedback is adopted, so that the output noise voltage or current is offset, thereby reducing the phase noise.

[0045] Next, a ring voltage-controlled oscillator and a multi-mode receiver according to the present embodiment will be described with reference to the accompanying drawings.

[0046] Figure 3 A structure diagram of a ring voltage-controlled oscillator according to an embodiment of the present application is shown in the figure. Figure 3 As shown in the figure, the ring voltage-controlled oscillator comprises three double-path structure delay units connected in sequence, wherein the first differential output end Voutp1 and the second differential output end Voutn1 of the first double-path structure delay unit Delay1 are connected with the first differential input end Vinp2 and the second differential input end Vinn2 of the second double-path structure delay unit Delay2 respectively; the first differential output end Voutp2 and the second differential output end Voutn2 of the second double-path structure delay unit Delay2 are connected with the first differential input end Vinp3 and the second differential input end Vinn3 of the third double-path structure delay unit Delay3 respectively; and the first differential output end Voutp3 and the second differential output end Voutn3 of the third double-path structure delay unit Delay3 are connected with the second differential input end Vinn1 and the first differential input end Vinp1 of the first double-path structure delay unit Delay1 respectively.

[0047] Figure 4 The structure diagram of a double-path structure delay unit provided by an embodiment of the present application is shown in the figure. Figure 4 The double-path structure delay unit comprises a first MOS transistor to a tenth MOS transistor.

[0048] The gate of the first MOS transistor M11 and the source of the fifth MOS transistor M51 are connected with a corresponding first differential input terminal Vinp, the drain of the first MOS transistor M11 is connected with the drain of the third MOS transistor M31, the gate of the third MOS transistor M31, the gate of the fourth MOS transistor M41 and the gate of the fifth MOS transistor M51, the source of the third MOS transistor M31, the source of the fourth MOS transistor M41 and the drain of the fifth MOS transistor M51 are all connected with a first power supply vdd, the drain of the fourth MOS transistor M41 and the drain of the second MOS transistor M21 are connected with a corresponding first differential output terminal Voutp, the source of the first MOS transistor M11 and the source of the second MOS transistor M21 are grounded, the gate of the second MOS transistor M21 is connected with a corresponding second differential input terminal Vinn; the gate of the sixth MOS transistor M12 and the source of the tenth MOS transistor M52 are connected with a corresponding second differential input terminal Vinn, the drain of the sixth MOS transistor M12 is connected with the drain of the eighth MOS transistor M32, the gate of the eighth MOS transistor M32, the gate of the ninth MOS transistor M42 and the gate of the tenth MOS transistor M52, the source of the eighth MOS transistor M32, the source of the ninth MOS transistor M42 and the drain of the tenth MOS transistor M52 are all connected with the first power supply vdd, the drain of the ninth MOS transistor M42 and the drain of the seventh MOS transistor M22 are connected with a corresponding second differential output terminal Voutn, the source of the sixth MOS transistor M12 and the source of the seventh MOS transistor M22 are grounded, and the gate of the seventh MOS transistor M22 is connected with a corresponding first differential input terminal Vinp.

[0049] In the embodiment, the differential input terminals composed of M11 and M12 respectively add a secondary signal loop composed of M22 and M21 and respectively add NMOS transistors shown as M51 and M52 on the left and right sides as feedback, wherein M31, M41 and M32, M42 respectively form current mirror structures on the left and right sides. In the embodiment, the input signal at one end is fed back to the output end to form a differential signal through the M11 common-source structure and the M51 source follower, part of the main noise source directly reaches one end of the differential output through the M11 common-source electrical path, and part of the main noise source is fed back to the input end through the M51 source follower and reaches the other end of the differential output through the secondary common-source transistor shown as M22. When the parameter design of the circuit meets certain conditions, the noise of the main noise source in the double-path structure delay unit can be eliminated at the differential output end, so as to reduce the phase noise of the Ring-VCO.

[0050] Please continue to referFigure 4 Each dual-path structure delay unit further comprises an A-MOS pair connected in parallel between the corresponding first differential output terminal Voutp and second differential output terminal Voutn.

[0051] As shown in Figure 4 , the A-MOS pair comprises a first adjustable capacitor Ca and a second adjustable capacitor Cb connected in series and then connected in parallel between the corresponding first differential output terminal Voutp and second differential output terminal Voutn, wherein one end of the first adjustable capacitor Ca and the second adjustable capacitor Cb is further connected to the second power supply Vc.

[0052] Please continue to refer to Figure 4 Each dual-path structure delay unit further comprises a SwitchedCap Array circuit connected in parallel between the corresponding first differential output terminal Voutp and second differential output terminal Voutn.

[0053] As shown in Figure 5 , the SwitchedCap Array circuit comprises a first capacitor C1 and a second capacitor C2, eleventh to thirteenth MOS transistors M6-M8, and a first resistor R1 and a second resistor R2.

[0054] Wherein, the gate of the eleventh MOS transistor M6 is connected to the drain of the twelfth MOS transistor M7 and the thirteenth MOS transistor M8, the drain of the eleventh MOS transistor M6 is connected to the corresponding first differential output terminal Voutp through the first capacitor C1, the source of the eleventh MOS transistor M6 is connected to the corresponding second differential output terminal Voutn through the second capacitor C2, the source of the twelfth MOS transistor M7 is connected to the first power supply vdd, the source of the thirteenth MOS transistor M8 is grounded, and the gates of the twelfth MOS transistor M7 and the thirteenth MOS transistor M8 are connected to the third power supply Vn; one end of the first resistor R1 is connected to the drain of the eleventh MOS transistor M6, one end of the second resistor R2 is connected to the source of the eleventh MOS transistor M6, and the other ends of the first resistor R1 and the second resistor R2 are connected to the third power supply Vn.

[0055] In this embodiment, the frequency tuning of the circuit can be realized by adding the A-MOS pair and the tuning voltage Vc, and on the basis of frequency tuning, the SwitchedCap Array circuit can be further added as shown in Figure 5The capacitor switch array is shown to further increase the tuning range of the Ring-VCO, and to realize a low phase noise low power Ring-VCO with a certain frequency range. In the capacitor switch array circuit, M7 and M8 form an inverter to input the control signal Vn, and R1, R2 and M6 form a switch structure to control the connection and disconnection of the capacitors C1 and C2.

[0056] Please continue to refer to Figure 4 Each double-path structure delay unit further comprises an I-MOS pair circuit connected in parallel between the corresponding first differential output end Voutp and second differential output end Voutn.

[0057] As Figure 6 The I-MOS pair circuit comprises a third capacitor C3 and a fourth capacitor C4, a fourteenth MOS transistor M9 to a sixteenth MOS transistor M11, and a third resistor R3 to a sixth resistor R6.

[0058] The gate of the fourteenth MOS transistor M9 is connected to the corresponding first differential output end Voutp through the third capacitor C3, the gate of the fifteenth MOS transistor M10 is connected to the corresponding second differential output end Voutn through the fourth capacitor C4, and the source and drain of the fourteenth MOS transistor M9 and the source and drain of the fifteenth MOS transistor M10 are connected to the second power supply Vc; one end of the third resistor R3 and the fourth resistor R4 is connected to the gate of the fourteenth MOS transistor M9 and the fifteenth MOS transistor M10 respectively, the other end of the third resistor R3 and the fourth resistor R4 and one end of the fifth resistor R5 and the sixth resistor R6 are connected to the gate of the sixteenth MOS transistor M11, the other end of the fifth resistor R5 and the source and drain of the sixteenth MOS transistor M11 are grounded, and the other end of the sixth resistor R6 is connected to the first power supply vdd.

[0059] In this embodiment, in order to suppress the large gain variation during band switching, an I-MOS pair circuit as shown in Figure 6 is added to the traditional A-MOS pair, so that the difference in the capacitance slope of the A-MOS pair is compensated by the I-MOS pair. In the I-MOS pair circuit of this embodiment, M9 and M10 are the main I-MOS pair, and M11 is equivalent to a filter capacitor. R5 and R6 divide the voltage of the first power supply vdd, and in combination with C3, R3 and C4, R4, provide a suitable bias for the varactor. The gain linearity optimization technology proposed in this embodiment can improve the tuning performance of the VCO and enhance the loop stability of the clock phase-locked loop without increasing the chip cost.

[0060] It should be noted that Figure 4-6The first MOS transistor, the second MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the tenth MOS transistor, the eleventh MOS transistor, the thirteenth MOS transistor and the fourteenth MOS transistor to the sixteenth MOS transistor in the first MOS transistor are NMOS transistors; the third MOS transistor, the fourth MOS transistor, the eighth MOS transistor, the ninth MOS transistor and the twelfth MOS transistor are PMOS transistors.

[0061] The present application adopts a three-stage delay unit structure, wherein each delay unit is composed of a small amount of single-stage amplifier and feedback network, so that signal voltage and noise voltage can form inverted and in-phase noise voltage or current at the output end respectively, thereby reducing phase noise. Meanwhile, the present application can improve fine tuning linearity by adopting the method of adjusting the capacitance of A-MOS varactor pair by I-MOS varactor pair, and can expand the frequency range by adopting switch capacitor array.

[0062] Further, the present application also provides a multi-mode receiver. As shown in the figure, the multi-mode receiver comprises the ring-type voltage-controlled oscillator. Figure 7

[0063] In summary, the present application provides a ring-type voltage-controlled oscillator and a multi-mode receiver, wherein the ring-type voltage-controlled oscillator is a three-stage Ring-VCO circuit structure with low power consumption and low phase noise, and specifically adopts a new structure of double common-source stage plus NMOS transistor source following feedback, so that the output noise voltage or current can be offset, thereby reducing phase noise. Meanwhile, the present application adds varactor pair and capacitor switch array at the output end, so that the frequency tuning of the circuit can be realized by introducing varactor and tuning voltage, and the tuning range of Ring-VCO can be further increased by capacitor switch array. In addition, in order to realize small VCO gain change, the present application adds a biased I-MOS varactor pair in parallel on the basis of the traditional A-MOS varactor pair, so that the poor capacitance characteristics of A-MOS varactor pair are compensated by I-MOS varactor pair, thereby optimizing the tuning linearity of VCO.

[0064] It should be noted that, in this text, relational terms such as first and second are used only to distinguish one entity or operation from another, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitation, the element defined by the statement "including a" does not exclude the presence of additional identical elements in the process, method, article or equipment including the element. ​

[0065] While the application has been described in detail by reference to preferred embodiments thereof, it is to be understood that the description is not to be construed as limiting the scope of the application. Various modifications and equivalents will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the application is to be determined by the following claims.

Claims

1. A ring-type voltage-controlled oscillator, characterized in that, The application relates to a three-stage delay unit, which comprises three double-path structure delay units connected in sequence, wherein the first differential output end and the second differential output end of the first double-path structure delay unit are connected with the first differential input end and the second differential input end of the second double-path structure delay unit respectively; the first differential output end and the second differential output end of the second double-path structure delay unit are connected with the first differential input end and the second differential input end of the third double-path structure delay unit respectively; and the first differential output end and the second differential output end of the third double-path structure delay unit are connected with the second differential input end and the first differential input end of the first double-path structure delay unit respectively. Each double-path structure delay unit comprises: The gate of the first MOS transistor and the source of the fifth MOS transistor are connected with the corresponding first differential input end, the drain of the first MOS transistor is connected with the drain of the third MOS transistor, the gate of the third MOS transistor, the gate of the fourth MOS transistor and the gate of the fifth MOS transistor, the source of the third MOS transistor, the source of the fourth MOS transistor and the drain of the fifth MOS transistor are connected with the first power supply, the drain of the fourth MOS transistor and the drain of the second MOS transistor are connected with the corresponding first differential output end, the source of the first MOS transistor and the source of the second MOS transistor are grounded, and the gate of the second MOS transistor is connected with the corresponding second differential input end. The gate of the sixth MOS transistor and the source of the tenth MOS transistor are connected with the corresponding second differential input end, the drain of the sixth MOS transistor is connected with the drain of the eighth MOS transistor, the gate of the eighth MOS transistor, the gate of the ninth MOS transistor and the gate of the tenth MOS transistor, the source of the eighth MOS transistor, the source of the ninth MOS transistor and the drain of the tenth MOS transistor are connected with the first power supply, the drain of the ninth MOS transistor and the drain of the seventh MOS transistor are connected with the corresponding second differential output end, the source of the sixth MOS transistor and the source of the seventh MOS transistor are grounded, and the gate of the seventh MOS transistor is connected with the corresponding first differential input end. Each double-path structure delay unit further comprises:

2. The ring voltage-controlled oscillator of claim 1, wherein An A-MOS varactor pair is connected in parallel between the corresponding first differential output end and second differential output end. The A-MOS varactor pair comprises:

3. The ring voltage controlled oscillator of claim 2, wherein the first and second capacitors are formed by a plurality of capacitors connected in series. A first adjustable capacitor and a second adjustable capacitor are connected in series and then connected in parallel between the corresponding first differential output end and second differential output end, wherein one end of the first adjustable capacitor and the second adjustable capacitor is further connected with the second power supply. Each double-path structure delay unit further comprises:

4. The ring voltage controlled oscillator of claim 3, wherein the first and second capacitors are formed by a plurality of capacitors connected in series. A capacitor switch array circuit is connected in parallel between the corresponding first differential output end and second differential output end. The capacitor switch array circuit comprises:

5. The ring voltage controlled oscillator of claim 4, wherein the first and second capacitors are formed by a plurality of capacitors connected in series. A first capacitor and a second capacitor. ​ a twelfth MOS transistor and a thirteenth MOS transistor, a gate of the eleventh MOS transistor is connected with a drain of the twelfth MOS transistor and a drain of the thirteenth MOS transistor respectively, a source of the eleventh MOS transistor is connected with a corresponding first differential output terminal through the first capacitor, a source of the twelfth MOS transistor is connected with the first power supply, a source of the thirteenth MOS transistor is grounded, and gates of the twelfth MOS transistor and the thirteenth MOS transistor are connected with a third power supply; a first resistor and a second resistor, one end of the first resistor is connected with the drain of the eleventh MOS transistor, one end of the second resistor is connected with the source of the eleventh MOS transistor, and the other ends of the first resistor and the second resistor are connected with the third power supply.

6. The ring voltage controlled oscillator of claim 5, wherein the first and second capacitors are formed by a plurality of capacitors connected in series. Each of the double-path structure delay units further comprises: an I-MOS varactor pair circuit connected in parallel between the corresponding first differential output terminal and the second differential output terminal.

7. The ring voltage controlled oscillator of claim 6, wherein the first and second capacitors are formed by a plurality of capacitors connected in series. The I-MOS varactor pair circuit comprises: a third capacitor and a fourth capacitor; a fourteenth MOS transistor to a sixteenth MOS transistor, a gate of the fourteenth MOS transistor is connected with the corresponding first differential output terminal through the third capacitor, a gate of the fifteenth MOS transistor is connected with the corresponding second differential output terminal through the fourth capacitor, and sources and drains of the fourteenth MOS transistor and the fifteenth MOS transistor are connected with the second power supply; a third resistor to a sixth resistor, one end of the third resistor and the fourth resistor is connected with the gate of the fourteenth MOS transistor and the fifteenth MOS transistor respectively, the other end of the third resistor and the fourth resistor, and one end of the fifth resistor and the sixth resistor are connected with a gate of the sixteenth MOS transistor, the other end of the fifth resistor, sources and drains of the sixteenth MOS transistor are grounded, and the other end of the sixth resistor is connected with the first power supply.

8. The ring voltage controlled oscillator of claim 7, wherein the first and second capacitors are formed by a plurality of capacitors connected in series. The first MOS transistor, the second MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the tenth MOS transistor, the eleventh MOS transistor, the thirteenth MOS transistor, and the fourteenth MOS transistor to the sixteenth MOS transistor are all NMOS transistors, and the third MOS transistor, the fourth MOS transistor, the eighth MOS transistor, the ninth MOS transistor, and the twelfth MOS transistor are all PMOS transistors.

9. A multi-mode receiver, characterized by The ring type voltage-controlled oscillator comprises the ring type voltage-controlled oscillator according to any one of claims 1 to 8.

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