Semiconductor structure and its fabrication method, memory

Abstract

This disclosure provides a semiconductor structure and its fabrication method, as well as a memory. The semiconductor structure includes: a plurality of active regions arranged in an array along intersecting first and second directions and spaced apart by an isolation structure; a bit line selection structure including a first gate, a second gate, a third gate, and a fourth gate located on four adjacent active regions, and at least one connecting line located on the isolation structure; one end of the first gate is connected to one end of the second gate, one end of the third gate is connected to one end of the fourth gate, and the connecting line connects the two corresponding ends of the first gate and the third gate and / or the two corresponding ends of the second gate and the fourth gate; a plurality of contact structures; each contact structure is located on one side of a gate, closer to the connecting line, and connected to an active region, the orthographic projection of the contact structure onto the plane of the active region being located at a position in the corresponding active region close to the connecting line.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method for fabricating the same, and a memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) consists of arrayed memory cells (memory bits). Each memory cell includes a transistor and a capacitor. The transistor acts as a switch between the capacitor and the bit line (BL), and can be activated by a word line (WL) coupled to the control terminal of the transistor. The memory cell stores binary information as charge on the capacitor. The bit line select line (CSL) signal of the column select line of the bit line select unit turns on the bit line select line transistor, allowing external circuitry to read specific information from the BL. Alternatively, external circuitry can write to the memory cell through the BL, ensuring that the data stored in the memory cell can be correctly written to or read from.

[0003] However, the design of bit line select units faces many challenges, such as the mismatch between multiple bit line select line transistors in the bit line select unit, which is an urgent problem to be solved. Summary of the Invention

[0004] To address the related technical issues, this disclosure provides a semiconductor structure, its fabrication method, and a memory.

[0005] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising:

[0006] Multiple active regions are arranged in an array along intersecting first and second directions and separated by an isolation structure; the first direction is parallel to the direction in which the active regions extend.

[0007] The bit line selection structure includes a first gate, a second gate, a third gate, and a fourth gate, all extending along the second direction and located on four adjacent active regions of the plurality of active regions, and at least one connecting line extending along the first direction and located on the isolation structure; one end of the first gate is connected to one end of the second gate, one end of the third gate is connected to one end of the fourth gate, and the connecting line connects the two corresponding ends of the first gate and the third gate and / or the two corresponding ends of the second gate and the fourth gate;

[0008] Multiple contact structures; each contact structure is located on one side of a gate near the connection line and connected to an active region, wherein the orthographic projection of the contact structure onto the plane of the active region is located in the corresponding active region near the connection line.

[0009] In the above scheme, the four adjacent active regions include a first active region, a second active region, a third active region, and a fourth active region. The first gate is located on the first active region, the second gate is located on the second active region, the third gate is located on the third active region, and the fourth gate is located on the fourth active region.

[0010] The plurality of contact structures include a first contact structure, a second contact structure, a third contact structure, and a fourth contact structure. The first contact structure is located on one side of the first gate and connected to the first active region. The second contact structure is located on one side of the second gate and connected to the second active region. The third contact structure is located on one side of the third gate and connected to the third active region. The fourth contact structure is located on one side of the fourth gate and connected to the fourth active region.

[0011] In the above scheme, the bit line selection structure includes a connecting line, which connects the connection ends of the first gate and the second gate and the connection ends of the third gate and the fourth gate;

[0012] The first contact structure and the third contact structure are both located on one side of the connecting line and close to the connecting line along the second direction, while the second contact structure and the fourth contact structure are both located on the other side of the connecting line and close to the connecting line along the second direction.

[0013] In the above scheme, the bit line selection structure further includes: a bit line selection line contact and a bit line selection line; one end of the bit line selection line contact is connected to the end of the connection between the first gate and the second gate or the end of the connection between the third gate and the fourth gate, and the other end is connected to the bit line selection line.

[0014] In the above scheme, the bit line selection structure includes two connecting lines, wherein the first connecting line of the two connecting lines is connected to the end of the first gate that is not connected to the second gate and the end of the third gate that is not connected to the fourth gate, and the second connecting line of the two connecting lines is connected to the end of the second gate that is not connected to the first gate and the end of the fourth gate that is not connected to the third gate.

[0015] The first contact structure and the third contact structure are both located on one side of the first connecting line and close to the first connecting line along the second direction. The second contact structure and the fourth contact structure are both located on one side of the second connecting line and close to the second connecting line along the second direction.

[0016] In the above scheme, the bit line selection structure further includes: a bit line selection line contact structure and a bit line selection line; one end of the bit line selection line contact structure is connected to the middle of the first connecting line or the middle of the second connecting line, and the other end is connected to the bit line selection line.

[0017] In the above scheme, the bit line selection structure further includes: sidewall isolation layers located on both sides of each gate; the dimension of the portion of the sidewall isolation layer near the connection line along the first direction is larger than the dimension of the portion of the sidewall isolation layer away from the connection line along the first direction; the contact structure at least penetrates the portion of the sidewall isolation layer near the connection line.

[0018] In the above scheme, the semiconductor structure further includes: multiple bit lines; the multiple bit lines are arranged along the first direction, and each bit line is connected to a contact structure; the orthographic projections of the multiple bit lines on the plane where the active region is located are separated from each other.

[0019] In the above scheme, each bit line includes a main body portion extending along the second direction and a protruding portion extending along the first direction, and each protruding portion is connected to a contact structure.

[0020] In the above scheme, the bit line selection structure further includes: a first source and a first drain located in each active region and on opposite sides of the corresponding gate, and each contact structure is connected to a first source or a first drain on the side closest to the connection line.

[0021] In the above scheme, the semiconductor structure includes:

[0022] The plurality of bit line selection structures include a first bit line selection structure and a second bit selection structure arranged along the first direction, wherein the gates connected to the two ends of the first bit line selection structure and the gates connected to the two ends of the second bit line selection structure share two adjacent active regions along the second direction.

[0023] The two shared active regions are provided with a first source and a first drain corresponding to the two ends of the gate connected to the first bit line selection structure, and a second source and a second drain corresponding to the two ends of the gate connected to the second bit line selection structure; the first source / second source located between the two ends of the gate connected to the first bit line selection structure and the two ends of the gate connected to the second bit line selection structure are shared, or the first drain / second drain is shared.

[0024] In the above scheme, the first direction is perpendicular to the second direction.

[0025] According to a second aspect of the present disclosure, a memory is provided, comprising:

[0026] The semiconductor structure as described in any of the above schemes.

[0027] According to a third aspect of the present disclosure, a method for fabricating a semiconductor structure is provided, comprising:

[0028] Multiple active regions are formed, and the multiple active regions are arranged in an array along intersecting first and second directions and are separated by an isolation structure; the first direction is parallel to the direction in which the active regions extend;

[0029] A bit line selection structure is formed, including a first gate, a second gate, a third gate, and a fourth gate, all extending along the second direction and located on four adjacent active regions of the plurality of active regions, and at least one connecting line extending along the first direction and located on the isolation structure; one end of the first gate is connected to one end of the second gate, one end of the third gate is connected to one end of the fourth gate, and the connecting line connects the two corresponding ends of the first gate and the third gate and / or the two corresponding ends of the second gate and the fourth gate;

[0030] Multiple contact structures are formed, each of which is located on one side of a gate near the connection line and connected to an active region. The orthographic projection of the contact structure onto the plane of the active region is located in the corresponding active region near the connection line.

[0031] The method in the above scheme further includes:

[0032] Sidewall isolation layers are formed on both sides of each gate; the portion of the sidewall isolation layer near the connection line has a larger dimension along the first direction than the portion of the sidewall isolation layer away from the connection line.

[0033] The formation of the plurality of contact structures includes:

[0034] A contact hole is formed that penetrates at least a portion of the sidewall isolation layer on the side closest to the connecting line;

[0035] Ion implantation is performed on the portion of the active region exposed by the contact hole;

[0036] The contact structure is obtained by incorporating conductive material into the contact hole.

[0037] The method in the above scheme further includes:

[0038] Before forming the sidewall isolation layer, a first protective layer covering each gate is formed;

[0039] After the sidewall isolation layer is formed, a second protective layer is formed to cover the sidewall isolation layer.

[0040] In this embodiment of the disclosure, the semiconductor structure includes a plurality of gates on the active region that are electrically connected as a whole by the connecting lines, which can ensure that the conduction and shutdown characteristics of transistors in all bit line selection structures are consistent. By setting all the contact structures that contact the source / drain regions of the active region at positions close to the connecting lines, the regional resistance of the contact structures on the active region can be reduced, thereby enabling the semiconductor structure to obtain better current characteristics. This ensures that all bit line selection structures have consistent characteristics and better electrical characteristics, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0041] Figure 1 A circuit diagram of a core device of a memory provided in an embodiment of this disclosure;

[0042] Figure 2 A partial schematic diagram of the circuit layout of a core device of a memory provided in an embodiment of this disclosure;

[0043] Figure 3 A schematic diagram of the circuit and circuit layout design for the inductive amplifier region provided in an embodiment of this disclosure;

[0044] Figure 4a This is a schematic diagram of the layout of a semiconductor structure provided in an embodiment of the present disclosure;

[0045] Figure 4b This is a schematic diagram of the layout of another semiconductor structure provided in an embodiment of the present disclosure;

[0046] Figure 5a This is a schematic diagram of the layout of another semiconductor structure provided in an embodiment of the present disclosure;

[0047] Figure 5b A schematic diagram showing the test results of the on-state current (IDS) of another semiconductor structure provided in this embodiment of the present disclosure;

[0048] Figure 5c A schematic diagram of the test results of the threshold voltage-on-state current (VTGM-IDS) curve of another semiconductor structure provided in the embodiments of this disclosure;

[0049] Figures 6a to 6d Layout schematic diagrams of some other semiconductor structures provided in embodiments of this disclosure;

[0050] Figure 7 A schematic diagram illustrating the implementation flow of a semiconductor structure fabrication method provided in this embodiment of the disclosure;

[0051] Figures 8 to 14b The diagram shows a top view and a cross-sectional view of the fabrication process of a semiconductor structure according to an embodiment of this disclosure. Detailed Implementation

[0052] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0053] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0054] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0055] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0056] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0057] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0058] The memories involved in the embodiments of this disclosure include, but are not limited to, dynamic random access memory (DRAM). The following description uses DRAM as an example only. It should be noted that the following descriptions of DRAM in the embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0059] Figure 1 This is a circuit diagram of a core device of a memory provided in an embodiment of the present disclosure.

[0060] like Figure 1 As shown, the dynamic random access memory includes a large number of memory cell arrays and a large number of logic circuits coupled to the memory cell arrays. The logic circuits are responsible for controlling the operation of the entire memory chip.

[0061] Dynamic Random Access Memory (DRAM) includes memory cells, sub-word lines (SWL), bit lines (BLT / BLB), complementary bit lines (BLT' / BLB'), sub-word line drives (SWD), sense amplifiers (SA), equalizers (EQ), and bit line select units (also known as "bit line select structures"). The sense amplifiers (SA) include PSA (PMOS of Sense-Amplifier) ​​and NSA (NMOS of Sense-Amplifier). The bit line select units include bit line select lines (CSL) and bit line select line transistors (Tc1 and Tc2). In the following text, the bit line select unit may also be referred to as a bit line selector, column selector, or column selector, and the bit line select line (CSL) may also be referred to as a column select line (CSL).

[0062] Each memory cell includes a transistor T and a capacitor C, i.e., a 1T1C structure. The capacitor stores information, and the amount of charge stored within it, or the voltage difference across the capacitor, represents a logical 1 or 0. (Word lines are referenced.) Figure 1 The voltage on the bit line (SWL) determines whether transistor T is turned on or off, and the on or off state of transistor T determines whether reading and writing of the information stored in the capacitor is allowed or prohibited; the bit line (reference) Figure 1 The middle bit line (BLT) and complementary bit line (BLT') are the only channels for external lines to access capacitor C. When transistor T is turned on, external lines can read or write to capacitor C through the bit lines. The sub-word line driver SWD circuit is mainly responsible for providing the drive voltage for the memory. The sensing amplifier SA is connected between bit line BLT and complementary bit line BLT' to detect and amplify the voltage difference between a pair of bit lines BLT and complementary bit line BLT'. The equalizer EQ is located between bit line BLT and complementary bit line BLT' to equalize the voltage between bit line BLT and complementary bit line BLT'. The bit line selection unit is used to select the bit line BLT and complementary bit line BLT' to perform read and write operations through the bit line selection line CSL. The bit line selection line transistors Tc1 and Tc2 are turned on through the bit line selection line signal. External lines (reference) Figure 1 The Local Input / Output (LIO) function can read the information stored in the capacitor from the bit line BLT and the complementary bit line BLT'. Alternatively, external lines can rewrite the information stored in the capacitor through the bit line BLT and the complementary bit line BLT', thus enabling the data stored in the memory cell to be correctly written or read.

[0063] Figure 2 This is a partial schematic diagram of the circuit layout of a core device of a memory provided in an embodiment of this disclosure. Figure 3 This is a schematic diagram of the circuit and circuit layout design for the inductive amplifier region provided in an embodiment of this disclosure. It should be noted that... Figure 3 for Figure 2 Enlarged view of the area within the dashed box.

[0064] like Figure 2 As shown, here, it can correspond to Figure 1 The circuit diagram shown illustrates that the memory includes a memory cell array (Array) region, an inductive amplifier (SA) region, and a sub-word line driver (SWD) region.

[0065] like Figure 3 As shown, here, it can correspond to Figure 1 The circuit diagram shown can be used to understand that the SA region of the inductive amplifier mainly includes multiple circuit modules such as the equalizer EQ, the P-type transistor PSA of the inductive amplifier, the N-type transistor NSA of the inductive amplifier, and the bit line selector CS.

[0066] To ensure that the data amplified by the induction amplifier can be effectively and quickly read and transmitted to the local input / output (reference) Figure 1 Data from local input / output (LIO, LIO') requires bit-line select line transistors (see reference). Figure 1 The bit line select line transistors (Tc1 and Tc2) have good switching characteristics, such as a good on / off ratio (Ion / Ioff). It is necessary to maintain the performance consistency between the bit line select line transistors Tc1 and Tc2 to avoid mismatch.

[0067] Figure 4a This is a schematic diagram of the layout of a semiconductor structure provided in an embodiment of the present disclosure; Figure 4b This is a schematic diagram of the layout of another semiconductor structure provided in an embodiment of this disclosure.

[0068] refer to Figure 4a and Figure 4b The semiconductor structure includes: bit line select line CSL, bit line select line transistors Tc1 and Tc2, bit lines and complementary bit lines BLT, BLT', BLB, and BLB', and input / output lines LIO and LIO'. Here, it can correspond to... Figure 1 The circuit diagram shown is for reference. It should be noted that the bit lines BLT, BLT', BLB, BLB' and the input / output lines LIO, LIO' are shown in perspective to show the layout of the source-drain contact structure C of the bit line select line transistors Tc1 and Tc2.

[0069] For example, the bit line select line CSL is connected to the gates G1 and G2 of the bit line select line transistors Tc1 and Tc2 via the bit line select line contact CSLC (or column select line contact CSLC); the bit lines BLT and BLT' are connected to the sources S1 and S2 of the bit line select line transistors Tc1 and Tc2 via the contact structure C, respectively; and the input / output lines LIO and LIO' are connected to the drains D1 and D2 of the bit line select line transistors Tc1 and Tc2 via the contact structure C, respectively.

[0070] In order to ensure that the data amplified by the induction amplifier SA can be effectively and quickly read and transmitted to the input / output lines LIO and LIO', the bit line select transistors Tc1 and Tc2 need to have good switching characteristics. At the same time, in order to prevent the data read by each data unit from being different, the multiple bit line select transistors Tc1 and Tc2 in the same group also need to be consistent.

[0071] Figure 4a and Figure 4b The diagram shows the layout designs of two semiconductor structures. The arrangement of the first gate G1, the second gate G2, the third gate G3, and the fourth gate G4, as well as the connecting lines CG (or connecting lines CG1 and CG2), forms an "H" shape (or a rectangle). The layout is regular and symmetrical, which is beneficial for manufacturing and the consistency of electrical performance.

[0072] In practical applications, to maintain maximum data output density, semiconductor structures consist of groups of four or eight transistors. For example, the following description uses a semiconductor structure consisting of groups of four transistors.

[0073] Figure 5a This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure. It should be noted that, in order to highlight the layout of the contact structures C1 to C4 on the source and drain of the bit line select line transistor, the active regions AA1 to AA4 corresponding to the bit line select line transistor, the gates G1 to G4, the connecting line CG, the bit line select line contact CSLC, and the contact structures C1 to C4 are shown. Other structures, such as bit lines, input / output lines, and isolation structures between active regions, are not shown.

[0074] Figure 5b This diagram illustrates the test results of the on-state current (IDS) of another semiconductor structure provided in this embodiment of the present disclosure. Figure 5c This is a schematic diagram of the test results of the threshold voltage-on-state current (VTGM-IDS) curve of another semiconductor structure provided in the embodiments of this disclosure.

[0075] It should be noted that this is based on Figure 5aThe provided semiconductor structure was tested by comparing the bit line select line transistors corresponding to contact structures C1 to C4.

[0076] refer to Figure 5a Each active region (e.g., active region AA1) and the contact structure on the active region (e.g., contact structure C1) are placed in exactly the same corresponding position, similar to the result of continuously replicating a unit. However, depending on the distance from the connecting line CG, the distance between contact structures C1 and C3 and the connecting line CG is smaller than the distance between contact structures C2 and C4 and the connecting line CG. That is, contact structures C1 and C3 are closer to the connecting line CG than contact structures C2 and C4.

[0077] refer to Figure 5b Table 1 below, and Figure 5a Under normal operating conditions, the operating current IDS (also known as "on-state current") of the bit line select line transistors corresponding to contact structures C1 and C3 is typically larger than that of the bit line select line transistors corresponding to contact structures C2 and C4. Figure 5b It can be observed that the bit line select line transistors corresponding to contact structures C1 and C3 have much better electrical performance than those corresponding to contact structures C2 and C4, with the on-state current IDS increasing by about 6%.

[0078] Table 1

[0079] C1 C2 C3 C4 IDS (median) / μA 79.8 74.4 79.8 75.2

[0080] Additionally, refer to Figure 5c Under the same threshold voltage VTGM, the on-state current (expected value) of the bit line select line transistors corresponding to contact structures C1 and C3 is usually larger than the on-state current (expected value) of the bit line select line transistors corresponding to contact structures C2 and C4.

[0081] In other words, a design structure where the contact structure is closer to the connection line can ensure that the characteristics of the bit line select line transistors corresponding to the contact structure are consistent, and also have better electrical characteristics.

[0082] Based on this, in order to solve one or more of the above problems, embodiments of this disclosure propose to move the contact structure to a position adjacent to the connection line, thereby improving the performance of the bit line select line transistor in the bit line selector and reducing mismatch.

[0083] Figures 6a to 6d This is a schematic diagram showing the layout of some other semiconductor structures provided in embodiments of this disclosure. It should be noted that... Figures 6a to 6dIn order to highlight the layout of the contact structures C1 to C4 on the source and drain of the bit line select line transistor, the active regions AA1 to AA4, gates G1 to G4, connecting lines CG, bit line select line contacts CSLC, and contact structures C1 to C4 corresponding to the bit line select line transistor are shown. Other structures such as bit lines, input / output lines, and isolation structures between active regions are not shown.

[0084] refer to Figure 6a and Figure 6b According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising:

[0085] Multiple active regions are arranged in an array along intersecting first and second directions and separated by an isolation structure; the first direction is parallel to the direction in which the active regions extend.

[0086] The bit line selection structure includes a first gate, a second gate, a third gate, and a fourth gate, all extending along the second direction and located on four adjacent active regions of the plurality of active regions, and at least one connecting line extending along the first direction and located on the isolation structure; one end of the first gate is connected to one end of the second gate, one end of the third gate is connected to one end of the fourth gate, and the connecting line connects the two corresponding ends of the first gate and the third gate and / or the two corresponding ends of the second gate and the fourth gate;

[0087] Multiple contact structures; each contact structure is located on one side of a gate near the connection line and connected to an active region, wherein the orthographic projection of the contact structure onto the plane of the active region is located in the corresponding active region near the connection line.

[0088] The following will combine Figure 6a and Figure 6b The semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0089] Here, the first direction is parallel to the direction in which each active region extends, and the second direction is parallel to the plane containing the active region, with an angle between the second and third directions ranging from 0 degrees to 90 degrees. In some embodiments, the first direction is perpendicular to the second direction. In some specific embodiments, the first direction can be the direction extending along the X-axis, and the second direction can be the direction extending along the Y-axis.

[0090] It should be noted that each bit selection structure in the embodiments of this disclosure can correspond to four transistors or more transistors, such as eight. Figure 6a and Figure 6b The diagram only shows the case where the bit line selection structure corresponds to four transistors. Figure 6a and Figure 6b The illustrations shown are not intended to limit the number of transistors corresponding to the bit line selection structure in the embodiments of this disclosure.

[0091] It is understood that each transistor may include: a gate located on the active region, and source and drain located on both sides of the gate within the active region.

[0092] It should be noted that, for ease of description in this embodiment, the active region and the bit line selection structure are described in parallel. However, in actual applications, the active region can also be classified into the bit line selection structure.

[0093] Here, multiple active regions can be arranged in an array along a first direction and a second direction, and different active regions are separated by an insulating structure (e.g., a shallow trench isolation structure, STI). Each active region extends along the first direction, and the shape of each active region includes a strip shape, which can be a right-angled strip shape or a rounded strip shape. For example, refer to... Figure 6a Each active region extends along the X-axis and is a right-angled strip.

[0094] In some embodiments, the material of the active region may include silicon (Si), germanium (Ge), silicon germanide (SiGe), etc. In some embodiments, the insulating structure ( Figure 6a and Figure 6b The constituent materials (not shown) include, but are not limited to, silicon oxide (SiO2).

[0095] Here, the bit line selection structure includes multiple gates corresponding to the transistor, the multiple gates being electrically connected as a whole by the interconnecting lines, and each gate extending along the Y-axis and spanning an active region. For example, refer to... Figure 6a and Figure 6b The first gate G1, the second gate G2, the third gate G3, and the fourth gate G4, along with connecting lines CG (or connecting lines CG1 and CG2), are electrically connected to form a single unit; wherein, one end of the first gate G1 is connected to one end of the second gate G2, and one end of the third gate G3 is connected to one end of the fourth gate G4, as shown below. Figure 6b As shown, the connecting line CG connects the two ends corresponding to the first gate G1 and the third gate G3, and the two ends corresponding to the second gate G2 and the fourth gate G4, or, as... Figure 6a As shown, the connecting lines CG1 and CG2 connect the two ends of the first gate G1 and the third gate G3 and / or the two ends of the second gate G2 and the fourth gate G4.

[0096] In some embodiments, the materials of the first gate G1, the second gate G2, the third gate G3, and the fourth gate G4, as well as the connecting lines CG (or connecting lines CG1, CG2), include, but are not limited to, polysilicon.

[0097] Here, multiple contact structures correspond to multiple gates of a transistor; each contact structure is located on the side of a gate closest to the connection line and connected to an active region. The orthographic projection of the contact structure onto the plane containing the active region is positioned within the corresponding active region, close to the connection line. It should be noted that "close" here can be understood as the shortest distance between the center point of the orthographic projection of the contact structure onto the plane containing the active region and the connection line being less than the shortest distance between the center point of the plane containing the active region and the connection line.

[0098] In some embodiments, the materials of the contact structure include, but are not limited to, tungsten, cobalt, nickel, copper, aluminum, polycrystalline silicon, doped silicon, silicides, or any combination thereof.

[0099] In this embodiment of the disclosure, the semiconductor structure includes a plurality of gates on the active region that are electrically connected as a whole by the connecting lines, which can ensure that the conduction and shutdown characteristics of transistors in all bit line selection structures are consistent. By setting all the contact structures that contact the source / drain regions of the active region at positions close to the connecting lines, the regional resistance of the contact structures on the active region can be reduced, thereby enabling the bit line selection structure to obtain better current characteristics. This ensures that all bit line selection structures have consistent characteristics and better electrical characteristics (e.g., a larger on / off ratio), thereby improving the performance of the semiconductor structure.

[0100] Refer to the above Figure 6a and Figure 6b In some embodiments, the four adjacent active regions include a first active region AA1, a second active region AA2, a third active region AA3, and a fourth active region AA4. The first gate G1 is located on the first active region AA1, the second gate G2 is located on the second active region AA2, the third gate G3 is located on the third active region AA3, and the fourth gate G4 is located on the fourth active region AA4.

[0101] The plurality of contact structures include a first contact structure C1, a second contact structure C2, a third contact structure C3, and a fourth contact structure C4. The first contact structure C1 is located on one side of the first gate G1 and connected to the first active region AA1. The second contact structure C2 is located on one side of the second gate G2 and connected to the second active region AA2. The third contact structure C3 is located on one side of the third gate G3 and connected to the third active region AA3. The fourth contact structure C4 is located on one side of the fourth gate G4 and connected to the fourth active region AA4.

[0102] Here, the arrangement of the first gate G1, the second gate G2, the third gate G3, and the fourth gate G4, as well as the connecting lines CG (or connecting lines CG1 and CG2), forms an upright "H" shape (or a rectangle). The layout is regular and symmetrical, which is beneficial for manufacturing and the consistency of electrical performance.

[0103] In some embodiments, the first gate G1 and the second gate G2, the third gate G3 and the fourth gate G4 are respectively located on the same straight line along the second direction, and the connecting line CG (or connecting lines CG1 and CG2) are in a straight line along the first direction. The straight line construction is more conducive to manufacturing and the consistency of electrical performance.

[0104] Refer to the above Figure 6b In some embodiments, the bit line selection structure includes a connection line CG, which connects the connection ends of the first gate G1 and the second gate G2 and the connection ends of the third gate G3 and the fourth gate G4.

[0105] The first contact structure C1 and the third contact structure C3 are both located on one side of the connecting line CG and close to the connecting line CG along the second direction. The second contact structure C2 and the fourth contact structure C4 are both located on the other side of the connecting line CG and close to the connecting line CG along the second direction.

[0106] Here, the arrangement of the first gate G1, the second gate G2, the third gate G3, the fourth gate G4, and the connecting line CG forms an upright "H" shape. The layout is regular and symmetrical, which is beneficial for manufacturing and the consistency of electrical performance.

[0107] In some embodiments, the first gate G1 and the second gate G2, the third gate G3 and the fourth gate G4 are respectively located on the same straight line along the second direction, and the connecting line CG is a straight line along the first direction. The straight line construction is more conducive to manufacturing and the consistency of electrical performance.

[0108] Here, in conjunction with the above Figures 5a to 5c Experimental analysis, Figure 6a or Figure 6b The first contact structure C1 and the third contact structure C3 are both located close to the connection line CG, and the second contact structure C2 and the fourth contact structure C4 are both located close to the connection line CG. This allows the transistor corresponding to the bit line selection structure to have better electrical characteristics (e.g., a larger on-state current).

[0109] In some embodiments, within the active region, the connecting lines CG (or connecting lines CG1, CG2) respectively form first, second, third, and fourth included-angle regions or rounded-corner regions with the first gate G1, second gate G2, third gate G3, and fourth gate G4. The first contact structure C1, second contact structure C2, third contact structure C3, and fourth contact structure C4 are positioned close to the included-angle regions or rounded-corner regions. That is, the projections of the first contact structure C1, second contact structure C2, third contact structure C3, and fourth contact structure C4 within the active region are at least partially located within the corresponding first, second, third, and fourth included-angle regions or rounded-corner regions. This allows the transistor corresponding to the bit-line selection structure to have a larger on / off ratio.

[0110] In some embodiments, the first contact structure C1 and the third contact structure C3, the second contact structure C2 and the fourth contact structure C4 are symmetrical about the connecting line CG; thus, the layout shape is regular and symmetrical, which is beneficial to manufacturing and the consistency of electrical performance.

[0111] In some embodiments, the bit line select structure further includes: a bit line select line contact CSLC and a bit line select line ( Figure 6b (Not shown); one end of the bit line select line is connected to the end of the CSLC where the first gate G1 and the second gate G2 are connected or the end of the third gate G3 and the fourth gate G4 are connected, and the other end is connected to the bit line select line.

[0112] Here, the bit line select line contact CSLC is located at the connection end between the first gate G1 and the second gate G2, or at the connection end between the third gate G3 and the fourth gate G4. In this way, the bit line select line signal via the bit line select line CSL can be transmitted synchronously or consistently through the bit line select line contact CSLC to the first gate G1 and the second gate G2, as well as the third gate G3 and the fourth gate G4.

[0113] In other embodiments, the bit line select line contact CSLC is located at the middle of the connection line CG. In this way, the bit line select line signal passing through the bit line select line CSL can be transmitted synchronously or uniformly through the bit line select line contact CSLC to each controlled transistor (the first gate G1, the second gate G2, the third gate G3, and the fourth gate G4). Here, along the X direction, the above... Figure 6b The bit line select line contact CSLC is moved to the middle of the connection line CG for understanding.

[0114] Refer to the above Figure 6a In some embodiments, the bit line selection structure includes two connection lines, wherein the first connection line CG1 of the two connection lines is connected to the end of the first gate G1 that is not connected to the second gate G2 and the end of the third gate G3 that is not connected to the fourth gate G4, and the second connection line CG2 of the two connection lines is connected to the end of the second gate G2 that is not connected to the first gate G1 and the end of the fourth gate G4 that is not connected to the third gate G3;

[0115] The first contact structure C1 and the third contact structure C3 are both located on one side of the first connecting line CG1 and close to the first connecting line CG1 along the second direction. The second contact structure C2 and the fourth contact structure C4 are both located on one side of the second connecting line CG2 and close to the second connecting line CG2 along the second direction.

[0116] Here, compared to the above Figure 6b The bitline selection structure described in [the document / reference]. Figure 6a The difference in the bit line selection structure described above lies in the arrangement of the first gate G1, second gate G2, third gate G3, and fourth gate G4, along with the two connecting lines CG1 and CG2, forming a rectangular shape. Other specific implementation details can be found above. Figure 6b The embodiments are understood in this way, and will not be repeated here.

[0117] In some embodiments, reference Figure 6a The bit line selection structure further includes: a bit line selection line contact CSLC and a bit line selection line ( Figure 6a (Not shown); one end of the bit line select line that contacts the CSLC is connected to the middle of the first connection line CG1 or the middle of the second connection line CG2, and the other end is connected to the bit line select line.

[0118] Here, compared to the above Figure 6b The bit line select line in the CSLC is contacted. Figure 6aThe difference in the bit line select line contact CSLC described above is that the bit line select line contact CSLC is not located at the connection end between the first gate G1 and the second gate G2 or the connection end between the third gate G3 and the fourth gate G4. Other specific implementation details can be found above. Figure 6b The embodiments are understood in this way, and will not be repeated here.

[0119] Refer to the following Figure 14a In some embodiments, the bit line selection structure further includes: sidewall isolation layers located on both sides of each gate; the dimension W1 of the portion of the sidewall isolation layer near the connection line along the first direction is greater than the dimension W2 of the portion of the sidewall isolation layer away from the connection line along the first direction; the contact structure at least penetrates the portion of the sidewall isolation layer near the connection line.

[0120] In this embodiment, the contact structure penetrates at least a portion of the sidewall isolation layer near the connection line. The formation process of the contact structure exposes the active region partially covered by the chamfered or rounded-corner isolation sidewalls, while simultaneously performing high-concentration ion implantation to reduce the resistance of this region, thereby obtaining better current characteristics and restoring the electrical characteristics of the bit line selection structure. For further details, please refer to the following... Figures 14a to 14b The relevant descriptions in the text will not be repeated here.

[0121] Refer to the above Figure 4a and Figure 4b In some embodiments, the semiconductor structure further includes: a plurality of bit lines; the plurality of bit lines are arranged along the first direction, and each bit line is connected to a contact structure; the orthographic projections of the plurality of bit lines onto the plane containing the active region are separated from each other.

[0122] Multiple bit lines arranged along the first direction are spaced apart from each other to ensure the independent transmission function of the bit lines.

[0123] Refer to the above Figure 4a and Figure 4b In some embodiments, each bit line includes a body portion extending along the second direction and a protrusion portion extending along the first direction, each protrusion portion being connected to a contact structure.

[0124] The protruding portion of each bit line connects a contact structure to the body portion of each bit line, such that multiple bit lines arranged along the first direction are spaced apart from each other (e.g., between bit lines and complementary bit lines).

[0125] Continue to refer to the above. Figure 6bIn some embodiments, the bit line selection structure further includes: a first source S1 and a first drain D1 located in each active region and situated on opposite sides of the corresponding gate, and each of the contact structures is connected to a first source S1 or a first drain D1 on the side closest to the connection line.

[0126] In some embodiments, the semiconductor structure includes:

[0127] Multiple bit line selection structures; the multiple bit line selection structures include a first bit line selection structure 11 and a second bit selection structure 12 arranged along the first direction, wherein the gates connected to the two ends of the first bit line selection structure 11 (e.g., the third gate G3 and the fourth gate G4 of the first bit line selection structure 11) and the gates connected to the two ends of the second bit line selection structure 12 (e.g., the first gate G1 and the second gate G2 of the second bit line selection structure 12) share two adjacent active regions (e.g., ...) along the second direction. Figure 6b The third active region AA3 and the fourth active region AA4 are shown in the figure;

[0128] Each of the two shared active regions is provided with a first source S1 and a first drain D1 corresponding to the gates connected to the two ends of the first bit line selection structure 11, and a second source S2 and a second drain D2 corresponding to the gates connected to the two ends of the second bit line selection structure; the first source / second source located between the gates connected to the two ends of the first bit line selection structure and the gates connected to the two ends of the second bit line selection structure are shared, or the first drain D1 / second drain D2 are shared.

[0129] It should be noted that the positions of the first source S1 and the first drain D1 can be interchanged, as can the positions of the second source S2 and the second drain D2. For example, as shown... Figure 6b As shown, contact structures C1, C2, C3, and C4 are located at the first source S1 and the second source S2, and output line contacts C5 and C6 are located on the first drain D1 and the second drain D2. It should be noted that the embodiments disclosed herein are also applicable to... Figure 6a The semiconductor structure shown can be found in the reference section for more details. Figure 6bTo understand this, the third gate G3 of the first bit line selection structure 11 and the first gate G1 of the second bit line selection structure 12 are located on a common third active region AA3. The transistor corresponding to the third gate G3 of the first bit line selection structure 11 and the transistor corresponding to the first gate G1 of the second bit line selection structure 12 share a drain (first drain D1 / second drain D2). A common output line contact C5 is formed on the common drain, and the output line contact C5 is used to connect the common drain and the input / output line; the first gate of the second bit line selection structure 12... G1 and the second gate G2 of the second bit line selection structure 12 are located on a common third active region AA4. The transistor corresponding to the first gate G1 of the second bit line selection structure 12 and the transistor corresponding to the second gate G2 of the second bit line selection structure 12 share a drain (first drain D1 / second drain D2). A common output line contact C6 is formed on the common drain. The output line contact C6 is used to connect the common drain and the input / output line. The output line contact C5 and the output line contact C6 are connected to the same input / output line. The first source S1 of the transistor corresponding to the third gate G3 of the first bit line selection structure 11, the first source S1 of the transistor corresponding to the fourth gate G4 of the first bit line selection structure 11, the second source S2 of the transistor corresponding to the first gate G1 of the second bit line selection structure 12, and the second source S2 of the transistor corresponding to the second gate G2 of the second bit line selection structure 12 are respectively electrically connected to their respective corresponding and spaced-apart bit lines BL through contact structures C1, C2, C3, and C4.

[0130] In some implementations, the dimensions of the output line contacts C5 and C6 along the second direction are larger than the dimensions of the contact structures C1, C2, C3, and C4 along the second direction. For example, the dimensions of the output line contacts C5 and C6 along the second direction are twice the dimensions of the contact structures C1, C2, C3, and C4 along the second direction. In this embodiment, the semiconductor structure comprises four transistors: the transistor corresponding to the third gate G3 of the first bit line selection structure 11, the transistor corresponding to the fourth gate G4 of the first bit line selection structure 11, the transistor corresponding to the first gate G1 of the second bit line selection structure 12, and the transistor corresponding to the second gate G2 of the second bit line selection structure 12. The transistor corresponding to the third gate G3 of the first bit line selection structure 11 and the transistor corresponding to the first gate G1 of the second bit line selection structure 12 share a common drain (first drain D1 / second drain D2), and the transistor corresponding to the first gate G1 of the second bit line selection structure 12 and the transistor corresponding to the second gate G2 of the second bit line selection structure 12 share a common drain (first drain D1 / second drain D2). The two shared drains are connected to the same input / output line. This structure can maintain the maximum data output density of the semiconductor structure.

[0131] refer to Figure 6c and Figure 6d In some embodiments, such as Figure 6c As shown, the bit line selection structure includes a connecting line CG1, which connects the unconnected end of the first gate G1 and the unconnected end of the third gate G3; the first contact structure C1 and the third contact structure C3 are both located on one side of the connecting line CG1 and close to the connecting line CG1 along the second direction; the second contact structure C2 and the fourth contact structure C4 are both located at the middle position of the corresponding active regions AA2 and AA4 along the second direction; or, as Figure 6d As shown, the bit line selection structure includes a connecting line CG2, which connects the unconnected end of the second gate G2 and the unconnected end of the fourth gate G4; the second contact structure C2 and the fourth contact structure C4 are both located on one side of the connecting line CG2 and close to the connecting line CG2 along the second direction; the first contact structure C1 and the third contact structure C3 are both located at the middle position of the corresponding active regions AA1 and AA3 along the second direction.

[0132] Here, compared to the above Figure 6a and Figure 6b The bitline selection structure described in [the document / reference]. Figure 6c and Figure 6dThe difference in the bit line selection structure shown is that the arrangement of the first gate G1, second gate G2, third gate G3, and fourth gate G4, as well as the connecting line CG1 or CG2, forms an inverted "U" shape or a regular "U" shape. This layout is regular in shape and has good symmetry, which is beneficial for manufacturing and consistency of electrical performance. Other specific implementation details can be found above. Figure 6a and Figure 6b The embodiments are understood in this way, and will not be repeated here.

[0133] According to a second aspect of the present disclosure, a memory is provided, comprising:

[0134] The semiconductor structure as described in any of the above embodiments of this disclosure.

[0135] Figure 7 This is a schematic diagram illustrating the implementation process of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0136] like Figure 7 As shown, according to a third aspect of the present disclosure, a method for fabricating a semiconductor structure is provided, comprising the following steps:

[0137] S701. A plurality of active regions are formed, the plurality of active regions being arranged in an array along intersecting first and second directions and separated by an isolation structure; the first direction is parallel to the direction in which the active regions extend;

[0138] S702, forming a bit line selection structure, including a first gate, a second gate, a third gate, and a fourth gate, all extending along the second direction and located on four adjacent active regions of the plurality of active regions, and at least one connecting line extending along the first direction and located on the isolation structure; one end of the first gate is connected to one end of the second gate, one end of the third gate is connected to one end of the fourth gate, and the connecting line connects the two ends of the first gate and the third gate and / or the two ends of the second gate and the fourth gate respectively;

[0139] S703. A plurality of contact structures are formed, each of the contact structures being located on one side of a gate near the connection line and connected to an active region. The orthographic projection of the contact structure onto the plane of the active region is located in the corresponding active region near the connection line.

[0140] It should be understood that Figure 7 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 7 The steps shown can be adjusted in order according to actual needs.

[0141] In this document and hereinafter, the first direction and the second direction refer to two intersecting directions parallel to the top surface of the active region; the third direction is a direction perpendicular to the plane containing the active region. For example, the first direction is represented by the X direction in the accompanying drawings, the second direction by the Y direction, and the X and Y directions are orthogonal; the third direction is represented by the Z direction in the accompanying drawings.

[0142] Figures 8 to 14b These are top view and cross-sectional structural diagrams illustrating the fabrication process of a semiconductor structure according to an embodiment of this disclosure. It should be noted that... Figure 8 , Figure 9 , Figure 10a , Figure 11 , Figure 12a , Figure 13 , Figure 14a It can be understood as Figure 14b Schematic diagrams of the structure along the BB section at different manufacturing processes. Figure 14b This can be understood as a top-down planar structural diagram of the semiconductor structure fabrication process; Figure 10b It can be understood as Figure 10a A simplified, enlarged diagram of the structure within the area framed by the dashed lines. Figure 12b It can be understood as Figure 14b A simplified structural diagram along the BB section. Figure 12c It can be understood as Figure 14b A simplified, enlarged structural diagram of the area within the dashed box P. The following is a combination of... Figure 7 , Figures 8 to 1 4. The method for preparing the semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0143] Execute step S701, refer to Figure 8 This forms multiple active regions.

[0144] A substrate SUB is provided. The material of the substrate SUB may include silicon, germanium, silicon-germanium substrate, etc.; the material of the substrate SUB may also be silicon-on-insulator or germanium-on-insulator.

[0145] The active layer is formed by incorporating a certain amount of impurity ions into the top layer of the substrate using an ion implantation process. Figure 8 (Not shown). The impurity ions can be N-type or P-type impurity ions; in one embodiment, the doped source / drain regions are doped. Exemplarily, the substrate material includes silicon, and the top of the substrate is heavily N-type doped to form an active layer with heavy N-type doping.

[0146] The plurality of active regions AA are arrayed along a first direction and a second direction using a shallow trench isolation process, and an isolation structure (STI) is located between adjacent active regions. The constituent materials of the isolation structure STI include, but are not limited to, silicon oxide.

[0147] Execute step S702, refer to Figures 9 to 13 This forms the gate.

[0148] refer to Figure 9 A thin-film deposition process is used to form a gate material G' covering the active region and the isolation structure.

[0149] Here and below, thin film deposition processes include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0150] refer to Figure 10a Multiple gates G are formed by etching the gate structure material using a photolithography-etching (LE) process. Each gate G extends along the second direction and is located on the multiple active regions. The first gate, second gate, third gate, and fourth gate located on four adjacent active regions, along with at least one connecting line extending along the first direction and located on the isolation structure, constitute a single gate. The specific layout of this single gate can be referred to above. Figure 6a and Figure 6b Further details will not be elaborated here.

[0151] refer to Figure 10b It can be understood as Figure 10a Enlarged view of the area within the dashed box.

[0152] refer to Figure 10b In some embodiments, a gate dielectric layer 201 is further included between the gate G and the active region. The material of the gate dielectric layer 201 includes, but is not limited to, silicon oxide. The material of the gate G can be a metallic material or a semiconductor conductive material, such as copper, cobalt, nickel, tungsten, molybdenum, doped silicon, polysilicon, or any combination thereof. In some embodiments, a protective dielectric layer 205 is further formed on the gate G to protect the top surface of the gate G. The material of the protective dielectric layer 205 includes, but is not limited to, silicon oxide.

[0153] Continue to refer to Figure 10bIn some embodiments, the gate G comprises a structure of multiple layers of different conductive materials stacked sequentially. In practical applications, the gate G comprises a semiconductor layer 202, an adhesive layer 203, and a metal layer 204 stacked sequentially. Exemplarily, the gate G comprises a polycrystalline silicon layer, a titanium carbide layer, and a tungsten metal layer stacked sequentially.

[0154] refer to Figures 11 to 13 In some embodiments, the method further includes:

[0155] Before forming the sidewall isolation layer, a first protective layer covering each gate is formed;

[0156] After the sidewall isolation layer is formed, a second protective layer is formed to cover the sidewall isolation layer.

[0157] refer to Figure 11 A first protective layer 101 is formed covering the top surface and sidewalls of the gate using a thin-film deposition process. The material of the first protective layer 101 may be silicon nitride, silicon oxynitride, silicon oxide, or any combination thereof. For example, the material of the first protective layer 101 includes silicon nitride.

[0158] Next, using the first protective layer 101 as a mask, the active region AA is lightly doped to serve as a lightly doped drain (LDD). Figure 11 (Not shown in the image). The lightly doped drain described herein includes an N-type ion implantation region.

[0159] refer to Figure 12a , Figure 12a It can be understood as Figure 14b The schematic diagram along the BB cross-section shows a sidewall isolation layer (Spacer) formed using a thin-film deposition process, covering the sidewalls of the first protective layer 101. The material of the sidewall isolation layer (Spacer) can be silicon nitride, silicon oxynitride, silicon oxide, or any combination thereof. For example, the material of the sidewall isolation layer (Spacer) includes silicon oxide.

[0160] Next, using the sidewall isolation layer Spacer and the first protective layer 101 as a mask, the lightly doped active region AA is heavily doped, forming source S and drain D on both sides of the gate G in the active region AA. Here, the source S and drain D include N+ type ion implantation regions.

[0161] Figure 12b It can be understood as Figure 14b A simplified structural diagram along the BB section. Figure 12c It can be understood as Figure 14b A simplified, enlarged structural diagram of the region P within the dashed box. Figure 12b and Figure 12cThe image shows the active region, gate, source, drain, and sidewall isolation layer corresponding to the bit line select line transistor. Other structures, such as bit lines, input / output lines, isolation structures between active regions, and the first protective layer, are not shown.

[0162] Here, in the patterning process, when forming each gate and the sidewall isolation layers on both sides of each gate, due to the diffraction effect of the optical system and the optical proximity correction (OPC), the final shape of each gate and the sidewall isolation layers on both sides of each gate in the corner or rounded corner area is often chamfered or rounded, rather than right-angled.

[0163] In the patterning process, when forming each gate and the sidewall isolation layers on both sides of each gate, the chamfered or rounded-corner partial isolation sidewalls have larger planar dimensions than other partial sidewall isolation layers. Specifically, the dimension W1 of the partial sidewall isolation layer near the connection line along the first direction is larger than the dimension W2 of the partial sidewall isolation layer away from the connection line along the first direction. This results in a high-resistivity region in the active area covered by the chamfered or rounded-corner partial isolation sidewalls, which affects the electrical characteristics of the bit line selection structure.

[0164] Thus, the active region covered by the chamfered or rounded-corner partial isolation sidewalls is blocked, and cannot be completely implanted during subsequent source and drain ion implantation. This results in a high-resistivity region in the active region covered by the chamfered or rounded-corner partial isolation sidewalls, which affects the electrical characteristics of the bit line selection structure and needs to be improved in subsequent process steps (see below). Figure 14a and Figure 14b (Explanation of the formation of multiple contact structures in the middle).

[0165] refer to Figure 13 A second protective layer 102 is formed by using a thin-film deposition process to cover the sidewall of the Spacer sidewall isolation layer. The material of the second protective layer 102 may be silicon nitride, silicon oxynitride, silicon oxide, or any combination thereof. For example, the material of the second protective layer 102 includes silicon nitride.

[0166] Additionally, a filling dielectric layer is formed in the gaps between the second protective layers 102. The filling dielectric layer is made of silicon oxide.

[0167] Execute step S703, refer to Figures 14a to 14b This forms multiple contact structures.

[0168] It should be noted that, Figure 14b This is a top-view planar structural diagram illustrating the semiconductor structure fabrication process. Figure 14b The image shows the active region, gate, interconnects, and contact structure corresponding to the bit line select line transistor. Other structures, such as bit lines, input / output lines, and isolation structures between active regions, are not shown.

[0169] refer to Figures 14a to 14b In some embodiments, the method further includes:

[0170] Sidewall isolation layers are formed on both sides of each gate; the dimension W1 of the sidewall isolation layer near the connection line along the first direction is greater than the dimension W2 of the sidewall isolation layer away from the connection line along the first direction.

[0171] The formation of the plurality of contact structures includes:

[0172] A contact hole is formed that penetrates at least a portion of the sidewall isolation layer on the side closest to the connecting line;

[0173] Ion implantation is performed on the portion of the active region exposed by the contact hole;

[0174] The contact structure is obtained by incorporating conductive material into the contact hole.

[0175] Here, referring to the above Figure 6a and Figure 6b Within the active region, the connecting line CG (or connecting lines CG1, CG2) forms a first, second, third, and fourth included-angle region or rounded-corner region with the first gate G1, the second gate G2, the third gate G3, and the fourth gate G4, respectively.

[0176] In conjunction with the above Figure 12b and Figure 12c The dimension W1 of the sidewall isolation layer near the connecting line along the first direction is greater than the dimension W2 of the sidewall isolation layer away from the connecting line along the first direction. This results in a high-resistance region in the active area covered by the chamfered or rounded-corner isolation sidewalls, which affects the electrical characteristics of the bit line selection structure.

[0177] In this embodiment, a contact hole is formed that penetrates at least a portion of the sidewall isolation layer near the connection line; ion implantation is performed on the portion of the active region exposed by the contact hole; conductive material is then placed in the contact hole to obtain the contact structure. The contact structure penetrates at least a portion of the sidewall isolation layer near the connection line. The formation process of the contact structure exposes the active region partially covered by the chamfered or rounded-corner isolation sidewall, while high-concentration ion implantation is performed to reduce the resistance of this region, thereby obtaining better current characteristics and improving the electrical characteristics of the bit line selection structure.

[0178] The semiconductor structure manufactured by the method of this disclosure is similar to the semiconductor structure in the above embodiments. For technical features not disclosed in detail in this disclosure, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0179] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0180] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0181] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Multiple active regions are arranged in an array along intersecting first and second directions and are separated by an isolation structure. The first direction is parallel to the direction in which the active region extends; The bit line selection structure includes a first gate, a second gate, a third gate, and a fourth gate, all extending along the second direction and located on four adjacent active regions of the plurality of active regions, and at least one connecting line extending along the first direction and located on the isolation structure; one end of the first gate is connected to one end of the second gate, one end of the third gate is connected to one end of the fourth gate, and the connecting line connects the two corresponding ends of the first gate and the third gate and / or the two corresponding ends of the second gate and the fourth gate; Multiple contact structures; each contact structure is located on one side of a gate near the connection line and connected to an active region, wherein the orthographic projection of the contact structure onto the plane of the active region is located in the corresponding active region near the connection line.

2. The semiconductor structure according to claim 1, characterized in that, The four adjacent active regions include a first active region, a second active region, a third active region, and a fourth active region. The first gate is located on the first active region, the second gate is located on the second active region, the third gate is located on the third active region, and the fourth gate is located on the fourth active region. The plurality of contact structures include a first contact structure, a second contact structure, a third contact structure, and a fourth contact structure. The first contact structure is located on one side of the first gate and connected to the first active region. The second contact structure is located on one side of the second gate and connected to the second active region. The third contact structure is located on one side of the third gate and connected to the third active region. The fourth contact structure is located on one side of the fourth gate and connected to the fourth active region.

3. The semiconductor structure according to claim 2, characterized in that, The bit line selection structure includes a connection line that connects the connection ends of the first gate and the second gate and the connection ends of the third gate and the fourth gate. The first contact structure and the third contact structure are both located on one side of the connecting line and close to the connecting line along the second direction, while the second contact structure and the fourth contact structure are both located on the other side of the connecting line and close to the connecting line along the second direction.

4. The semiconductor structure according to claim 3, characterized in that, The bit line selection structure further includes: a bit line selection line contact and a bit line selection line; one end of the bit line selection line contact is connected to the end of the connection between the first gate and the second gate or the end of the connection between the third gate and the fourth gate, and the other end is connected to the bit line selection line.

5. The semiconductor structure according to claim 2, characterized in that, The bit line selection structure includes two connection lines, wherein the first connection line of the two connection lines is connected to the end of the first gate that is not connected to the second gate and the end of the third gate that is not connected to the fourth gate, and the second connection line of the two connection lines is connected to the end of the second gate that is not connected to the first gate and the end of the fourth gate that is not connected to the third gate. The first contact structure and the third contact structure are both located on one side of the first connecting line and close to the first connecting line along the second direction. The second contact structure and the fourth contact structure are both located on one side of the second connecting line and close to the second connecting line along the second direction.

6. The semiconductor structure according to claim 5, characterized in that, The bit line selection structure further includes: a bit line selection line contact structure and a bit line selection line; one end of the bit line selection line contact structure is connected to the middle of the first connecting line or the middle of the second connecting line, and the other end is connected to the bit line selection line.

7. The semiconductor structure according to claim 1, characterized in that, The bit line selection structure further includes: sidewall isolation layers located on both sides of each gate; the portion of the sidewall isolation layer near the connection line has a larger dimension along the first direction than the portion of the sidewall isolation layer away from the connection line; the contact structure at least penetrates the portion of the sidewall isolation layer near the connection line.

8. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes: multiple bit lines; the multiple bit lines are arranged along the first direction, and each bit line is connected to a contact structure; the orthographic projections of the multiple bit lines on the plane where the active region is located are separated from each other.

9. The semiconductor structure according to claim 8, characterized in that, Each bit line includes a body portion extending along the second direction and a protruding portion extending along the first direction, each protruding portion being connected to a contact structure.

10. The semiconductor structure according to claim 1, characterized in that, The bit line selection structure further includes: a first source and a first drain located in each active region and on opposite sides of the corresponding gate, and each of the contact structures is connected to a first source or a first drain on the side closest to the connection line.

11. The semiconductor structure according to claim 10, characterized in that, The semiconductor structure includes: The plurality of bit line selection structures include a first bit line selection structure and a second bit line selection structure arranged along the first direction, wherein the gates connected to the two ends of the first bit line selection structure and the gates connected to the two ends of the second bit line selection structure share two adjacent active regions along the second direction. The two shared active regions are provided with a first source and a first drain corresponding to the two ends of the gate connected to the first bit line selection structure, and a second source and a second drain corresponding to the two ends of the gate connected to the second bit line selection structure; the first source / second source located between the two ends of the gate connected to the first bit line selection structure and the two ends of the gate connected to the second bit line selection structure are shared, or the first drain / second drain is shared.

12. The semiconductor structure according to claim 1, characterized in that, The first direction is perpendicular to the second direction.

13. A memory, characterized in that, include: The semiconductor structure as described in any one of claims 1 to 12.

14. A method for fabricating a semiconductor structure, characterized in that, include: Multiple active regions are formed, and the multiple active regions are arranged in an array along intersecting first and second directions and are separated by an isolation structure; The first direction is parallel to the direction in which the active region extends; A bit line selection structure is formed, including a first gate, a second gate, a third gate, and a fourth gate, all extending along the second direction and located on four adjacent active regions of the plurality of active regions, and at least one connecting line extending along the first direction and located on the isolation structure; one end of the first gate is connected to one end of the second gate, one end of the third gate is connected to one end of the fourth gate, and the connecting line connects the two corresponding ends of the first gate and the third gate and / or the two corresponding ends of the second gate and the fourth gate; Multiple contact structures are formed, each of which is located on one side of a gate near the connection line and connected to an active region. The orthographic projection of the contact structure onto the plane of the active region is located in the corresponding active region near the connection line.

15. The manufacturing method according to claim 14, characterized in that, The method further includes: Sidewall isolation layers are formed on both sides of each gate; the portion of the sidewall isolation layer near the connection line has a larger dimension along the first direction than the portion of the sidewall isolation layer away from the connection line. The formation of the plurality of contact structures includes: A contact hole is formed that penetrates at least a portion of the sidewall isolation layer on the side closest to the connecting line; Ion implantation is performed on the portion of the active region exposed by the contact hole; The contact structure is obtained by incorporating conductive material into the contact hole.

16. The manufacturing method according to claim 15, characterized in that, The method further includes: Before forming the sidewall isolation layer, a first protective layer covering each gate is formed; After the sidewall isolation layer is formed, a second protective layer is formed to cover the sidewall isolation layer.

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