A digital temperature sensor

Abstract

The application provides a digital temperature sensor, which comprises an oscillator, a phase detector and a counter; a voltage-controlled oscillator is connected with the phase detector and the counter respectively, and the phase detector is further connected with the counter; the oscillator is used for receiving an input voltage to generate a clock signal which changes with the input voltage; wherein the input voltage changes with temperature; the phase detector is used for converting the clock signal into a pulse signal after detecting that the clock signal generated by the voltage-controlled oscillator reaches a preset frequency; the counter is used for counting the frequency of the clock signal output by the voltage-controlled oscillator when detecting that the level state of the pulse signal is a first preset level, and outputting a data code value corresponding to the count value; and the data code value is used for representing a temperature value. The application can reduce the device area and lower the device power consumption.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a digital temperature sensor. BACKGROUND

[0002] With the vigorous development of microprocessors, more and more microprocessors are developing towards miniaturization, low cost, low power consumption and high integration. At present, some microprocessors integrated with temperature sensors appear in the prior art. Usually, this temperature sensor is integrated in an analog-to-digital converter (ADC), so as to detect the temperature by using the analog-to-digital converter to detect a bandgap voltage proportional to the absolute temperature in the voltage domain.

[0003] However, in the process of research and practice of the prior art, the inventors of the present application found that although the temperature sensor integrated in the analog-to-digital converter has the advantages of high precision, good linearity, wide temperature measurement range and low voltage sensitivity, it has the disadvantages of large area and high power consumption because it needs to use the analog-to-digital converter to detect the temperature.

[0004] The foregoing narrative is to provide general background information and does not necessarily constitute the prior art. SUMMARY

[0005] In view of the above technical problems, the present application provides a digital temperature sensor which can reduce the device area and reduce the device power consumption.

[0006] The present application provides a digital temperature sensor, comprising an oscillator, a phase detector and a counter; the oscillator is connected with the phase detector and the counter respectively, and the phase detector is further connected with the counter;

[0007] The oscillator is configured to receive an input voltage to generate a clock signal varying with the input voltage; wherein the input voltage varies with temperature;

[0008] The phase detector is configured to convert the clock signal generated by the oscillator into a pulse signal after detecting that the clock signal reaches a preset frequency;

[0009] The counter is configured to count the frequency of the clock signal output by the oscillator when detecting that the level state of the pulse signal is a first preset level, and output a data encoding value corresponding to the count value; the data encoding value is used to represent a temperature value.

[0010] Optionally, the digital temperature sensor further comprises an input circuit, and the input circuit comprises a charge-discharge capacitor, which is configured to sample the input voltage and output a sampled voltage to the oscillator.

[0011] Optionally, the input circuit further comprises a switch unit, configured to control the accumulated charge amount of the charging and discharging capacitor when charging to the first preset level, and control the oscillator to discharge the charging and discharging capacitor.

[0012] Optionally, the phase detector is further configured to switch the level state of the pulse signal to a second preset level and stop the counting of the counter after the charging and discharging capacitor is discharged.

[0013] Optionally, the digital temperature sensor further comprises a logic control unit, connected with the oscillator, phase detector, counter and switch unit respectively, configured to control the switching state of the switch unit, and control the enable switching state of the oscillator, phase detector and counter.

[0014] Optionally, the digital temperature sensor further comprises a delay unit, connected with the oscillator, phase detector and counter respectively;

[0015] The delay unit is configured to receive the clock signal output by the oscillator, and output the clock signal to the phase detector after converting the clock signal into a delay clock signal.

[0016] The phase detector is further configured to compare the clock signal and the delay clock signal, and output a corresponding pulse signal according to the comparison result.

[0017] Optionally, the delay unit is further configured to output the delay clock signal to the counter, the phase detector is further configured to output the pulse signal to the counter, and the counter is further configured to count the frequency of the delay clock signal when the level state of the pulse signal is the first preset level, and output a corresponding data encoding value according to the count value.

[0018] Optionally, the oscillator comprises a plurality of inverters connected in series, wherein the output terminal of the last inverter is connected with the input terminal of the first inverter, and the supply voltage of each inverter is the input voltage.

[0019] Optionally, the logic control unit comprises a voltage comparator, a latch, an XOR gate and a NOT gate connected in sequence.

[0020] The voltage comparator is configured to output a signal of the first preset level when monitoring the input voltage reaching a reference voltage during the sampling process of the charging and discharging capacitor, and output the input voltage to the latch.

[0021] The latch is configured to output the signal of the first preset level after receiving the input voltage and the pulse signal.

[0022] The exclusive OR gate is configured to compare the level state of the received reference voltage and the output signal of the latch, and output a first enable signal of a first preset level or a second preset level according to a comparison result;

[0023] The NOT gate is configured to convert the first enable signal into a second enable signal, and the first enable signal and the second enable signal are configured to control the state of the switch unit.

[0024] Optionally, the frequency of the clock signal output by the oscillator is counted, and a data encoding value corresponding to a count value is output.

[0025] The pulse width of the pulse signal is detected, and a corresponding count duration is determined;

[0026] The frequency of the clock signal is counted according to the count duration, and a corresponding count value is obtained.

[0027] The data encoding value corresponding to the count value is determined.

[0028] The embodiments of the present application have the following beneficial effects:

[0029] As described above, the digital temperature sensor provided by the present application comprises an oscillator, a phase detector and a counter. The oscillator is connected with the phase detector and the counter respectively, and the phase detector is further connected with the counter. The oscillator is configured to receive an input voltage to generate a clock signal varying with the input voltage. The phase detector is configured to convert the clock signal into a pulse signal after detecting that the clock signal generated by the oscillator reaches a preset frequency. The counter is configured to count the frequency of the clock signal output by the oscillator when detecting that the level state of the pulse signal is a first preset level, and output a data encoding value corresponding to a count value. The data encoding value is used to represent a temperature value. Compared with the conventional temperature sensor, the present application can achieve the effect of detecting temperature without additionally increasing an analog-to-digital converter with a large area and high power consumption. Thus, the device area of the digital temperature sensor can be reduced, and the overall power consumption can be lowered. Therefore, the present application can reduce the device area and lower the device power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0030] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and serve to explain the principles of the present application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced as follows. Obviously, those drawings can also provide other drawings for those skilled in the art without any creative effort.

[0031] Figure 1is a structural schematic diagram of a first embodiment of a digital temperature sensor provided by the embodiment of the present application;

[0032] Figure 2 is a structural schematic diagram of a second embodiment of a digital temperature sensor provided by the embodiment of the present application;

[0033] Figure 3 is a structural schematic diagram of a logic control unit provided by the embodiment of the present application;

[0034] Figure 4 is a structural schematic diagram of a third embodiment of a digital temperature sensor provided by the embodiment of the present application;

[0035] Figure 5 is a structural schematic diagram of a voltage-controlled oscillator provided by the embodiment of the present application;

[0036] Figure 6 is a flowchart of temperature measurement provided by the embodiment of the present application.

[0037] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. The above-described drawings have shown the specific embodiments of the present application, and more detailed description will be given hereinafter. These drawings and the written description are not intended to limit the scope of the present application concept in any way, but to illustrate the present application concept to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0038] The exemplary embodiments will be described in detail herein with reference to the accompanying drawings. The following description is presented with reference to the drawings, wherein the same reference numerals are used to refer to like or similar elements throughout the several views. The embodiments described in the following exemplary embodiments are not meant to represent all implementations in accordance with the present application. Rather, they are merely examples of apparatus and methods in accordance with some aspects of the present application as detailed in the appended claims.

[0039] It should be noted that, in this document, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, so that a process, method, article, or apparatus that comprises a list of elements does not include only those elements, but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element. Furthermore, components, features, elements with the same name in different embodiments of the present application can have the same meaning or different meanings, and the specific meaning thereof should be determined in the light of its explanation in the specific embodiment or further in conjunction with the context in the specific embodiment.

[0040] It should be understood that, although the terms first, second, third, etc. can be used herein to describe various information, the information should not be limited to these terms. These terms are only used to distinguish one category of information from another category of information. For example, a first information can also be termed a second information, similarly, a second information can also be termed a first information without departing from the scope of this document. As used herein, the word "if' can be interpreted to mean "when" or "upon" or "in response to a determination" depending on the context. Also, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", when used herein, specify the presence of stated features, steps, operations, elements, components, items, and / or groups but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, items, and / or groups thereof. As used herein, the term "or", "and / or", "at least one of", and the like as used herein can be interpreted to be inclusive, i.e., the selection can be

[0041] It should be understood that, although the steps in the flowcharts of the embodiments of the present application are shown in a sequence following the arrows, the steps are not necessarily executed in the order following the arrows. Unless otherwise specified herein, the execution of the steps is not limited to a strict sequence, and the steps can be executed in other sequences. Moreover, at least a part of the steps in the flowcharts can include a plurality of sub-steps or a plurality of stages, and the sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution sequence is not necessarily sequential, but can be executed in rotation or alternation with at least a part of other steps or sub-steps or stages of other steps.

[0042] As used herein, the word "if' can be interpreted to mean "when" or "upon" or "in response to a determination" or "in response to detecting", depending on the context. Similarly, as used herein, the phrase "if determined" or "if detecting (a stated condition or event)" can be interpreted to mean "when determined" or "in response to a determination" or "when detecting (a stated condition or event)" or "in response to detecting (a stated condition or event)".

[0043] It is to be understood that the specific embodiments described herein are merely illustrative of the application and do not limit the scope of the application.

[0044] In the following description, suffixes for elements such as "module", "part", or "unit" are used only to facilitate explanation of the application, and have no particular meaning by themselves. Thus, "module", "part", or "unit" can be mixedly used.

[0045] At present, some microprocessors integrated with temperature sensors appear in the prior art, and the temperature sensor is usually integrated in an analog-to-digital converter (ADC), so as to detect temperature by using the analog-to-digital converter to detect a bandgap voltage proportional to absolute temperature in a voltage domain. Although the temperature sensor integrated in the analog-to-digital converter has advantages of high precision, good linearity, wide temperature measurement range, and low voltage sensitivity, since the analog-to-digital converter needs to be used to detect temperature, the temperature sensor has disadvantages of large area and high power consumption.

[0046] In order to solve the above problems, the application provides a digital temperature sensor, which can reduce device area and reduce device power consumption.

[0047] Please refer to Figure 1 , Figure 1 is a structural schematic diagram of a first embodiment of the digital temperature sensor provided by the application. The digital temperature sensor comprises a voltage-controlled oscillator 10, a phase detector 20, and a counter 30; the voltage-controlled oscillator 10 is connected with the phase detector 20 and the counter 30 respectively, and the phase detector 20 is further connected with the counter 30.

[0048] The voltage-controlled oscillator 10 is configured to receive an input voltage to generate a clock signal varying with the input voltage; wherein the input voltage varies with temperature.

[0049] The phase detector 20 is configured to convert the clock signal into a pulse signal after detecting that the clock signal generated by the voltage-controlled oscillator reaches a preset frequency.

[0050] The counter 30 is configured to count the frequency of the clock signal output by the voltage-controlled oscillator when the level state of the pulse signal is a first preset level, and output a data encoding value corresponding to the count value; the data encoding value is used to represent a temperature value.

[0051] Specifically, in the embodiment, the digital temperature sensor comprises the voltage-controlled oscillator 10, the phase detector 20, and the counter 30, wherein a first end of the voltage-controlled oscillator 10 is configured to receive an input voltage to generate a clock signal CLK varying with the input voltage Vctrl, the input voltage Vctrl varies with temperature, and thus the frequency of the clock signal CLK varies.

[0052] The first end of the phase detector 20 is connected to the second end of the voltage-controlled oscillator 10 in an electrical signal manner, and the phase detector 20 is configured to output the clock signal CLK reaching a preset frequency as a pulse signal, that is, the phase detector 20 detects whether the clock signal CLK generated by the voltage-controlled oscillator 10 reaches the preset frequency, and if so, converts the clock signal CLK into a pulse signal (Trigger signal). The preset frequency is mainly set based on the accuracy of the digital temperature sensor.

[0053] The first end of the counter 30 is connected to the second end of the voltage-controlled oscillator 10, and the second end of the counter 30 is connected to the second end of the phase detector 20. When the counter 30 detects that the pulse signal output by the phase detector 20 is a first preset level (for example, a high level), the counter 30 starts to count the frequency of the clock signal CLK output by the voltage-controlled oscillator 10, that is, calculates the number of square waves of the clock signal, so as to output a corresponding data encoding value Dout according to the count value, until the pulse signal is not the first preset level (the level is pulled low), and different data encoding values Dout represent different temperature values detected.

[0054] As can be seen, the digital temperature sensor in the embodiment only needs to pass through the voltage-controlled oscillator 10, the phase detector 20 and the counter 30 to achieve the effect of detecting temperature. Compared with the conventional temperature sensor which needs to detect temperature by using an analog-to-digital converter, the embodiment does not need to increase the analog-to-digital converter which has a large area and high power consumption, so that the device area of the digital temperature sensor can be reduced, and the overall power consumption can be reduced. Therefore, the application can reduce the device area and reduce the device power consumption.

[0055] Optionally, in some embodiments, the digital temperature sensor can further include an input circuit connected to the first end of the voltage-controlled oscillator 10, and the input voltage Vctrl is output to the voltage-controlled oscillator 10 through the input circuit. The input circuit includes a charge-discharge capacitor C1, and the input voltage Vctrl is sampled through the charge-discharge capacitor C1 and output to the voltage-controlled oscillator 10.

[0056] In specific embodiments, the input circuit includes a charging and discharging capacitor C1, and the charging and discharging capacitor C1 needs to accumulate a preset amount of charge required for charging to a first preset level, wherein the preset amount of charge is determined according to the subsequent discharging requirement of the charging and discharging capacitor C1. The discharging of the charging and discharging capacitor C1 is realized by a voltage-controlled oscillator 10. During the discharging of the charging and discharging capacitor C1, the frequency of the clock signal CLK output by the voltage-controlled oscillator 10 decreases with the decrease of the input voltage Vctrl. The clock signal CLK output by the voltage-controlled oscillator 10 is input to a phase detector 20 and a counter 30. When the clock signal CLK reaches a preset frequency, the phase detector 30 outputs the clock signal CLK as a pulse signal and outputs the pulse signal to the counter 30. When the pulse signal is at a high level, the counter 30 starts counting the frequency of the clock signal CLK output by the voltage-controlled oscillator 10 and outputs a final data code Dout, and stops working until the pulse signal becomes a low level.

[0057] Optionally, in some embodiments, the input circuit specifically further includes a switching unit for controlling the accumulation of the amount of charge required for charging the charging and discharging capacitor C1 to the first preset level, and controlling the discharging of the charging and discharging capacitor C1 by the voltage-controlled oscillator 10.

[0058] Specifically, the input circuit further includes a switching unit connected to the charging and discharging capacitor C1, and the switching unit includes a first switch S1 and a second switch S2. The first end of the first switch S1 is connected to the input voltage, and the second end of the first switch S1 and the first end of the second switch S2 are connected to one end of the charging and discharging capacitor C1. The second end of the second switch S2 is connected to one end of the voltage-controlled oscillator 10. The switching unit controls the accumulation of the amount of charge required for charging the charging and discharging capacitor C1 to the first preset level by the first switch S1 and the second switch S2, and controls the discharging of the charging and discharging capacitor C1 by the voltage-controlled oscillator 10.

[0059] Optionally, in some embodiments, the phase detector 20 is specifically further used for switching the level state of the pulse signal to a second preset level after the discharging of the charging and discharging capacitor C1 is completed, and stopping the counting of the counter 30.

[0060] Specifically, the phase detector 20 in the present embodiment is further used for switching the level state of the pulse signal to a second preset level (such as a low level) after the voltage-controlled oscillator 10 controls the discharging of the charging and discharging capacitor C1 to be completed, and stopping the counting of the counter 30.

[0061] Optionally, as Figure 2As shown, in some embodiments, the digital temperature sensor can further comprise a logic control unit 40 connected with the voltage-controlled oscillator 10, the phase detector 20, the counter 30 and the switch unit respectively, for controlling the switch states of the switch unit, and for controlling the enable switch states of the voltage-controlled oscillator 10, the phase detector 20 and the counter 30.

[0062] Specifically, in the present embodiment, the digital temperature sensor further comprises a logic control unit 40 connected with the voltage-controlled oscillator 10, the phase detector 20, the counter 30 and the switch unit respectively, for controlling the switch states of the first switch S1 and the second switch S2 of the switch unit, and for controlling the enable switch states of the voltage-controlled oscillator 10, the phase detector 20 and the counter 30. In a specific implementation process, the first switch S1 is controlled to be closed and the second switch S2 is controlled to be opened by the logic control unit 40, at which time the charging of the charge-discharge capacitor C1 starts and the accumulated charge amount required for charging to the first preset level; then the first switch S1 is controlled to be opened and the second switch S2 is controlled to be closed by the logic control unit 40, so as to realize the discharging of the charge-discharge capacitor C1 by the voltage-controlled oscillator 10. In the process of discharging the charge-discharge capacitor C1, the clock signal CLK output by the voltage-controlled oscillator 10 will decrease with the decrease of the input voltage Vctrl. The clock signal output by the voltage-controlled oscillator 10 will be input to the phase detector 20 and the counter 30. When the phase detector 20 detects that the frequency of the clock signal reaches a preset frequency, the clock signal will be output as a pulse signal; when the counter 30 detects that the pulse signal is at a first preset level (such as high level), the counter 30 starts to count the frequency of the clock signal CLK output by the voltage-controlled oscillator 10, and outputs the final data code Dout by the counter 30, until the pulse signal is no longer at the first preset level, such as the pulse signal becomes low level, at which time the counter 30 stops working.

[0063] Optionally, as shown in FIG. 4, in some embodiments, the logic control unit 40 can specifically comprise a voltage comparator, a latch, an XOR gate and a NOT gate connected in sequence; Figure 3

[0064] The voltage comparator is used to output a signal at a first preset level when monitoring that the input voltage during the sampling process of the charge-discharge capacitor C1 reaches a reference voltage, and output the input voltage to the latch;

[0065] The latch is used to output a signal at a first preset level after receiving the input voltage and the pulse signal;

[0066] The XOR gate is used to compare the level states of the received reference voltage and the output signal of the latch, and output a first enable signal at a first preset level or a second preset level according to the comparison result;

[0067] ​The NOT gate is used to convert the first enable signal into a second enable signal. The first enable signal and the second enable signal are used to control the state of the switching unit.

[0068] In a specific embodiment, the logic control unit 40 includes a voltage comparator, a latch, an XOR gate, and a NOT gate, which are electrically connected in sequence. The latch is preferably an SR latch. The voltage comparator is electrically connected to the charging / discharging capacitor C1 and is used to monitor the input voltage during the sampling process of the charging / discharging capacitor C1. Figure 3 Whether the Track voltage in the signal reaches the reference voltage Vref, during the capacitor sampling phase, the pulse signal ( Figure 3 The Trigger signal in the logic control unit 40 is low, and the XOR gate output in the logic control unit 40 is low. The EN signal and the enable signal control the first switch S1 to close and the second switch S2 to open, thereby controlling the charging and discharging capacitor C1 to charge to the preset value of the reference voltage. If the voltage comparator detects that the input voltage of the charging and discharging capacitor C1 reaches the reference voltage Vref during the sampling process, it outputs a high-level signal, which is input to the input terminal of the next stage latch. Figure 3 The XOR gate (S-terminal) is used to pull the latch's output level high; the XOR gate compares the reference voltage Vref with the latch's output level, detecting whether both signals are simultaneously high. When the latch output is high, the XOR gate's output level is pulled low. The signal is a low-level signal, and the EN signal is pulled high through a NOT gate, thereby according to The signal and the EN signal respectively control the first switch S1 to open and the second switch S2 to close. The voltage-controlled oscillator 10 discharges the charging and discharging capacitor C1. At the same time, the phase detector 20 and the counter 30 start working. After the charging and discharging capacitor C1 is discharged, the phase detector 20 pulls down the level of the pulse signal and outputs the Dout signal, thus completing one temperature measurement.

[0069] For example Figure 4 As shown, during the discharge process of capacitor C1, the frequency of the clock signal CLK output by voltage-controlled oscillator 10 decreases as the input voltage Vctrl decreases. The clock signal CLK output by voltage-controlled oscillator 10 is input to phase detector 20 and delay unit 50. Phase detector 20 compares the clock signal CLK output by voltage-controlled oscillator 10 with the delayed clock signal CLK_DLY output by delay unit 50. When these two clock signals coincide, phase detector 20 outputs a pulse signal. Figure 4When the pulse signal is at high level, the counter 30 starts to count the frequency of the clock signal output by the voltage-controlled oscillator 10 until the pulse signal becomes at low level, when the pulse signal is at low level, the counter 30 stops counting, the delay clock signal CLK_DLY output by the delay unit 50 and the pulse signal output by the phase detector 20 are simultaneously input to the counter 30, the pulse width of the pulse signal is calculated, so as to determine the working duration of the counter 30 according to the pulse width, the counter 30 counts the frequency of the delay clock signal within the working duration, so as to output the corresponding data encoding value Dout according to the count value, and different data encoding values Dout are used to represent different temperature values.

[0070] The latch can also be other suitable latch in addition to the SR latch described in the above embodiment.

[0071] Optionally, as shown in some embodiments, the digital temperature sensor can further include a delay unit 50, which is connected with the voltage-controlled oscillator 10, the phase detector 20 and the counter 30 respectively. Figure 4

[0072] The delay unit 50 is configured to receive the clock signal output by the voltage-controlled oscillator 10 and convert the clock signal into a delay clock signal and output the delay clock signal to the phase detector 20.

[0073] The phase detector 20 is further configured to compare the clock signal and the delay clock signal and output a corresponding pulse signal according to the comparison result.

[0074] Optionally, in some embodiments, the delay unit 50 can be further configured to output the delay clock signal to the counter 30, and the phase detector 20 can be further configured to output the pulse signal to the counter 30, and the counter 30 can be further configured to count the frequency of the delay clock signal when the level state of the pulse signal is at the first preset level and output a corresponding data encoding value according to the count value.

[0075] Specifically, in the embodiment, the digital temperature sensor further includes a delay unit 50 connected with the voltage-controlled oscillator 10, the phase detector 20 and the counter 30 respectively, the delay unit 50 is configured to convert the clock signal output by the voltage-controlled oscillator 10 into a delay clock signal and output the delay clock signal to the phase detector 20 and the counter 30. The clock signal output by the voltage-controlled oscillator 10 is first output to the phase detector 20 and the delay unit 50, the phase detector 20 compares the clock signal CLK output by the voltage-controlled oscillator 10 and the delay clock signal CLK_DLY output by the delay unit 50, when the clock signal CLK and the delay clock signal CLK_DLY coincide, the phase detector 20 outputs a trigger signal (the trigger signal is also called a pulse signal in the present embodiment). Figure 4 ​The trigger signal is a pulse signal. When the trigger signal (i.e. the pulse signal) is at a first preset level, the counter 30 starts counting the frequency of the clock signal output by the voltage-controlled oscillator 10 until the pulse signal becomes low, i.e. no longer maintains the first preset level, and the counter 30 stops counting. The delay clock signal output by the delay unit 50 and the pulse signal output by the phase detector 20 are simultaneously input to the counter 30. When the level of the pulse signal is the first preset level, the pulse width of the pulse signal is calculated, so that the working duration of the counter 30 is determined according to the pulse width. The counter 30 counts the frequency of the delay clock signal within the working duration, so as to output a corresponding data encoding value Dout according to the count value. The data encoding value Dout output under different temperature conditions also corresponds to a difference.

[0076] In the specific implementation process, when the input voltage Vctrl is introduced to the voltage-controlled oscillator 10 through an input circuit connected to the voltage-controlled oscillator 10, the input circuit has a charge-discharge capacitor C1, and the input voltage Vctrl is sampled through the charge-discharge capacitor C1, the charge-discharge capacitor C1 starts charging until the accumulated charge amount of the first preset level reaches a preset value, wherein the preset value is subject to the subsequent discharge requirement of the charge-discharge capacitor C1. The voltage-controlled oscillator 10 discharges the charge-discharge capacitor C1, and the frequency of the clock signal CLK output by the voltage-controlled oscillator 10 decreases with the decrease of the input voltage Vctrl. The clock signal CLK output by the voltage-controlled oscillator 10 is input to the phase detector 20 and the delay unit 50. The phase detector 20 compares the output clock signal CLK of the voltage-controlled oscillator 10 and the delay clock signal CLK_DLY output by the delay unit 50, and outputs a trigger signal when the two clocks coincide. The trigger signal is a pulse signal. When the pulse signal is at a high level, the counter 30 starts counting the frequency of the clock signal output by the voltage-controlled oscillator 10, and stops counting when the pulse signal becomes low. The delay clock signal CLK_DLY output by the delay unit 50 and the pulse signal output by the phase detector 20 are simultaneously input to the counter 30. The pulse width of the pulse signal is calculated, so that the working duration of the counter 30 is determined according to the pulse width. The counter 30 counts the frequency of the delay clock signal within the working duration, so as to output a corresponding data encoding value Dout according to the count value.

[0077] In addition, when the input circuit has a first switch S1 and a second switch S2, when the first switch S1 is closed and the second switch S2 is opened, the charge-discharge capacitor C1 is charged to the accumulated charge amount of the first preset level. When the first switch S1 is opened and the second switch S2 is closed, the discharge of the charge-discharge capacitor C1 is controlled by the voltage-controlled oscillator 10.

[0078] When the digital temperature sensor further comprises a logic control unit 40 connected with the voltage-controlled oscillator 10, the phase detector 20, the counter 30, the delay unit 50 and the switch unit respectively, the logic control unit 40 controls the open and close states of the first switch S1 and the second switch S2 in the switch unit, and controls the enable switches of other modules. When the first switch S1 is controlled to be closed and the second switch S2 is controlled to be opened by the logic control unit 40, the charge amount accumulated on the charging and discharging capacitor C1 when the charging and discharging capacitor C1 is charged to the first preset level reaches the preset value. Then, the logic control unit 40 controls the first switch S1 to be opened and the second switch S2 to be closed, and the discharging of the charging and discharging capacitor C1 is realized by the voltage-controlled oscillator 10. During the discharging of the charging and discharging capacitor C1, the frequency of the clock signal CLK output by the voltage-controlled oscillator 10 decreases with the decrease of the input voltage Vctrl. The clock signal output by the voltage-controlled oscillator 10 is input into the phase detector 20 and the delay unit 50. The phase detector 20 compares the output clock signal CLK of the voltage-controlled oscillator 10 with the delay clock signal CLK_DLY output by the delay unit 50, and outputs a trigger signal (pulse signal) when the two clock signals coincide. When the pulse signal is at a high level, the counter 30 starts counting the frequency of the clock signal output by the voltage-controlled oscillator 10, and stops counting when the pulse signal is at a low level. The delay clock signal CLK_DLY output by the delay unit 50 and the pulse signal output by the phase detector 20 are simultaneously input into the counter 30. The working duration of the counter 30 is determined according to the pulse width of the signals, and the counter 30 counts the frequency of the delay clock signal within the working duration, so as to output a corresponding data encoding value Dout according to the count value.

[0079] Optionally, in some embodiments, the voltage-controlled oscillator 10 can specifically comprise a plurality of inverters connected in series, wherein the output end of the last inverter is connected with the input end of the first inverter, and the power supply voltage of each inverter is the input voltage Vref. For example, as shown in FIG. 3, the voltage-controlled oscillator in the embodiment adopts a three-level standard inverter. Figure 5 As shown in FIG. 3, the voltage-controlled oscillator in the embodiment adopts a three-level standard inverter. Since the voltage-controlled oscillator 10 in the embodiment does not additionally use a power supply, but directly uses the sampled charging and discharging capacitor C1, the previously sampled charge can be effectively reused, the overall power consumption of the temperature sensor can be effectively further reduced, and the frequency change caused by the change of the power supply voltage can be effectively avoided, so that the inaccuracy of temperature detection caused by the inaccuracy of frequency counting can be avoided.

[0080] The voltage-controlled oscillator 10 can also be other suitable voltage-controlled oscillators in addition to the above configuration. It can be understood that, in addition to the voltage-controlled oscillator 10, the digital temperature sensor in each of the above embodiments can also use a ring oscillator instead of the voltage-controlled oscillator 10, and of course, other oscillators can also be selected.

[0081] Optionally, in some embodiments, the step of counting the frequency of the clock signal output by the voltage-controlled oscillator 10 and outputting the data encoding value corresponding to the count value can specifically include:

[0082] detecting the pulse width of the pulse signal to determine the corresponding counting duration;

[0083] counting the frequency of the clock signal according to the counting duration to obtain the corresponding count value;

[0084] determining the corresponding data encoding value according to the count value.

[0085] Specifically, for the counter 30, first, the pulse width of the pulse signal output by the phase detector 20 is detected, so as to determine the counting duration of the counter 30 according to the pulse width. The counter 30 counts the frequency of the clock signal output by the voltage-controlled oscillator 10 within the counting duration. The counting manner is mainly to count the number of square waves of the clock signal. The number of square waves is related to the frequency of the clock signal. The corresponding count value is obtained. Based on a preset encoding rule, such as binary encoding, the count value is converted into a corresponding binary data encoding value, so as to represent different temperature values through the data encoding value.

[0086] As shown in FIG. 4, the counter 30 is connected to the phase detector 20 and the voltage-controlled oscillator 10. Figure 6 Figure 6 ​The application provides a temperature measurement method, comprising the following steps: during charging of a charge-discharge capacitor C1, judging whether a sampled input voltage is equal to a reference voltage; if yes, starting counting when the charge-discharge capacitor C1 starts discharging; if no, the charge-discharge capacitor C1 continues charging; judging whether a pulse signal is at a high level; if yes, outputting a data code value corresponding to the counting value, and the charge-discharge capacitor C1 continues charging; if no, the charge-discharge capacitor C1 continues discharging, and the counter continues counting until the pulse signal is at the high level. The temperature measurement method is executed on the digital temperature sensor, an input voltage is received by a voltage-controlled oscillator 10 to generate a clock signal varying with the input voltage; the clock signal generated by the voltage-controlled oscillator 10 is converted into a pulse signal by a phase detector 20 after the clock signal reaches a preset frequency; finally, when the level state of the pulse signal is at a first preset level, the frequency of the clock signal output by the voltage-controlled oscillator 10 is counted by a counter 30, and a data code value corresponding to the counting value is output; the data code value is used to represent a temperature value. In each conversion process, the charge amount of the charge-discharge capacitor C1 is fixed during each charging, and after the charge amount accumulated by the charge-discharge capacitor C1 when charged to the reference voltage reaches a preset value, the charge-discharge capacitor C1 starts discharging through the subsequent voltage-controlled oscillator 10, and the data code value Dout is output by the counter 30. When the temperature changes, the frequency of the voltage-controlled oscillator 10 changes, which causes the discharging time of the charge-discharge capacitor C1 to be different, thereby affecting the pulse width of the pulse signal, and the working time of the counter 30 is changed, thereby causing the counting number of the counter 30 to change, so that different data code values are output under different temperature conditions, and the temperature detection can be completed without using an analog-digital converter.

[0087] The above merely illustrates the embodiments of the application, and does not limit the patent scope of the application. Any equivalent structure or equivalent flow transformation made by using the content of the specification and drawings, such as the mutual combination of technical features among the embodiments, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the application.

[0088] In addition, the same or different reference signs can be used to identify structural elements with the same or similar properties in the application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first" and "second" can explicitly or implicitly include one or more features. In the description of the application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0089] In this application, the word "for example" is used to mean "used as an example, illustration, or explanation." Any embodiment described as "for example" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to make and use it. Various details are set forth in the above description for purposes of explanation.

[0090] It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A digital temperature sensor, characterized in that, It includes an oscillator, a phase detector, and a counter; the oscillator is connected to the phase detector and the counter respectively, and the phase detector is also connected to the counter; The oscillator is used to receive an input voltage to generate a clock signal that varies with the input voltage; wherein the input voltage varies with temperature. The phase detector is used to convert the clock signal generated by the oscillator into a pulse signal after detecting that the clock signal reaches a preset frequency. The counter is used to count the frequency of the clock signal output by the oscillator when the level of the detected pulse signal is a first preset level, and output the data encoding value corresponding to the count value; the data encoding value is used to characterize the temperature value. The digital temperature sensor further includes an input circuit, which includes a charging / discharging capacitor and a switching unit. The charging / discharging capacitor is used to sample the input voltage and output the sampled voltage to the oscillator. The switching unit is used to control the amount of charge accumulated by the charging / discharging capacitor to the first preset level and to control the oscillator to discharge the charging / discharging capacitor.

2. The digital temperature sensor according to claim 1, characterized in that, The phase detector is also used to switch the level of the pulse signal to a second preset level and stop the counter after the charging and discharging capacitor has finished discharging.

3. The digital temperature sensor according to claim 2, characterized in that, It also includes a logic control unit, which is connected to the oscillator, phase detector, counter and switch unit respectively, and is used to control the switching state of the switch unit and the enable switching state of the oscillator, phase detector and counter.

4. The digital temperature sensor according to any one of claims 1 to 3, characterized in that, It also includes a delay unit, which is connected to the oscillator, phase detector and counter respectively; The delay unit is used to receive the clock signal output by the oscillator, convert the clock signal into a delayed clock signal, and then output it to the phase detector. The phase detector is also used to compare the clock signal and the delayed clock signal, and output the corresponding pulse signal according to the comparison result.

5. The digital temperature sensor according to claim 4, characterized in that, The delay unit is further configured to output the delayed clock signal to the counter, the phase detector is further configured to output the pulse signal to the counter, and the counter is further configured to count the frequency of the delayed clock signal when the level of the pulse signal is the first preset level, and output the corresponding data encoding value according to the count value.

6. The digital temperature sensor according to claim 1, characterized in that, The oscillator includes multiple inverters connected in series, wherein the output of the last inverter is connected to the input of the first inverter, and the power supply voltage for each inverter is the input voltage.

7. The digital temperature sensor according to claim 3, characterized in that, The logic control unit includes a voltage comparator, a latch, an XOR gate, and a NOT gate, which are connected in sequence. The voltage comparator is used to output a signal with a first preset level when the input voltage during the sampling process of the charging and discharging capacitor reaches the reference voltage, and output the input voltage to the latch. The latch is used to output a signal with the first preset level after receiving the input voltage and pulse signal; The XOR gate is used to compare the received reference voltage and the level state of the output signal of the latch, and output a first enable signal of a first preset level or a second preset level according to the comparison result; The NOT gate is used to convert the first enable signal into a second enable signal, and the first and second enable signals are used to control the state of the switching unit.

8. The digital temperature sensor according to claim 1, characterized in that, The step of counting the frequency of the clock signal output by the oscillator and outputting the data encoding value corresponding to the count value includes: The pulse width of the pulse signal is detected to determine the corresponding counting duration; The frequency of the clock signal is counted according to the counting duration to obtain the corresponding count value; The corresponding data encoding value is determined based on the count value.

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