configurable capacitance

Abstract

A capacitor device includes a semiconductor substrate; a capacitor disposed on the semiconductor substrate including first and second positive terminals and first and second negative terminals; a passivation layer formed on the capacitor, the first and second positive terminals, and the first and second negative terminals, the passivation layer defining first and second openings on the first and second positive terminals, respectively, a third opening on the first negative terminal, and a fourth opening on the second negative terminal; a first metal bump disposed on the passivation layer including a first extension portion extending through each of the first and second openings electrically coupling the first and second positive terminals; a second metal bump disposed on the passivation layer including a second extension portion extending through each of the third and fourth openings electrically coupling the first and second negative terminals.

Description

BACKGROUND

[0001] The materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by virtue of their inclusion in this section.

[0002] Switching DC / DC regulators and other electronic circuits use decoupling capacitors to reduce voltage ripple and noise on input and output voltage lines. Miniaturization and integration of electronic circuit elements have resulted in a need for multiple high-density, small-area capacitors. One approach is to stack multiple discrete capacitors on a printed circuit board or integrated circuit package. Due to the limited spacing of discrete capacitors, this approach can result in poor overall capacitor performance, large circuit footprint, and wasted board space between capacitors. SUMMARY

[0003] Various aspects of the present disclosure relate to capacitors, and more particularly, although not necessarily exclusively, to configurable capacitors in integrated packages.

[0004] According to aspects, a capacitor apparatus is provided. In some aspects, the capacitor apparatus can include a semiconductor substrate; a capacitor disposed on the semiconductor substrate including first and second positive terminals and first and second negative terminals; a passivation layer formed on the capacitor, the first and second positive terminals, and the first and second negative terminals, the passivation layer defining a first opening on the first positive terminal, a second opening on the second positive terminal, a third opening on the first negative terminal, and a fourth opening on the second negative terminal; a first metal bump disposed on the passivation layer including a first extension portion extending through each of the first and second openings electrically coupling the first positive terminal to the second positive terminal; and a second metal bump disposed on the passivation layer including a second extension portion extending through each of the third and fourth openings electrically coupling the first negative terminal to the second negative terminal.

[0005] According to aspects, an apparatus is provided. In some aspects, the apparatus can include: a semiconductor substrate; a first capacitor disposed on the semiconductor substrate and electrically coupled between a first pair of metal terminals and a second pair of metal terminals, wherein the first and second pairs of metal terminals are disposed on a first surface of the semiconductor substrate; a second capacitor disposed on the semiconductor substrate and electrically coupled between a third pair of metal terminals and a fourth pair of metal terminals, wherein the third and fourth pairs of metal terminals are disposed on the first surface of the semiconductor substrate; a passivation layer disposed on the first surface of the semiconductor substrate and spanning at least the first, second, third, and fourth pairs of metal terminals; a pair of first openings defined by the passivation layer and respective openings of the pair of first openings disposed on the pair of first metal terminals; a pair of second openings defined by the passivation layer and respective openings of the pair of second openings disposed on the pair of second metal terminals; a pair of third openings defined by the passivation layer and respective openings of the pair of third openings disposed on the pair of third metal terminals; a pair of fourth openings defined by the passivation layer and respective openings of the pair of fourth openings disposed on the pair of fourth metal terminals; a first metal bump disposed on the passivation layer and electrically coupling the pair of first metal terminals together through the pair of first openings; a second metal bump disposed on the passivation layer and electrically coupling the pair of second metal terminals together through the pair of second openings; a third metal bump disposed on the passivation layer and electrically coupling the pair of third metal terminals together through the pair of third openings; and a fourth metal bump disposed on the passivation layer and electrically coupling the pair of fourth metal terminals together through the pair of fourth openings.

[0006] According to aspects, an apparatus is provided. In some aspects, the apparatus can include: a semiconductor substrate; a first capacitor disposed on the semiconductor substrate and electrically coupled between a first terminal and a second terminal; a second capacitor disposed on the semiconductor substrate and electrically coupled between a third terminal and a fourth terminal; a passivation layer disposed on a first surface of the semiconductor substrate and defining a first opening formed on the first terminal, a second opening formed on the second terminal, a third opening formed on the third terminal, and a fourth opening formed on the fourth terminal; a first metal bump disposed on the passivation layer and electrically coupled to the first terminal and the third terminal through the first opening and the third opening, respectively; and a second metal bump disposed on the passivation layer and electrically coupled to the second terminal and the fourth terminal through the second opening and the fourth opening, respectively. BRIEF DESCRIPTION OF DRAWINGS

[0007] Various embodiments according to the present disclosure will be described in conjunction with the accompanying drawings, in which:

[0008] Figure 1A is a diagram illustrating a representative example of a configurable capacitance chip according to some aspects of the present disclosure.

[0009] Figure 1B is a diagram illustrating a representative example of a configurable capacitance chip according to some aspects of the present disclosure. Figure 1A is a diagram illustrating a side view of a representative example of a configurable capacitance chip in

[0010] Figure 1C is a diagram illustrating a side view of another representative example of a configurable capacitance chip according to some aspects of the present disclosure.

[0011] Figure 2 is a diagram of another representative example of a configurable capacitance chip provided for some aspects of the present disclosure.

[0012] Figure 3A is a diagram illustrating a representative example of a configurable capacitance chip with sensing terminals according to some aspects of the present disclosure.

[0013] Figure 3B is a simplified schematic diagram illustrating electrical connections of internal sensing terminals of a configurable capacitance chip in Figure 3A

[0014] Figure 4 is a diagram illustrating an example of a configurable capacitance chip in an electronic package according to some aspects of the present disclosure.

[0015] Figure 5 is a simplified schematic diagram illustrating an example circuit connection of an application of a configurable capacitance chip according to some aspects of the present disclosure.

[0016] Figure 6 is a simplified schematic diagram of an example of some parasitic inductance of an electronic package provided for some aspects of the present disclosure.

[0017] Figure 7 is a simplified schematic diagram of another example of some parasitic inductance of an electronic package provided for some aspects of the present disclosure.

[0018] Figure 8 is a diagram illustrating a representative example of a configurable capacitance inductance chip according to some aspects of the present disclosure.

[0019] Figure 9 is a simplified schematic diagram of an example application of a configurable capacitance inductance chip provided for some aspects of the present disclosure.

[0020] Figure 10 is a diagram illustrating a representative example of a configurable capacitance resistance chip according to some aspects of the present disclosure. ​

[0021] Figure 11 This is a diagram illustrating a representative example of a configurable capacitor-resistor-inductor chip according to some aspects of this disclosure.

[0022] Figure 12 This is a flowchart illustrating an example of a method for manufacturing a configurable capacitor device according to some aspects of this disclosure.

[0023] Figure 13 This is a diagram illustrating a representative example of a configurable capacitor chip having the same cell size and different inter-cell capacitance values ​​according to some aspects of this disclosure.

[0024] Figure 14 This is a diagram illustrating a representative example of a configurable capacitor chip with different cell sizes and different inter-cell capacitance values ​​according to some aspects of this disclosure.

[0025] Figure 15 This is a diagram illustrating a representative example of a configurable capacitor chip having a shared ground connection between adjacent units, according to some aspects of this disclosure.

[0026] Figure 16A This is a diagram illustrating a representative example of a configurable capacitor chip according to some aspects of this disclosure.

[0027] Figure 16B This illustrates some aspects according to this disclosure. Figure 16A A diagram of a representative example of a configurable capacitor chip, showing copper pillars connecting multiple integrally formed capacitors in a cell.

[0028] Figure 16C This illustrates some aspects of the disclosure. Figure 16B A cross-sectional view of the configurable capacitor chip in the image, with section line AA.

[0029] Figure 16D This is a diagram illustrating an example of a circuit trace connecting copper pillars together according to some aspects of this disclosure.

[0030] Figure 16E This illustrates some aspects of coupling to according to this disclosure. Figure 16A A diagram illustrating an example of the interconnection of terminals of a capacitor formed as a single unit.

[0031] Figure 16F This illustrates some aspects according to this disclosure. Figure 16E A diagram illustrating an example of copper pillars formed between the interconnects of the configurable capacitor chip 1600.

[0032] Figure 16G This illustrates some aspects according to this disclosure. Figure 16Ais a simplified schematic diagram of an example of a capacitor integrated with a capacitor of

[0033] Figure 17 is a flowchart illustrating an example of a method of manufacturing a configurable capacitor chip in accordance with some aspects of the present disclosure. DETAILED DESCRIPTION

[0034] While certain embodiments are described, these embodiments are presented by way of example only, and are not intended to limit the scope of protection. The apparatuses, methods, and systems described herein can be embodied in a variety of other forms. In addition, various omissions, substitutions and changes in the form of the methods and systems described herein can be made without departing from the scope of protection.

[0035] Discrete capacitors can be used in a variety of applications. One such application is decoupling capacitors used to reduce voltage ripple and noise at the input and output voltage lines of an integrated circuit, such as but not limited to a voltage regulator. As integrated circuits are becoming smaller and smaller, with circuit elements integrated on-chip, there is a need for high-density small-area capacitors with low equivalent series resistance (ESR) and equivalent series inductance (ESL) requirements that can be placed in close proximity to the integrated circuit.

[0036] Various aspects of the present disclosure can provide a method of configuring a desired capacitance on a single chip. The configurable capacitor chip can be manufactured using standard semiconductor processing techniques. The configurable capacitor chip can be more flexible and cost-advantageous compared to placing multiple capacitors on a printed circuit board (PCB) or an integrated circuit (IC) package. The configurable capacitor chip can be manufactured at a lower cost compared to multiple discrete capacitors and can provide the ability to configure capacitor characteristics such as ESR and ESL at the package level. More specifically, in some embodiments, a standardized capacitor chip can be used in different applications, where the number and characteristics of the capacitors formed by the capacitor chip are configured by changing electrical interconnections on a package substrate to which the capacitor chip is connected. In addition, the configurable capacitor chip can take up less space on a PCB compared to discrete capacitors. The configurable capacitor chip can be suitable for any application that requires multiple capacitors.

[0037] Figure 1A is a simplified schematic diagram of an example of a capacitor integrated with a capacitor of Figure 1B is a simplified schematic diagram of an example of a capacitor integrated with a capacitor of Figure 1A is a side view of a representative example of a configurable capacitor chip 100 in Figure 1A and 1BThe configurable capacitance chip 100 can include a plurality of capacitors 110 fabricated on the first surface 122 of the substrate 120. Each capacitor 110 can be electrically connected to a pair of contacts, referred to herein as chip bumps 140, fabricated on the first surface 122 of the substrate 120. The chip bumps 140 can be, for example, solder bumps.

[0038] In some embodiments, the capacitance range of each integrated capacitor can be 10 to 10,000 millimicrofarads, in another embodiment 50 to 5000 millimicrofarads, and in one embodiment 50 to 500 millimicrofarads. In some embodiments, the plurality of capacitors 110 can be combined to provide a larger or smaller capacitance value. The combined capacitors can be referred to as capacitor banks 112, 114. The capacitor banks 112, 114 can be formed, for example, by electrical connections fabricated on the first surface 122 of the substrate 120, by electrical connections fabricated on a substrate of an IC package to which the configurable capacitance chip 100 is attached, by traces on a PCB to which the IC package is attached, or by some combination. The electrical connections can be formed to provide a parallel combination of capacitors, a series combination of capacitors, or a series-parallel combination of capacitors.

[0039] Figure 1C is a diagram illustrating a side view of another representative example of a configurable capacitance chip 150 according to some aspects of the present disclosure. See Figure 1C The configurable capacitance chip 150 can include a plurality of capacitors 155 fabricated on the first surface 162 of the substrate 160. Each capacitor 155 can be electrically connected to a pair of contacts 170 fabricated on the first surface 162 of the substrate 160. The contacts 170 fabricated on the first surface 162 of the substrate 160 can be electrically connected to contacts, referred to herein as chip bumps 180, fabricated on the second surface 164 of the substrate 160. The chip bumps 180 can be, for example, solder bumps. In some embodiments, the plurality of capacitors 110 can be combined into a plurality of banks to provide a larger or smaller capacitance value by electrical connections fabricated on the second surface 164 of the substrate 160, by electrical connections fabricated on a substrate of an IC package to which the configurable capacitance chip 150 is attached, by traces on a PCB to which the IC package is attached, or by some combination.

[0040] While Figure 1A While two banks 112, 114 are shown having the same number of capacitors in each bank, the banks can have different sizes depending on the intended application. In some implementations, the capacitors 110 can not be divided into banks. In implementations where capacitor banks are fabricated, the electrical connections between capacitors are not limited to capacitors within a capacitor bank.

[0041] It should be understood that Figure 1A , 1Band 1C are schematic representations of configurable capacitance chips according to some aspects of the present disclosure and are provided for ease of explanation. The figures are not used to illustrate representative dimensions of any elements of the configurable capacitance chips. Further, the number of capacitors illustrated is merely representative and is not limiting of the number of capacitors or their relative placement provided by various embodiments. Moreover, when the capacitor contacts 140 are labeled as Vout and Vss in Figure 1A , the labels are merely representative and should not be construed as requiring the capacitor contacts 140 to be connected to the Vout and Vss voltages.

[0042] Figure 2 is a diagram of another representative example of a configurable capacitance chip 200 provided for some aspects of the present disclosure. Referring to Figure 2 , a configurable capacitance chip is shown that includes four different groups of capacitors 210-240. As shown in Figure 2 , each group of capacitors 210-240 can include a different number of capacitors. Further, the capacitors can be fabricated in different orientations. For example, the capacitors 212 in the first row 210 are fabricated in a vertical orientation, while the capacitors 222 in the second row 220 are fabricated in a horizontal orientation. The groups of capacitors can include capacitors fabricated in both horizontal and vertical orientations. The configurable capacitance chip 200 can be configured as a single capacitance (e.g., all of the capacitors coupled together) or multiple capacitances (e.g., a group of capacitors coupled together).

[0043] In some implementations, multiple configurable capacitance chips in a semiconductor package can be interconnected, such that a variety of capacitance values can be achieved. In some implementations, multiple configurable capacitance chips can be arranged in different orientations relative to each other in the semiconductor package. The different orientations can allow for interconnection of the configurable capacitance chips, such that a variety of capacitance values can be achieved. For example, adjacent configurable capacitance chips can be rotated to allow for interconnection between the configurable capacitance chips.

[0044] It should be appreciated that Figure 2 is a schematic representation of a configurable capacitance chip according to some aspects of the present disclosure and is provided for ease of explanation. The figure is not used to illustrate representative dimensions of any elements of the configurable capacitance chips. Further, the number of capacitors illustrated is merely representative and is not limiting of the number of capacitors or their relative placement provided by various embodiments. Moreover, when the capacitor terminals are labeled as Vout and Vss in Figure 2 , the labels are merely representative and should not be construed as requiring the capacitor terminals to be connected to the Vout and Vss voltages.

[0045] Figure 3A is a diagram showing a representative example of a configurable capacitance chip 300 having sense terminals according to some aspects of the present disclosure. Figure 3Bis a simplified schematic diagram illustrating internal sensing terminals of a configurable capacitance chip 300 in an electronic package according to some aspects of the present disclosure. See Figure 3A Figure 3A and 3B , the configurable capacitance chip 300 can include a first voltage sense terminal Vosns 340 and a second voltage sense terminal 345. The voltage sense terminal Vosns 340 can be externally connected to a solder bump (e.g., solder bump 140) of the configurable capacitance chip 300, can be internally connected to the configurable capacitance chip 300 at the capacitor 310, and can be a connection point for a capacitance combination of the configurable capacitance chip 300. One or more voltage sense terminal Vosns 340 solder bumps can be used for a capacitance group or a group of capacitors. The voltage sense terminal Vssns 345 can be externally connected to a solder bump (e.g., solder bump 140) of the configurable capacitance chip 300, can be internally connected to the configurable capacitance chip 300 at the capacitor 310, and can be a connection point for a capacitance combination of the configurable capacitance chip 300. One or more voltage sense terminal Vssns 345 solder bumps can be used for a capacitance group or a group of capacitors.

[0046] The voltage sense terminal Vosns 340 can enable voltage sensing that can minimize the effects of the ESR 360 and ESL 350 of a capacitance or capacitance combination. For example, in a voltage regulator application, the voltage sense terminal Vosns 340 can minimize the effects of the parasitic resistance and inductance of the Vout configurable capacitance chip bump, the metal routing on the package (or PCB) substrate, and / or the Vout package ball, and the control loop of the voltage regulator. The inductance of the voltage regulator can be terminated on the Vout bump, and the control loop feedback can be taken from the Vout sense bump Vosns 340. Similarly, the voltage sense terminal Vssns 345 can enable voltage sensing that can minimize the effects of the ESR 365 and ESL 355 of a capacitance or capacitance combination.

[0047] Figure 4 is a diagram illustrating an example of a configurable capacitance chip in an electronic package according to some aspects of the present disclosure. As shown in Figure 4 ​As shown, the electronic package 410 can be mounted on a PCB 420 with a ball grid array 430, or other solder connections connecting the package substrate 440 to the PCB 420. An integrated circuit 450 (e.g., a voltage regulator) and a configurable capacitance chip 460 can be mounted on the package substrate 440 within the electronic package 410 using solder bumps 470. Electrical connections between the integrated circuit 450 and the configurable capacitance chip 460 can be made through solder bump connections to the package substrate 440. Electrical connections between the integrated circuit 450 and the configurable capacitance chip 460 (e.g., Vout, Vss, Vosns) can be connected to the PCB through the ball grid array 430 or other solder connections connecting the package substrate 440 to the PCB 420.

[0048] Electrical connections from the integrated circuit 450 and the configurable capacitance chip 460 to the PCB 420 can be made from the solder bumps 470 and the ball grid array 430. In some embodiments, electrical connections between the capacitances on the configurable capacitance chip 460 can be made on the substrate of the configurable capacitance chip 460, on the substrate 440 of the electronic package 410 to which the configurable capacitance chip 460 is attached, through traces or electrical connections on the PCB 420 to which the electronic package 410 is attached, or some combination of the above.

[0049] As used herein, the term "ball" or "package ball" can refer to electrical connections between integrated circuit packages (e.g., balls 430), such as but not limited to quad flat no-lead (QFN) packages, quad flat packages (QFP), small outline ICs (SOIC), or other types of electronic packages, and a PCB. As used herein, the term "bump" or "chip bump" can refer to solder bump connections between an integrated circuit chip 450 or a configurable capacitance chip 460 and an electronic package substrate 440 (e.g., bumps 470), or in a chip on board (COB) implementation, between an integrated circuit or configurable capacitance chip and a PCB 420.

[0050] The substrate 440 of the electronic package 410, the PCB 420, or both, can be used to connect any number of chip capacitors together to form one or more capacitors with specific capacitance values, ESR, and ESL values. By varying the electrical traces on either structure in different applications, one standardized capacitance chip can be configured for a variety of applications. For example, in one application, all of the capacitors can be coupled in parallel to provide one large capacitance. In another application, one capacitor can be used for an IC decoupling capacitor, a first set of 10 capacitors can be coupled in parallel to form a decoupling capacitor for a first voltage regulator, and a second set of 10 capacitors can be coupled in parallel to form a decoupling capacitor for a second voltage regulator decoupling capacitor. The decoupling capacitors formed by the parallel combinations can be able to provide suitable capacitance values, ESR, and ESL values for the first and second voltage regulators.

[0051] Figure 5 is a simplified schematic diagram showing an example circuit connection of an application of a configurable capacitance chip according to some aspects of the present disclosure. As shown, the application of the configurable capacitance chip can be a dual channel voltage regulator (VR) 500 having a capacitance for each output. Figure 5

[0052] Referring to Figure 5 , the dual channel voltage regulator can include a voltage regulator circuit 510 having a first voltage regulator VR1 and a second voltage regulator VR2. The first voltage regulator VR1 can produce an output current to a load 525 through a first set of inductors 515. The second voltage regulator VR2 can produce an output current to the load 525 through a second set of inductors 520. Configurable capacitance chips 530a, 530b according to the present disclosure can be used to provide input capacitance 532 and output capacitance 534, 536 for the voltage regulator circuit 510.

[0053] Printed circuit traces and solder joint connections to electronic packages provide parasitic inductance to a circuit. According to some aspects of the present disclosure, package ball inductance can be incorporated into the output inductance of a circuit, such as a voltage regulator circuit. Figure 6 is a simplified schematic diagram showing an example of some parasitic inductance of an electronic package provided by some aspects of the present disclosure.

[0054] Referring to Figure 6 , an electronic package 620 can be mounted on a PCB 610 and electrically connected to the PCB 610 through package balls as previously described. As previously described, a configurable capacitance chip 630 can be mounted in the electronic package 620 through chip bumps. A voltage regulator circuit (not shown) can include inductors 615 on the PCB 610. The inductors can be, for example and without limitation, discrete component inductors, inductor traces formed on the surface of the PCB 610, inductor traces integrated in the multiple layers of the PCB 610, and the like.

[0055] Each inductor includes one or more package balls 622 as part of each PCB inductor 615. Incorporating the package ball inductance with the PCB inductance and sensing the output voltage through the Vosns package ball 624 as shown can reduce the effective ESL and ESR of the capacitance 632 affecting the control loop. Similarly, incorporating the package ball inductance with the PCB inductance and sensing the voltage through the Vssns package ball 625 can reduce the effective ESL and ESR of the capacitance 632. The Vout and Vss connections of the voltage regulator circuit can be brought out through the package Vout ball 626 and the package Vss ball 628. The Vout connection through the package Vout ball 626 likewise can reduce output ripple by reducing the effective ESR and ESL of the capacitance 632.

[0056] ​In some embodiments, one or more inductors can be integrated in the electronic package substrate. Figure 7 is a simplified schematic diagram of another example of some of the parasitic inductance of an electronic package provided in accordance with some aspects of the present disclosure. Referring to Figure 7 The configurable capacitance chip 730 can be mounted in the electronic package 720 by chip bumps. The electronic package 720 can be mounted on the PCB 710 by the aforementioned package balls. The voltage regulator circuit 705 can be an integrated circuit included in the electronic package 720. As previously described, the voltage regulator circuit 705 can be mounted in the electronic package 720 by chip bumps. The output inductance 715 of the voltage regulator circuit 705 can be, for example and without limitation, a discrete component inductor, an embedded (or integrated) inductor formed by metal traces on a single layer of a substrate of the electronic package 720 (or PCB), or within multiple layers of the electronic package substrate (or PCB), etc.

[0057] Each inductor includes one or more chip bumps 732 as part of each output inductor 715. Incorporating the chip bump inductance with the output inductance 715 and sensing the output voltage through the illustrated Vosns chip bump 724 and Vssns chip bump 725 can reduce the effective ESL and ESR of the control loop affected by the capacitance 734. The Vout and Vss connections of the voltage regulator circuit can be brought out through the Vout chip bump 732 and the Vss chip bump 738.

[0058] In accordance with some aspects of the present disclosure, various embodiments of the configurable capacitance chip can include additional configurable components, such as resistors and inductors. Figure 8 is a diagram illustrating a representative example of a configurable capacitance inductor chip 800 in accordance with some aspects of the present disclosure. Referring to Figure 8 The configurable capacitance inductor chip 800 can include a plurality of capacitances 810 and a plurality of inductors 820 fabricated on a first surface of a substrate 830. Each capacitance 810 and each inductor 820 can be electrically connected to a pair of contacts 840, 845 fabricated on the first surface of the substrate 830, respectively. The contacts 840, 845 fabricated on the first surface of the substrate 830 can be referred to herein as chip bumps. The chip bumps can be, for example, solder bumps.

[0059] The bumps can be fabricated similarly to the bumps described in connection with FIG. 1. Further, as described in connection with FIG. 1, in some implementations, the capacitances 810 and the inductors 820 can be grouped into banks 850. In some implementations, the capacitances 810 and the inductors 820 can not be grouped into banks. In some implementations, the configurable capacitance inductor chip 800 can include one or more voltage sense terminals Vosns and Vssns as described in connection with FIG. 3.

[0060] In some embodiments, the range of capacitance of each integrated capacitor can be 10 to 10,000 millimicrofarads, in another embodiment 50 to 5000 millimicrofarads, and in one embodiment 50 to 500 millimicrofarads. In some embodiments, multiple capacitors 810 can be combined to provide a larger or smaller capacitance value.

[0061] In some embodiments, the range of inductance of each integrated inductor can be between 1 picohenry and 100 millihenry, in another embodiment the range of inductance can be between 100 picohenry and 10 millihenry, and in one embodiment the range of inductance can be between 1 and 5 millihenry.

[0062] It should be understood that, Figure 8 is a schematic representation of a configurable capacitance inductance chip according to some aspects of the disclosure. This figure is provided to facilitate explanation. This figure is not used to illustrate representative dimensions of any elements of the configurable capacitance inductance chip. Further, the number of capacitors and inductors illustrated is merely representative and is not limiting of the number of capacitors and inductors provided by various embodiments or their relative placement. When the capacitor contacts 840 are labeled Cl and C2, they can be connected to Vout and / or Vss, or to other points in the circuit. The labels are merely representative and should not be construed as requiring the capacitor contacts 840 to be connected to any particular voltage.

[0063] Figure 9 is a simplified schematic of an exemplary application of a configurable capacitance inductance chip provided by some aspects of the disclosure. See Figure 9 The configurable capacitance inductance chip 930 can be mounted in an electronic package 920 by chip bumps. The electronic package 920 can be mounted on a PCB by package balls as previously described. The voltage regulator circuit 905 can be an integrated circuit included in the electronic package 920. As previously described, the voltage regulator circuit 905 can be mounted in the electronic package 920 by chip bumps. In some implementations, the configurable capacitance inductance chip and the voltage regulator circuit can be mounted directly to a PCB by chip bumps.

[0064] The output inductance and capacitance of the voltage regulator circuit 905 can be provided by the inductance 932 and the capacitance 934 of the configurable capacitance inductance chip 930. In some implementations, each inductor includes one or more chip bumps 917 as part of each output inductor 932. Combining the chip bump 917 inductance with the output inductance 932 and sensing the output voltage through the illustrated Vosns chip bump 915 and the voltage Vss through the Vssns chip bump 916 can reduce the effective ESL and ESR of the capacitance 934 affecting the control loop.

[0065] Figure 10is a diagram illustrating a representative example of a configurable capacitance-resistance chip 1000 in accordance with some aspects of the present disclosure. See Figure 10 The configurable capacitance-resistance chip 1000 can include a plurality of capacitances 1010 and a plurality of resistances 1020 fabricated on a first surface of a substrate 1030. Each capacitance 1010 and each resistance 1020 can be electrically connected to a pair of contacts 1040, 1045 fabricated on the first surface of the substrate 1030, respectively. The contacts 1040, 1045 fabricated on the first surface of the substrate 1030 can be referred to herein as chip bumps. The chip bumps can be, for example, solder bumps.

[0066] The bumps can be fabricated similarly to the bumps described in connection with FIG. 1. Further, as described in connection with FIG. 1, in some embodiments, the capacitances 1010 and the resistances 1020 can be grouped into sets 1050. In some embodiments, the capacitances 1010 and the resistances 1020 can not be grouped into sets. In some embodiments, the configurable capacitance-resistance chip 1000 can include one or more voltage sense terminals Vosns and Vssns as described in connection with FIG. 3.

[0067] In some embodiments, the capacitance range of each integrated capacitance can be 10 to 10,000 millimicrofarads, in another embodiment 50 to 5000 millimicrofarads, and in one embodiment 50 to 500 millimicrofarads. In some embodiments, multiple capacitances 1010 can be combined to provide a larger or smaller capacitance value.

[0068] In some embodiments, the resistance range of each integrated resistance can be between 50 ohms and 10,000 ohms. Other resistance ranges can be possible. In some embodiments, multiple resistances 1020 can be combined to provide a larger or smaller resistance value.

[0069] It should be understood that, Figure 10 is a schematic representation of a configurable capacitance-resistance chip in accordance with some aspects of the present disclosure. This figure is provided for ease of explanation. This figure is not used to illustrate representative dimensions of any elements of the configurable capacitance-resistance chip. Further, the number of capacitances and resistances illustrated is merely representative and is not limiting of the number of capacitances and resistances provided by various embodiments or their relative placement. The capacitance contacts 1040 are labeled Cl and C2 and can be connected to Vout and / or Vss or to other points in a circuit. The labels are merely representative and should not be understood to require that the capacitance contacts 1040 be connected to any particular voltage.

[0070] Figure 11 is a diagram illustrating a representative example of a configurable capacitance-resistance-inductance chip 1100 in accordance with some aspects of the present disclosure. See Figure 11Configurable capacitor-resistor-inductor chip 1100 can include a plurality of capacitors 1110, a plurality of resistors 1120, and a plurality of inductors 1125 fabricated on a first surface of substrate 1130. Each capacitor 1110, each resistor 1120, and each inductor 1125 can be electrically connected to a pair of contacts 1140, 1145, 1148 fabricated on the first surface of substrate 1130, respectively.

[0071] Contacts 1140, 1145, 1148 fabricated on the first surface of substrate 1130 can be referred to herein as chip bumps. The chip bumps can be, for example, solder bumps. The bumps can be fabricated similarly to the bumps described in connection with FIG. 1. Further, as described in connection with FIG. 1, in some embodiments, capacitors 1110, resistors 1120, and inductors 1125 can be grouped into sets 1150. In some embodiments, capacitors 1110, resistors 1120, and inductors 1125 can not be grouped. In some embodiments, configurable capacitor-resistor-inductor chip 1100 can include one or more voltage sense terminals Vosns and Vssns as described in connection with FIG. 3.

[0072] In some embodiments, each integrated capacitor can have a capacitance range of 10 to 10,000 millimicrofarads, in another embodiment, 50 to 5000 millimicrofarads, in one embodiment, 50 to 500 millimicrofarads. In some embodiments, multiple capacitors 1110 can be combined to provide a larger or smaller capacitance value.

[0073] In some embodiments, each integrated resistor can have a resistance range of 50 ohms to 10,000 ohms. Other resistance ranges can be possible. In some embodiments, multiple resistors 1120 can be combined to provide a larger or smaller capacitance value.

[0074] In some embodiments, each integrated inductor can have an inductance range of 1 picohenry to 100 millihenry, in another embodiment, an inductance range of 100 picohenry to 10 millihenry, in one embodiment, an inductance range of 1 to 5 millihenry. In some embodiments, multiple inductors 1125 can be combined to provide a larger or smaller inductance value.

[0075] It should be appreciated that, Figure 11 FIG. 4 is a schematic representation of a configurable capacitor-resistor-inductor chip according to some aspects of the present disclosure. This figure is provided for ease of explanation. The figure is not used to illustrate representative dimensions or a specific order of any of the elements of the configurable capacitor-resistor-inductor chip. Further, the number of capacitors, resistors, and inductors illustrated is merely representative and does not limit the number of capacitors, resistors, and inductors provided by various embodiments or their relative placement. Moreover, when a capacitor contact 1140 is illustrated as being connected to a resistor contact 1145, it is understood that the connection can be made to any of the resistor contacts 1145.Figure 11 The labels are merely representative and should not be construed as requiring that the capacitor contacts 1140 be connected to Vout and Vss voltages.

[0076] Figure 12 is a flowchart illustrating an example of a method 1200 of manufacturing configurable integrated circuit (IC) capacitor devices according to some aspects of the present disclosure. See Figure 12 In block 1210, a capacitor device can be formed. The capacitor device can be manufactured using standard semiconductor processing techniques. A plurality of capacitors can be manufactured on a first surface of a substrate. Each capacitor can be electrically connected to a pair of contacts manufactured on the first surface of the substrate 120. The contacts manufactured on the first surface of the substrate can be referred to as chip bumps. The chip bumps can be, for example, solder bumps.

[0077] In optional block 1220, electrical connections between the capacitors can be formed on the substrate of the capacitor device. In some embodiments, a plurality of capacitors can be combined to provide a larger or smaller capacitance value. The combined capacitors can be referred to as a capacitor bank. The capacitor bank can be formed, for example, by electrical connections manufactured on a second surface of the substrate.

[0078] In block 1230, electrical connections between the capacitors can be formed on the substrate of the electronic package. The additional electrical connections can be manufactured as circuit traces on the substrate of the electronic package that integrates the capacitor device. The conductive traces on the substrate of the electronic package can provide electrical connections between the chip bumps to configure the capacitors on the capacitor device.

[0079] In block 1240, the capacitor device can be integrated into the electronic package. Electrical connections can be formed between the substrate of the capacitor device and the substrate of the electronic package. For example, solder bumps on the substrate of the capacitor device can be electrically connected to conductive traces on the substrate of the electronic package. The electrical connections between the capacitors formed by the conductive traces on the substrate of the electronic package can form desired capacitance values.

[0080] In optional block 1250, additional electrical connections between the capacitors can be formed by conductive traces on a PCB to which the electronic package is attached. The electrical connections between the capacitors formed by the conductive traces on the PCB and the conductive traces on the substrate of the electronic package can combine the capacitors to form desired capacitance values.

[0081] Figure 12 The specific operations shown can provide a particular method of manufacturing configurable integrated circuit (IC) capacitors according to embodiments of the present disclosure. Other sequences of operations can also be performed according to alternative embodiments. For example, alternative embodiments of the present disclosure can perform the operations described above in a different order. Moreover, Figure 12Each operation shown can include a number of sub-operations that can be performed in various sequences as appropriate to the particular operation. Furthermore, additional operations can be added or removed based on specific applications.

[0082] According to some aspects of the disclosure, a set of capacitors can be formed on a semiconductor substrate of the configurable capacitor chip. The set of capacitors can be referred to herein as a "cell." The cells can have the same physical size and / or capacitance value relative to the size of the substrate occupied by the cell, or can have unequal physical size and / or capacitance values. Figure 13 FIG. 13 shows a representative example of a configurable capacitor chip 1300 having the same cell size and different inter-cell capacitance values, according to some aspects of the disclosure.

[0083] Referring to Figure 13 The configurable capacitor chip 1300 can include a plurality of cells 1312a-1312b with integrally formed capacitors 1310 on a semiconductor substrate 1320. Each cell 1312a-1312c can include one or more integrally formed capacitors 1310, and each integrally formed capacitor 1310 in a respective cell can have the same capacitance value. For example, each integrally formed capacitor in the first cell 1312a can have a capacitance value of 100 nF, each integrally formed capacitor in the second cell 1312b can have a capacitance value of 200 nF, and so on, and one or more cells on the semiconductor substrate 1320 can have integrally formed capacitors 1310 with the same capacitance value. For example, each integrally formed capacitor in the first cell 1312a and the third cell 1312c can have a capacitance value of 100 nF. The cells can have equal size relative to the size of the substrate occupied by the cell.

[0084] Each integrally formed capacitor 1310 on the semiconductor substrate 1320 can include a contact terminal 1340. The contact terminal 1340 can be used for electrical connection external to the configurable capacitor chip 1300. For example, circuit connection with the contact terminal 1340 of one or more integrally formed capacitors 1310 can be made through external routing traces on an integrated circuit package substrate (see, e.g., FIG. 14) on which the configurable capacitor chip 1300 is mounted. Figure 4 In some cases, the external routing traces on the integrated circuit package substrate can connect the contact terminals 1340 of two or more integrally formed capacitors 1310 in parallel or in series to provide different capacitance values.

[0085] In some cases, circuit connection with the contact terminal 1340 of one or more integrally formed capacitors 1310 can be made through external routing traces on an integrated circuit package (see, e.g., FIG. 14) on which the configurable capacitor chip 1300 is mounted. Figure 4External wiring traces are formed on the PCB of the configurable capacitor chip 1300. In some cases, the circuit connection to the contact terminals 1340 of one or more integrally formed capacitors 1310 can be formed by two external wiring traces on the integrated circuit package substrate on which the configurable capacitor chip 1300 is mounted and external wiring traces on the PCB on which the integrated circuit package is mounted. The cells can be connected together in any configuration, such as, but not limited to, all or part of a row or column, a combination of rows and columns, cells between adjacent configurable capacitor chips, etc., to achieve a desired capacitance value.

[0086] Although Figure 13 Each unit is shown to have two capacitors, but each unit may include any number of integrally formed capacitors. Further, each unit may include the same or different numbers of integrally formed capacitors. The provided capacitance values ​​are merely illustrative. Units of the configurable capacitor chip 1300 according to this disclosure may have integrally formed capacitors with other capacitance values ​​without departing from the scope of this disclosure.

[0087] Figure 14 This is a diagram illustrating a representative example of a configurable capacitor chip 1400 with different cell sizes and inter-cell capacitance values ​​according to some aspects of this disclosure. See also Figure 14 The configurable capacitor chip 1400 may include multiple units 1412a-1412b, each having an integrally formed capacitor 1410 on a semiconductor substrate 1420. Each unit 1412a-1412b may include one or more integrally formed capacitors 1410, and each integrally formed capacitor 1410 in each unit may have a different capacitance value. For example, each integrally formed capacitor in the first unit 1412a may have a capacitance value of 100nF, each integrally formed capacitor in the second unit 1412b may have a capacitance value of 200nF, and so on. More than one unit on the semiconductor substrate 1420 may have integrally formed capacitors 1410 with the same capacitance value. For example, each integrally formed capacitor in the second unit 1412b and the third unit 1412c may have a capacitance value of 200nF. The physical dimensions of the units relative to the substrate area occupied by the units may be unequal. Units having the same number of integrally formed capacitors with the same capacitance value may have the same physical dimensions relative to the substrate area occupied by the units.

[0088] Each integrally formed capacitor 1410 on the semiconductor substrate 1420 may include a contact terminal 1440. The contact terminal 1440 can be used for electrical connections to the external components of the configurable capacitor chip 1400. For example, circuit connections to the contact terminals 1440 of one or more integrally formed capacitors 1410 can be made via an integrated circuit package substrate on which the configurable capacitor chip 1400 is mounted (e.g., see...).Figure 4 External wiring traces are formed on the integrated circuit package substrate. In some cases, external wiring traces on the integrated circuit package substrate can connect the contact terminals 1440 of two or more integrally formed capacitors 1410 in parallel or in series to provide different capacitance values. In some cases, the wiring traces forming the connection can be on the configurable capacitor chip 1400.

[0089] In some cases, the circuit connection to the contact terminals 1440 of one or more integrally formed capacitors 1410 can be achieved by mounting an integrated circuit package (e.g., see...). Figure 4 External wiring traces are formed on the PCB of the configurable capacitor chip 1400. In some cases, the circuit connection to the contact terminals 1440 of one or more integrally formed capacitors 1410 can be formed by two external wiring traces on the integrated circuit package substrate on which the configurable capacitor chip 1400 is mounted and external wiring traces on the PCB on which the integrated circuit package is mounted. The cells can be connected together in any configuration, such as, but not limited to, all or part of a row or column, a combination of rows and columns, cells between adjacent configurable capacitor chips, etc., to achieve a desired capacitance value.

[0090] Although Figure 14 Each cell is shown to have one capacitor, but each cell may include any number of integrally formed capacitors. Further, each cell may include the same or different numbers of integrally formed capacitors. The provided capacitance values ​​are merely illustrative. Cells of the configurable capacitor chip 1400 according to this disclosure may have integrally formed capacitors with other capacitance values ​​without departing from the scope of this disclosure.

[0091] In some implementations, multiple configurable capacitor chips within a semiconductor package can be interconnected to achieve various capacitance values. In some implementations, the multiple configurable capacitor chips can be arranged in different orientations relative to each other within the semiconductor package. Different orientations can allow the configurable capacitor chips to interconnect, thereby enabling various capacitance values. For example, adjacent configurable capacitor chips can be rotated to allow interconnection between the configurable capacitor chips.

[0092] In some implementations, connections can be shared between capacitors integrally formed on a configurable capacitor chip. Figure 15 is a diagram illustrating a representative example of a configurable capacitor chip 1500 with shared connections according to some aspects of this disclosure, such as, but not limited to, ground connections between adjacent cells. Figure 15As shown, the capacitor integrally formed in the first unit 1510 can share one or more connections 1515 with the capacitor integrally formed in the second unit 1520. In some embodiments, the shared connection 1535 can be shared by all capacitors in a unit, such as in the third unit 1530. In yet another implementation, the shared connection 1545 can be shared by all capacitors in two units, such as in the fourth unit 1540 and the fifth unit 1550.

[0093] Individual capacitors formed within each unit can have the same capacitance value. Capacitors formed within different units can have different capacitance values. For example, see... Figure 15 Each integrally formed capacitor in the first unit 1510 may have a capacitance value of 100 nF, each integrally formed capacitor in the second unit 1520 may have a capacitance value of 200 nF, and each integrally formed capacitor in the third unit 1530 may have a capacitance value of 300 nF. In some embodiments, integrally formed capacitors in adjacent units may have the same capacitance value. For example, each integrally formed capacitor in the fourth unit 1540 may have a capacitance value of 400 nF, and each integrally formed capacitor in the fifth unit 1550 may have a capacitance value of 400 nF.

[0094] According to some aspects of this disclosure, copper pillar technology can be used to form an electrical connection between a configurable capacitor chip and an electronic packaging substrate or PCB. The contact terminals of the integrally formed capacitor can be formed from a metal layer on the semiconductor substrate of the configurable capacitor chip. Copper pillars formed between the common contact terminals of the integrally formed capacitor can provide additional bonding surfaces for forming an electrical connection with the configurable capacitor chip. The copper pillars can be formed on a passivation layer to connect the common contact terminals of the integrally formed capacitor.

[0095] Figure 16A This is a diagram illustrating a representative example of a configurable capacitor chip 1600 with a display passivation layer 1610 according to some aspects of this disclosure. Figure 16A Three cells 1605a-1605c are shown, each cell containing an integrally formed capacitor composed of a plurality of smaller interconnected integrally formed capacitors. Figure 16G This illustrates some aspects according to this disclosure. Figure 16A A simplified schematic diagram of an example of an integrally formed capacitor. In some embodiments, an integrally formed capacitor may be a single capacitor structure with multiple parallel interconnections, as described in more detail below.

[0096] See Figure 16GCapacitor 1625 can represent a plurality of integrally formed capacitors that can be combined to form capacitor 1625 having a capacitance value of the plurality of integrally formed capacitors. Each of the plurality of integrally formed capacitors can include a pair of contact terminals, collectively referred to as contact terminals 1602a, 1602b. Contact terminals 1602a, 1602b can be formed on a substrate and can form an electrical connection with the integrally formed capacitors. At least one of the pair of contact terminals 1602a, 1602b can include secondary terminals 1622, 1624 connected in parallel with the contact terminals 1602a, 1602b. In some embodiments, not every secondary terminal in each set of secondary terminals 1622, 1624 can be connected with every other secondary terminal in the set. In some embodiments, the secondary terminals can be formed as conductive strips extending from each contact terminal 1602a, 1602b. Interconnects can be formed to couple the secondary terminals 1622, 1624 from the surface forming the capacitor to an opposing surface of the substrate.

[0097] Referring again to Figure 16A , passivation layer 1610 can be processed, for example by etching or other methods, to provide openings 1615a-1615g, 1617a-161f in passivation layer 1610. The openings can correspond to interconnects to underlying secondary terminals 1622, 1624 (see Figure 16G ) of capacitor 1625. For example, openings 1615a-1615g can correspond to interconnects to the underlying secondary terminals 1622 (see Figure 16G ) that, for example, can be terminals connected to a ground potential, referred to herein as the negative terminal of the capacitor. Openings 1617a-161f can correspond to interconnects to the underlying secondary terminals 1624 that are connected to a potential different from the ground potential, referred to herein as the positive terminal of the capacitor.

[0098] Accordingly, each of openings 1615a-1615g in column 1601 can correspond to a secondary terminal 1622 of a capacitor 1625 formed in first cell 1605a that is connected to the negative terminal of the capacitor, each of openings 1617a-1617f in column 1602 can correspond to a secondary terminal 1624 connected to the positive terminal of the capacitor. Each of the openings in column 1603 can correspond to a secondary terminal of a capacitor formed in second cell 1605b that is connected to the negative terminal of the capacitor, and each of the openings in column 1604 can correspond to a secondary terminal connected to the positive terminal of the capacitor. Similarly, each of the openings in columns 1605 and 1607 can correspond to a secondary terminal of a capacitor formed in third cell 1605c that is connected to the negative terminal of the capacitor, and each of the openings in columns 1606 and 1608 can correspond to a secondary terminal connected to the positive terminal of the capacitor.

[0099] Figure 16B This illustrates some aspects according to this disclosure. Figure 16A A diagram illustrating a representative example of the configurable capacitor chip 1600 shows copper pillars connecting multiple integrally formed capacitors within a cell. These copper pillars provide multiple parallel interconnects to the capacitors, thereby reducing the effective series inductance (ESL) and effective series resistance (ESR), which is particularly advantageous for power supply applications with high transient currents. Figure 16B As shown, copper pillar technology can be used to form copper pillars to provide electrical connections to the contact terminals of capacitors integrally formed in each unit. For example, copper pillar 1630a can be formed to electrically connect the negative contact terminals below openings 1615a and 1615b, copper pillar 1630b can be formed to electrically connect the negative contact terminals below openings 1615c-1615e, and copper pillar 1630c can be formed to electrically connect the negative contact terminals below openings 1615f and 1615g. Similarly, copper pillar 1635a can be formed to electrically connect the positive contact terminals below openings 1617a and 1617b, copper pillar 1635b can be formed to electrically connect the positive contact terminals below openings 1617c and 1617d, and copper pillar 1635c can be formed to electrically connect the positive contact terminals below openings 1617e and 1617f. The copper pillars in each column can then be coupled to conductive traces formed on a substrate, such as an IC package or PCB, thereby connecting each secondary terminal (e.g., ...) in the same column. Figure 16G The secondary terminals 1622 and 1624 are electrically connected to the same potential.

[0100] Figure 16C This illustrates some aspects of the disclosure. Figure 16B A cross-sectional view of the configurable capacitor chip, shown by section line AA. Figure 16C As shown, copper extension regions 1616a-1616g can be formed through openings 1615a-1615g, and copper pillars 1630a-1630c can be formed to form at least a portion of the copper extension regions 1616a-1616g extending through the openings 1615a-1615g in the passivation layer 1610. Figure 16C In the example, copper pillars 1630a-1630c can connect to the bottom negative contact terminals of multiple integrated capacitors.

[0101] Figure 16DThis is a diagram illustrating an example of a circuit trace 1640 connecting copper pillars 1630a-1630c together according to some aspects of this disclosure. The circuit trace 1640 may be, for example, a circuit trace on an electronic packaging substrate or PCB, for electrically connecting copper pillars 1630, which are respectively electrically connected to the ground contact terminals of individual capacitors. Thus, each bottom negative terminal and each bottom positive terminal of the capacitor in the cell can be electrically coupled. In embodiments where the opening 1615 is too small to form an external connection with an external structure (e.g., a PCB, etc.), the copper pillars 1630 can provide a larger contact area suitable for forming a connection with an external PCB, etc.

[0102] One or more metal layers 1620 forming contact terminals (e.g., secondary terminals 1622, 1624) are in Figure 16C , 16D The area is represented by a region and can be formed of copper or a combination of copper and one or more other materials. Each of the one or more metal layers 1620 may have a thickness of about 0.5-5.0 μm and may be separated by a respective dielectric layer. In some embodiments, the one or more metal layers 1620 may include one or more redistribution layers. The passivation layer 1610 may be formed of polyimide or other materials and may have a thickness in the range of 0.5-1.0 μm. The passivation layer 1610 may provide a protective insulating layer on integrally formed capacitor and contact terminals. The copper pillar 1630 may be formed of copper or a combination of copper and one or more other materials. The copper pillar 1630 may have a thickness of about 5-75 μm.

[0103] Figure 16E This demonstrates that some aspects of this disclosure are capable of... Figure 16A A diagram illustrating an example of the interconnections formed between the terminals of a capacitor that is integrally formed. See also... Figure 16E Each unit 1670a, 1670b, and 1670n may include a capacitor element. The capacitor element may be composed of multiple individual, integrally formed capacitors, or it may be composed of multiple single capacitors interconnected in parallel.

[0104] More specifically, in one embodiment, a single capacitor may be formed in region 1670a and may have a plurality of positive terminal interconnect regions defined by passivation openings in columns 1660 and 1661. The single capacitor may have a plurality of negative terminal interconnect regions defined by passivation openings in column 1662. In some embodiments, the plurality of positive terminal interconnect regions in column 1660 may be coupled to the plurality of positive terminal interconnect regions in column 1661 via interconnects 1671a-1671f. In some embodiments, interconnects 1671a-1671f may include metal traces extending along a first direction 1680. Similarly, interconnects 1673a-1673b may connect one or more columns of negative terminal interconnect regions together; however, in this embodiment, only one column of negative terminal interconnects 1662 is present.

[0105] In a further embodiment, multiple capacitor elements may be formed in region 1670a. More specifically, in one embodiment, a capacitor may be formed between each interconnect; for example, a capacitor may be formed between interconnects 1673a and 1671a, and other capacitors may be formed between interconnects 1672a and 1671b, and so on. Those skilled in the art will understand that other suitable configurations may be made for a single capacitor within region 1670a.

[0106] like Figure 16E As shown, interconnects 1671a-1671f may include metal traces extending linearly along a first direction 1680 and formed between passivation openings in column 1660 and passivation openings in column 1661. Interconnects 1671a-1671f may be coupled to the positive terminal of a capacitor integrally formed in the first cell 1670a. Interconnects 1671a-1671f may extend within the first cell 1670a and terminate at cell boundary 1675a. Similarly, interconnects may be coupled to the positive terminal of a capacitor integrally formed in the second cell 1670b, extending only within the second cell 1670b, i.e., they terminate at cell boundaries 1675a, 1675b.

[0107] Interconnects 1672a-1672e and 1673a-1673b may include metal traces extending linearly along a first direction 1680 and formed between passivation openings in columns 1662 and 1666. Interconnects 1672a-1672e and 1673a-1673b may be coupled to the negative terminal of a capacitor integrally formed in the first cell 1670a. For example, interconnect 1672a may couple a passivation opening in column 1662 to a passivation opening in each of columns 1666, 1667, and 1668. Interconnects 1673a-1673b may have a width in a second direction 1685 that is less than, equal to, or greater than the width of interconnects 1672a-1672e.

[0108] The interconnects coupling the positive connection through passivation openings and the interconnects coupling the negative connection through passivation openings can be arranged alternately in a second direction 1685 of the substrate, such as the width direction. Interconnects 1671a-1671f, 1672a-1672e, and 1673a-1673b can be formed on the substrate before the passivation layer 1610 is formed. The passivation layer 1610 is formed on interconnects 1671a-1671f, 1672a-1672e, and 1673a-1673b, and interconnects 1671a-1671f, 1672a-1672e, and 1673a-1673b have openings formed in the passivation layer, allowing the interconnects to make electrical contact.

[0109] Figure 16F This illustrates some aspects according to this disclosure. Figure 16E A diagram illustrating an example of copper pillars formed between the passivation openings of a configurable capacitor chip 1600. (See diagram for reference.) Figure 16F As shown, copper pillars 1690a-1690c can electrically couple the positive interconnects in column 1660, and copper pillars 1690d-1690f can electrically couple the positive interconnects in column 1661 of the first unit 1670a. Similarly, copper pillars 1691a-1691c can electrically couple the negative interconnects in column 1662 of the first unit 1670a. Similar electrical couplings can be formed by copper pillars in columns 1666, 1667, and 1668 of each unit. The copper pillars in each column can then be electrically coupled to conductive traces, for example, on an IC package substrate or PCB, such as... Figure 16D As shown.

[0110] Due to the alternating arrangement of interconnects 1671a-1671f, 1672a-1672e, and 1673a-1673b, copper pillars coupling interconnects in each column can span interconnects. For example, copper pillar 1690a coupling positive interconnects 1671a and 1671b in column 1660 through a passivation opening in passivation layer 1610 can span negative interconnect 1672a. Because copper pillar 1690a is formed, no electrical connection is formed between copper pillar 1690a and negative interconnect 1672a. No opening is formed on passivation layer 1610. Similarly, copper pillar connections can configure other interconnects on capacitor chip 1600.

[0111] While specific embodiments of the disclosure have been shown and described, these are only for purposes of illustration. Various changes in the form and details of the exemplary embodiments, e.g., without limitation, embodiments having more or fewer integrally formed capacitors, more or fewer copper pillars, different orientations of the configurable capacitor chip, etc., can be made without departing from the scope of the disclosure. For example, multiple integrally formed capacitors with secondary terminals can be provided in one cell, each integrally formed capacitor in the cell can have a copper pillar connecting the secondary terminals. Multiple such cells can be fabricated on the substrate of the configurable capacitor chip.

[0112] Figure 17 is a flowchart showing an example of a method 1700 of fabricating a configurable capacitor chip according to some aspects of the disclosure. See Figure 17 In block 1710, a capacitive device can be formed. The capacitor chip can be fabricated using standard semiconductor processing techniques. Multiple capacitors can be fabricated on a first surface of a substrate. Each capacitor can be electrically connected to a pair of contacts fabricated on the first surface of the substrate.

[0113] In block 1720, electrical connections can be formed on the substrate of the configurable capacitor chip. A metal layer can be provided, forming multiple parallel contact terminals for each contact of the capacitors.

[0114] In block 1730, a passivation layer can be formed on the capacitors. The passivation layer can be formed on the multiple capacitors and associated multiple parallel contact terminals. The passivation layer can be formed using standard semiconductor processing techniques. The passivation layer can be formed of polyimide, silicon oxide, silicon nitride, etc., and can have a thickness of about 0.5-1.0 pm. The passivation layer can provide a protective insulating layer on the integrally formed capacitors and contact terminals.

[0115] In block 1740, openings can be formed in the passivation layer. The holes can be formed using standard semiconductor processing techniques. The holes in the passivation layer can correspond to the multiple parallel contact terminals for each contact of the capacitors.

[0116] In block 1750, copper pillars can be formed. Copper pillar technology can be used to form electrical connections between the multiple parallel contact terminals for each contact of the capacitors. The copper pillars can be formed on top of the passivation layer to connect the common contact terminals of the integrally formed capacitors. The copper pillars 1630 can have a thickness of about 5-75 pm.

[0117] In block 1760, an electrical connection between the copper pillar and an external routing can be formed. The external routing can be, for example, a circuit trace on an electronic package substrate or a PCB, and can be used to electrically connect the copper pillar to a parallel contact terminal of the integrally formed capacitor. The via can be formed using standard semiconductor processing techniques. The copper pillar can provide an additional bonding surface for forming an electrical connection between the contact terminal of the integrally formed capacitor of the configurable capacitor chip and a next higher level component, such as an integrated circuit package or a PCB.

[0118] Figure 17 The illustrated specific operations provide a specific method of manufacturing a configurable capacitor chip according to embodiments of the present disclosure. Other sequences of operations can also be performed according to alternative embodiments. For example, alternative embodiments of the present disclosure can perform the above operations in a different order. Moreover, Figure 17 Each of the illustrated operations can include a number of sub-operations that can be performed in various sequences according to the specific operation. Moreover, additional operations can also be added or deleted according to specific applications.

[0119] According to some aspects of the present disclosure, a configurable capacitor in an integrated package is provided. As used below, any reference to a series of examples should be understood as a reference to each of the examples in the series (e.g., "Examples 1-4" should be understood as "Examples 1, 2, 3, or 4").

[0120] Example 1 is a capacitor device comprising: a semiconductor substrate; a capacitor disposed on the semiconductor substrate, comprising first and second positive terminals and first and second negative terminals; a passivation layer formed on the capacitor, the first and second positive terminals, and the first and second negative terminals, the passivation layer defining a first opening over the first positive terminal, a second opening over the second positive terminal, a third opening over the first negative terminal, and a fourth opening over the second negative terminal; a first metal bump disposed on the passivation layer, comprising a first extension portion extending through each of the first and second openings, electrically coupling the first positive terminal to the second positive terminal; and a second metal bump disposed on the passivation layer, comprising a second extension portion extending through each of the third and fourth openings, electrically coupling the first negative terminal to the second negative terminal.

[0121] Example 2 is the capacitor device of Example 1, wherein the first and second positive terminals and the first and second negative terminals each comprise parallel metal traces extending through a surface of the semiconductor substrate.

[0122] Example 3 is the capacitive device of Example 1 or Example 2, wherein the first and second metal bumps are copper pillars configured to be electrically and mechanically coupled to the substrate.

[0123] Example 4 is the capacitive device of Examples 1-3, wherein the capacitor further comprises third and fourth positive terminals and third and fourth negative terminals.

[0124] Example 5 is the capacitive device of Examples 1-4, wherein the passivation layer defines a fifth opening over the third positive terminal, a sixth opening over the fourth positive terminal, a seventh opening over the third negative terminal, and an eighth opening over the fourth negative terminal.

[0125] Example 6 is the capacitive device of Examples 1-5, wherein at least one pair of the plurality of integrally formed capacitors share one of the pair of contact terminals.

[0126] Example 7 is the capacitive device of Examples 1-6, further comprising a third metal bump disposed on the passivation layer including a third extension portion extending through each of the fifth and sixth openings electrically coupling the third positive terminal to the fourth positive terminal; and a fourth metal bump disposed on the passivation layer including a fourth extension portion extending through each of the seventh and eighth openings electrically coupling the third negative terminal to the fourth negative terminal.

[0127] Example 8 is an apparatus comprising: a semiconductor substrate; a first capacitor disposed on the semiconductor substrate and electrically coupled between a first pair of metal terminals and a second pair of metal terminals, wherein the first and second pairs of metal terminals are disposed on a first surface of the semiconductor substrate; a second capacitor disposed on the semiconductor substrate and electrically coupled between a third pair of metal terminals and a fourth pair of metal terminals, wherein the third and fourth pairs of metal terminals are disposed on the first surface of the semiconductor substrate; a passivation layer disposed on the first surface of the semiconductor substrate and spanning at least the first, second, third, and fourth pairs of metal terminals; a pair of first openings defined by the passivation layer and respective openings of the pair of first openings disposed on the pair of first metal terminals; a pair of second openings defined by the passivation layer and respective openings of the pair of second openings disposed on the pair of second metal terminals; a pair of third openings defined by the passivation layer and respective openings of the pair of third openings disposed on the pair of third metal terminals; a pair of fourth openings defined by the passivation layer and respective openings of the pair of fourth openings disposed on the pair of fourth metal terminals; a first metal bump disposed on the passivation layer and electrically coupling the pair of first metal terminals together through the pair of first openings; a second metal bump disposed on the passivation layer and electrically coupling the pair of second metal terminals together through the pair of second openings; a third metal bump disposed on the passivation layer and electrically coupling the pair of third metal terminals together through the pair of third openings; and a fourth metal bump disposed on the passivation layer and electrically coupling the pair of fourth metal terminals together through the pair of fourth openings.

[0128] Example 9 is the apparatus of Example 8, wherein the first capacitor has a first capacitance value and the second capacitor has a second capacitance value, the first capacitance value being different than the second capacitance value.

[0129] Example 10 is the apparatus of Example 8 or 9, wherein the first capacitor has a first capacitance value and the second capacitor has a second capacitance value, the first capacitance value being equal to the second capacitance value.

[0130] Example 11 is the apparatus of Examples 8-10, wherein the first, second, third, and fourth pairs of terminals each comprise parallel metal traces extending through the first surface of the semiconductor substrate.

[0131] Example 12 is the apparatus of Examples 8-11, wherein the first metal bump, the second metal bump, the third metal bump, and the fourth metal bump are copper pillars configured to be electrically and mechanically coupled to a substrate.

[0132] Example 13 is the apparatus of Examples 8-12, wherein the first and third pairs of metal terminals are negative terminals of the first and second capacitors, respectively, and the second and fourth pairs of metal terminals are positive terminals of the first and second capacitors, respectively.

[0133] Example 14 is the apparatus of Examples 8-13, wherein at least one metal terminal of the first pair of metal terminals is electrically coupled to at least one metal terminal of the third pair of metal terminals.

[0134] Example 15 is an apparatus comprising: a semiconductor substrate; a first capacitor disposed on the semiconductor substrate and electrically coupled between a first terminal and a second terminal; a second capacitor disposed on the semiconductor substrate and electrically coupled between a third terminal and a fourth terminal; a passivation layer disposed on a first surface of the semiconductor substrate defining a first opening formed on the first terminal, a second opening formed on the second terminal, a third opening formed on the third terminal, and a fourth opening formed on the fourth terminal; a first metal bump disposed on the passivation layer electrically coupled with the first terminal and the third terminal through the first opening and the third opening, respectively; a second metal bump disposed on the passivation layer electrically coupled with the second terminal and the fourth terminal through the second opening and the fourth opening, respectively.

[0135] Example 16 is the apparatus of Example 15, wherein the first capacitor has a first capacitance value and the second capacitor has a second capacitance value, the first capacitance value being different than the second capacitance value.

[0136] Example 17 is the apparatus of Examples 15 or 16, wherein the first capacitor has a first capacitance value and the second capacitor has a second capacitance value, the first capacitance value being equal to the second capacitance value.

[0137] Example 18 is the apparatus of Examples 15-17, wherein the first capacitor is coupled in parallel with the second capacitor through the first metal bump and the second metal bump.

[0138] Example 19 is the apparatus of Examples 15-18, wherein the first capacitor is coupled in series with the second capacitor through the first metal bump and the second metal bump.

[0139] Example 20 is the apparatus of Examples 15-19, wherein the first metal bump and the second metal bump are copper pillars configured to be electrically and mechanically coupled to a substrate.

[0140] The examples and embodiments described herein are for illustrative purposes only. Various modifications or changes in light thereof will be apparent to persons skilled in the art. Such modifications or changes are included in the spirit and scope of the application, and are intended to be included within the scope of the claims as set out below.

Claims

1. A capacitive device, characterized by comprising: a semiconductor substrate; a capacitor disposed on the semiconductor substrate, the capacitor comprising first and second positive terminals and first and second negative terminals; a passivation layer formed on the capacitor, the first and second positive terminals, and the first and second negative terminals, the passivation layer defining a first opening on the first positive terminal, a second opening on the second positive terminal, a third opening on the first negative terminal, and a fourth opening on the second negative terminal; a first metal bump disposed on the passivation layer, comprising a first extension portion extending through each of the first and second openings, electrically coupling the first positive terminal to the second positive terminal; and a second metal bump disposed on the passivation layer, comprising a second extension portion extending through each of the third and fourth openings, electrically coupling the first negative terminal to the second negative terminal. The first and second positive terminals and the first and second negative terminals each comprise parallel metal traces extending through a surface of the semiconductor substrate.

2. The capacitive device of claim 1, wherein, The first and second metal bumps are copper pillars configured to be electrically and mechanically coupled to a substrate.

3. The capacitive device of claim 1, wherein, The capacitor further comprises third and fourth positive terminals and third and fourth negative terminals.

4. The capacitive device of claim 1, wherein, The passivation layer defines a fifth opening on the third positive terminal, a sixth opening on the fourth positive terminal, a seventh opening on the third negative terminal, and an eighth opening on the fourth negative terminal.

5. The capacitive device of claim 4, wherein, Further comprising a third metal bump disposed on the passivation layer, the third metal bump comprising a third extension portion extending through each of the fifth and sixth openings, electrically coupling the third positive terminal to the fourth positive terminal; and 6. The capacitive device of claim 5, wherein, a fourth metal bump disposed on the passivation layer, comprising a fourth extension portion extending through each of the seventh and eighth openings, electrically coupling the third negative terminal to the fourth negative terminal. The first and third metal bumps are arranged in a first column, and the second and fourth metal bumps are arranged in a second column. comprising:

7. The capacitive device of claim 6, wherein, a semiconductor substrate; 8. An apparatus, comprising: a first capacitor disposed on the semiconductor substrate and electrically coupled between a first pair of metal terminals and a second pair of metal terminals, wherein the first and second pairs of metal terminals are disposed on a first surface of the semiconductor substrate; a second capacitor disposed on the semiconductor substrate and electrically coupled between a third pair of metal terminals and a fourth pair of metal terminals, wherein the third and fourth pairs of metal terminals are disposed on the first surface of the semiconductor substrate; a passivation layer disposed on the first surface of the semiconductor substrate and laterally across at least the first, second, third, and fourth pairs of metal terminals; a pair of first openings defined by the passivation layer and respective openings of the pair of first openings disposed on the pair of first metal terminals; a pair of second openings defined by the passivation layer and respective openings of the pair of second openings disposed on the pair of second metal terminals; and a pair of third openings defined by the passivation layer and respective openings of the pair of third openings disposed on the pair of third metal terminals. ​ a pair of third openings defined by the passivation layer and respective openings of the pair of third openings disposed on the pair of third metal terminals; a pair of fourth openings defined by the passivation layer and respective openings of the pair of fourth openings disposed on the pair of fourth metal terminals; a first metal bump disposed on the passivation layer and electrically coupling the pair of first metal terminals together through the pair of first openings; a second metal bump disposed on the passivation layer and electrically coupling the pair of second metal terminals together through the pair of second openings; a third metal bump disposed on the passivation layer and electrically coupling the pair of third metal terminals together through the pair of third openings; and a fourth metal bump disposed on the passivation layer and electrically coupling the pair of fourth metal terminals together through the pair of fourth openings.

9. The apparatus of claim 8, wherein, the first capacitor has a first capacitance value and the second capacitor has a second capacitance value, the first capacitance value being different than the second capacitance value.

10. The apparatus of claim 8, wherein, the first capacitor has a first capacitance value and the second capacitor has a second capacitance value, the first capacitance value being equal to the second capacitance value.

11. The apparatus of claim 8, wherein, the first, second, third, and fourth pairs of terminals each include parallel metal traces extending through the first surface of the semiconductor substrate.

12. The apparatus of claim 8, wherein, the first metal bump, the second metal bump, the third metal bump, and the fourth metal bump are copper pillars configured to be electrically and mechanically coupled to a substrate.

13. The apparatus of claim 8, wherein, the first and third pairs of metal terminals are negative terminals of the first and second capacitors, respectively, and the second and fourth pairs of metal terminals are positive terminals of the first and second capacitors, respectively.

14. The apparatus of claim 13, wherein, at least one metal terminal of the first pair of metal terminals is electrically coupled to at least one metal terminal of the third pair of metal terminals.

15. An apparatus, comprising: including: a semiconductor substrate; a first capacitor disposed on the semiconductor substrate and electrically coupled between a first terminal and a second terminal; a second capacitor disposed on the semiconductor substrate and electrically coupled between a third terminal and a fourth terminal; a passivation layer disposed on a first surface of the semiconductor substrate defining a first opening formed on the first terminal, a second opening formed on the second terminal, a third opening formed on the third terminal, and a fourth opening formed on the fourth terminal; a first metal bump disposed on the passivation layer and electrically coupled to the first terminal and the third terminal through the first opening and the third opening, respectively; and a second metal bump disposed on the passivation layer and electrically coupled to the second terminal and the fourth terminal through the second opening and the fourth opening, respectively.

16. The apparatus of claim 15, wherein, the first capacitor has a first capacitance value and the second capacitor has a second capacitance value, the first capacitance value being different than the second capacitance value.

17. The apparatus of claim 15, wherein, the first capacitor has a first capacitance value and the second capacitor has a second capacitance value, the first capacitance value being equal to the second capacitance value.

18. The apparatus of claim 15, wherein, the first capacitor is coupled in parallel with the second capacitor through the first metal bump and the second metal bump.

19. The apparatus of claim 15, wherein, The first capacitor is coupled in series with the second capacitor through the first metal bump and the second metal bump.

20. The apparatus of claim 15, wherein, The first metal bump and the second metal bump are copper pillars configured to be electrically and mechanically coupled to a substrate.

Images