Semiconductor device and method of manufacturing the same, method of optimizing turn-on voltage kick

Abstract

The application provides a semiconductor device and a manufacturing method thereof, and an optimization method of turn-on voltage bounce. The semiconductor device comprises a first element part and a second element part. The first element part is located on a substrate and is a working area of an insulated gate bipolar transistor. The second element part is located on the substrate and is a working area of a diode. The first element part comprises a first collector region, a first drift region, a first base region, a second base region, at least one first contact region and a plurality of first grooves. The second element part comprises a second collector region, a second drift region, a third base region and a plurality of second grooves. The semiconductor device further comprises a first contact electrode and a second contact electrode. By adjusting the doping type of the polysilicon gate of the FRD region on the reverse-conducting IGBT chip, the anode of the FRD can produce hole injection more quickly, so that the FRD can enter the bipolar conduction state as soon as possible, the turn-on voltage drop is reduced, and the bounce is eliminated.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device, a manufacturing method thereof and an optimization method of turn-on voltage kickback. BACKGROUND

[0002] IGBT (Insulated Gate Bipolar Transistor) has the advantages of high voltage resistance, easy driving control, and strong current carrying capacity, etc., and is known as the "CPU" in the electric energy conversion system, and its rated current level can reach thousands of amperes, and is widely used in new energy vehicles, rail transit, power grid, etc. The structure diagram of trench IGBT is shown in Figure 1 , which includes P+ collector region 1, N+ buffer layer 7, N- drift layer 2, N base region 3, P base region 4, N+ emitter region 5, trench 6, gate oxide layer 6a, first lead electrode 8 and second lead electrode 9. Referring to Figure 1 , the gate is formed by backfilling polysilicon in the trench 6, and N-type impurities such as phosphorus or arsenic are doped into the polysilicon. When a positive voltage is applied to the driving end, the electrons in the polysilicon gate flow out of the gate rapidly, so that the gate is positively charged, and at the same time an N-type inversion layer is formed in the channel outside the gate, realizing the flow of electrons in the channel, which is the working principle of the IGBT forward trench MOS (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET is the abbreviation of Metal-Oxide-Semiconductor Field-Effect Transistor, field effect transistor) structure.

[0003] In order to further increase the power density of the device, a fast recovery diode (FRD) can be integrated into the IGBT chip to form a reverse conducting IGBT (RC-IGBT), and its structure is shown in Figure 2 , in which the IGBT region 10 and the FRD region 20 are separated by the separation line P-P on the trench type reverse conducting IGBT chip, wherein the IGBT region 10 can include P+ collector region 11, N+ buffer layer 17, N- drift layer 12, N base region 13, P base region 14, N+ emitter region 15, trench 16 and gate oxide layer 16a, and the FRD region 20 can include N+ collector region 21, N+ buffer layer 27, N- drift layer 22, N base region 23, P base region 24, trench 26 and gate oxide layer 26a, and the reverse conducting IGBT further includes first lead electrode 80 and second lead electrode 90. The reverse conducting IGBT has the ability of forward conduction and reverse conduction. When forward conduction, the RC-IGBT works in IGBT mode, and when reverse conduction, the RC-IGBT works in FRD mode.

[0004] The reverse conducting IGBT has a series of outstanding advantages: first, the chip cost is saved. Compared with the traditional structure with a chip area ratio of 2:1 between IGBT and FRD, the IGBT and FRD in the reverse conducting IGBT can share the terminal area, and 1 / 3 of the chip area can be saved; second, the high-temperature leakage current is low. Because the main source of the chip high-temperature leakage current is the terminal part, and the reverse conducting IGBT shares the terminal and has a back anode short circuit effect, the high-temperature leakage current is greatly reduced compared with the traditional IGBT chip; third, the chip area is larger, the thermal resistance is lower, the working junction temperature that can be used is higher, and the surge resistance is greatly improved.

[0005] However, the reverse conducting IGBT also introduces some disadvantages due to its structural characteristics. In the static performance aspect, the main performance is the forward and reverse conduction voltage snap-back phenomenon. The test curve of the forward conduction voltage snap-back phenomenon is as shown in Figure 3 When the anode of the IGBT is applied with a forward voltage, the conduction voltage drop will first increase and then suddenly snap back to decrease, and sometimes there will be a secondary snap-back phenomenon, so that the conduction voltage drop curve is not smooth, thereby causing a voltage mutation in the application of the device, which is not conducive to the stability of the circuit system and reduces the usability of the reverse conducting IGBT. Referring to Figure 4A and Figure 4B The principle of the voltage snap-back phenomenon is that because the reverse conducting IGBT has a back anode short circuit area, first, after the front MOS channel is opened, electrons will flow out of the anode from the back N+ area, at this time it is the MOS working mode, and only one kind of carrier works; when the current is large enough, the lateral voltage difference between the back anode n+ area and the p+ area is greater than 0.7V, for example, the PN junction will be turned on, the holes of the anode will be injected into the n- drift area, and the conductance modulation effect will be generated, so that the single-pole conduction is switched to the bipolar conduction state, the MOS working mode is switched to the IGBT working mode, thereby the conduction voltage drop is reduced, and the voltage snap-back is generated. Similarly, when the reverse conducting IGBT is reversely conducted, the device is in the FRD working mode, and the reverse conduction voltage snap-back phenomenon will also be generated, and the principle is similar to the front snap-back. When the front MOS channel is opened, the FRD area is equivalent to the anode being short-circuited, and the holes cannot be injected, at this time the conduction voltage drop is large, and when the current is large enough, the PN junction of the anode of the FRD area is opened, the holes are injected to form the conductance modulation effect, which causes the conduction voltage drop to suddenly decrease, and the voltage snap-back is generated. It also affects the stability of the circuit, brings additional electrical stress impact to the circuit elements, and reduces the application performance of the device.

[0006] Therefore, a scheme is needed to solve the voltage snap-back problem of the reverse conducting IGBT. SUMMARY

[0007] The main purpose of the present application is to provide a semiconductor device and a manufacturing method thereof, and a conduction voltage snap-back optimization method, to solve the voltage snap-back problem of the reverse conducting IGBT.

[0008] The present application provides a semiconductor device, comprising: a first element part, the first element part being located on a substrate, the first element part being an active region of an insulated gate bipolar transistor; and a second element part, the second element part being located on the substrate, the second element part being an active region of a diode; wherein the first element part comprises: a first collector region of a second conductivity type, the first collector region being located on the substrate; a first drift region of a first conductivity type, the first drift region being located above the first collector region; a first base region of the first conductivity type, the first base region being located above the first drift region; a second base region of the second conductivity type, the second base region being located above the first drift region; at least one first contact region of the first conductivity type, the first contact region being located above the second base region, the first contact region having a higher doping concentration than the first base region; a plurality of first trenches, each of the first trenches extending from a surface of the first element part away from the first collector region through the second base region to the first drift region, each of the first trenches being filled with a filling material of the first conductivity type, wherein the at least one first contact region is adjacent to at least one of the first trenches to form a conductive channel in the second base region along the first trench when the insulated gate bipolar transistor is in operation; wherein the second element part comprises: a second collector region of the first conductivity type, the second collector region being located on the substrate; a second drift region of the first conductivity type, the second drift region being located above the second collector region; a third base region of the second conductivity type, the third base region being located above the second drift region; a plurality of second trenches, each of the second trenches extending from a surface of the second element part away from the second collector region through the third base region to the second drift region, the filling material in at least one of the second trenches being different from the filling material in the first trenches to make the second trenches have a lower potential than the first trenches; wherein the semiconductor device further comprises: a first contact electrode, the first contact electrode being electrically connected with the at least one first contact region and the second base region; and a second contact electrode, the second contact electrode being electrically connected with the first collector region and the second collector region.

[0009] In an embodiment, the second element part further comprises: a fourth base region of the first conductivity type, the fourth base region being located above the second drift region.

[0010] In an embodiment, the filling material in the at least one second trench is different from the filling material in the first trenches, comprising: the filling material in the at least one second trench being undoped.

[0011] In an embodiment, the filling material in the at least one second trench is different from the filling material in the first trenches, comprising: the filling material in the at least one second trench being of the second conductivity type.

[0012] In one embodiment, the fill material in the at least one second trench is different from the fill material in the first trench, including: the fill material in the at least one second trench is undoped, and the fill material in the at least one second trench is of the second conductivity type.

[0013] The present application provides a method for manufacturing a semiconductor device, including: forming a first element part on a substrate, the first element part being an active region of an insulated gate bipolar transistor; and forming a second element part on the substrate, the second element part being an active region of a diode; wherein forming the first element part on the substrate includes: forming a first collector region of a second conductivity type on the substrate; forming a first drift region of a first conductivity type above the first collector region; forming a first base region of the first conductivity type above the first drift region; forming a second base region of the second conductivity type above the first drift region; forming at least one first contact region of the first conductivity type above the second base region, the first contact region having a higher doping concentration than the first base region; and forming a plurality of first trenches, each first trench extending from a surface of the first element part away from the first collector region, through the second base region, and to the first drift region, each first trench being filled with a fill material of the first conductivity type, wherein the at least one first contact region is adjacent to at least one first trench to form a conductive channel in the second base region along the first trench when the insulated gate bipolar transistor is in operation; wherein forming the second element part on the substrate includes: forming a second collector region of the first conductivity type on the substrate; forming a second drift region of the first conductivity type above the second collector region; forming a third base region of the second conductivity type above the second drift region; and forming a plurality of second trenches, each second trench extending from a surface of the second element part away from the second collector region, through the third base region, and to the second drift region, the fill material in at least one second trench being different from the fill material in the first trench to make the second trench have a lower potential than the first trench; wherein the method further includes: forming a first contact electrode electrically connected to the at least one first contact region and the second base region; and forming a second contact electrode electrically connected to the first collector region and the second collector region.

[0014] In one embodiment, the fill material in the at least one second trench is different from the fill material in the first trench, the method including: providing a mask above the at least one second trench of the second element part before doping the first trench of the first element part to not dope the fill material in the at least one second trench.

[0015] In an embodiment, the filling material in the at least one second trench is different from the filling material in the first trench, and the method comprises: providing a mask above the at least one second trench of the second element part before doping the first trench of the first element part; and providing a mask above the first trench of the first element part and above the remaining second trenches of the second element part before doping the at least one second trench of the second element part, so as to dope the filling material in the at least one second trench of the second element part into the second conductive type.

[0016] In an embodiment, the filling material in the at least one second trench is different from the filling material in the first trench, and the method comprises: providing a mask above the at least two second trenches of the second element part before doping the first trench of the first element part, so as to not dope the filling material in the at least two second trenches; and providing a mask above the first trench of the first element part and above the remaining second trenches of the at least two second trenches of the second element part before doping the at least one second trench of the at least two second trenches, so as to dope the at least one second trench of the at least two second trenches into the second conductive type.

[0017] The application provides an optimization method for turn-on voltage kickback of a reverse-conducting IGBT chip, comprising: when a first potential is applied to a gate of an IGBT working area of the reverse-conducting IGBT chip, a second potential is applied to a gate of a diode of the reverse-conducting IGBT chip, wherein the second potential is lower than the first potential.

[0018] In an embodiment, the first potential is a positive potential, and the second potential is a negative potential.

[0019] The application improves the FRD anode short circuit condition of the chip at the initial reverse conduction stage by adjusting the doping type and potential connection of the polysilicon gate of the FRD area on the reverse-conducting IGBT chip, so that the FRD anode produces hole injection faster, so that the FRD enters the bipolar conduction state as soon as possible, reduces the turn-on voltage drop, eliminates kickback, makes the turn-on voltage drop curve smooth, is close to the performance of an ordinary IGBT chip, and improves the comprehensive performance of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0020] The drawings accompanying the specification of this application are used to provide a further understanding of the application, the illustrative embodiments of the application and their descriptions serve to explain the application, and do not constitute an improper limitation on the application, in the drawings:

[0021] Figure 1 It is a cross-sectional structure schematic diagram of a trench IGBT in the related art;

[0022] Figure 2 It is a cross-sectional structure schematic diagram of a reverse-conducting IGBT in the related art;

[0023] Figure 3 Fig. 2 is a test curve diagram of the voltage kickback phenomenon when the reverse conducting IGBT is forward conducting in the related art;

[0024] Figure 4A Fig. 3 is a schematic diagram of the principle of the voltage kickback phenomenon when the reverse conducting IGBT is forward conducting in the related art; Figure 4B

[0025] Figure 5 Fig. 5 is a schematic diagram of the relationship between the gate potential of the diode and the kickback voltage in the reverse conducting IGBT;

[0026] Figure 6 Fig. 6 is a schematic diagram of the cross-sectional structure of a semiconductor device according to an exemplary embodiment of the present application;

[0027] Figure 7 Fig. 7 is a schematic diagram of the cross-sectional structure of a semiconductor device according to an exemplary embodiment of the present application;

[0028] Figure 8 Fig. 8 is a schematic diagram of the cross-sectional structure of a semiconductor device according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0029] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0030] According to the above analysis, the reason for the voltage kickback is that there is a unipolar working stage in the initial reverse conducting stage, there are few hole injections in the drift region, the conductive modulation effect is weak, and the anode PN junction reaches the turn-on voltage late. Therefore, the potential difference between the anode PN junction of the FRD can be increased as much as possible to reach the turn-on voltage earlier, so that the reverse conducting IGBT can enter the bipolar conduction state faster.

[0031] Reference Figure 5 Fig. 5 is a schematic diagram of the relationship between the gate potential of the diode and the kickback voltage in the reverse conducting IGBT; Figure 5 As can be seen from Fig. 5, when the IGBT structure parameters such as the N-well dose and the trench spacing are certain, the kickback voltage size and the gate polysilicon potential have a clear positive correlation. From the simulation results, it can also be verified that by reducing the gate polysilicon potential of the diode, the turn-on voltage kickback phenomenon can be effectively suppressed.

[0032] ​The principle of the present application is to increase the potential difference across the anode PN junction of the FRD region of the reverse conducting IGBT, so that the PN junction opens early into the bipolar conduction mode. The specific measures can be to change the potential of the polysilicon in the FRD region trench gate, and the polysilicon in the FRD region trench gate can be undoped or P-type doped, or the FRD region trench gate can be connected to a negative potential, thereby reducing the potential of the polysilicon in the FRD trench gate, which can make it more difficult to form the electron inversion layer in the channel, reduce the channel short circuit effect, and increase the potential difference across the PN junction of the anode of the FRD region, thereby opening earlier to produce hole injection, reduce or even eliminate the voltage kickback when the FRD is turned on, smooth the conduction voltage curve, and improve the usability of the reverse conducting IGBT and the stability of the circuit.

[0033] Figure 6 A cross-sectional structure of a semiconductor device according to an exemplary embodiment of the present application is shown in FIG. 1. Figure 7 A cross-sectional structure of a semiconductor device according to an exemplary embodiment of the present application is shown in FIG. 1. Figure 8 A cross-sectional structure of a semiconductor device according to an exemplary embodiment of the present application is shown in FIG. 1. Figures 6 to 8 In FIG. 1, the reverse conducting IGBT is divided into two cross sections by a vertical cutting line A-A. Although in the present embodiment, the two cross sections are located in the same plane, the two cross sections can not necessarily be placed in the same plane. The region 100 can be referred to as a first element portion, which is an IGBT working region, and the region 200 can be referred to as a second element portion, which is an FRD working region. The IGBT and the FRD are integrated in parallel on the same silicon chip.

[0034] Referring to Figure 6 , the present embodiment provides a semiconductor device, which can include: a first element portion 100 located on a substrate, the first element portion 100 being a working region of an insulated gate bipolar transistor; and a second element portion 200 located on the substrate, the second element portion 200 being a working region of a diode.

[0035] The first element part 100 can include: a first collector region 110 of a second conductivity type, located on the substrate; a first drift region 120 of a first conductivity type, located above the first collector region 110; a first base region 130 of the first conductivity type, located above the first drift region 120; a second base region 140 of the second conductivity type, located above the first drift region 120; at least one first contact region 150 of the first conductivity type, located above the second base region 140, the first contact region 150 having a higher doping concentration than the first base region 130; a plurality of first trenches 160, each first trench 160 extending from a surface of the first element part 100 away from the first collector region 110 through the second base region 140 to the first drift region 120, each first trench 160 being filled with a filling material of the first conductivity type, wherein the at least one first contact region 150 is adjacent to at least one first trench 160 to form a conductive channel in the second base region 140 along the first trench 160 when the insulated gate bipolar transistor is in operation;

[0036] The second element part 200 can include: a second collector region 210 of the first conductivity type, located on the substrate; a second drift region 220 of the first conductivity type, located above the second collector region 210; a third base region 240 of the second conductivity type, located above the second drift region 220; a plurality of second trenches 260, each second trench 260 extending from a surface of the second element part 200 away from the second collector region 210 through the third base region 240 to the second drift region 220, the filling material in at least one second trench 260 being different from the filling material in the first trench 160, so that the second trench 260 has a lower potential than the first trench 160;

[0037] The semiconductor device can further include: a first contact electrode 800 electrically connected to the at least one first contact region 150 and the second base region 140; and a second contact electrode 900 electrically connected to the first collector region 110 and the second collector region 210.

[0038] In this embodiment, the first conductivity type can be N-type, and the second conductivity type can be P-type.

[0039] In this embodiment, the first collector region 110 can be a P+ collector region (located in the IGBT region 100), and the second collector region 210 can be an N+ collector region (located in the FRD region 200). The P+ collector region can supply holes for bipolar conduction in the on state, and the N+ collector region can supply electrons for bipolar conduction in the on state.

[0040] In the embodiment, the first drift region 120 and the second drift region 220 can both be N-drift regions.

[0041] In the embodiment, the first base region 130 can provide an N-well, which can act as a charge storage layer.

[0042] In the embodiment, a dielectric layer 160a can also be included between the first trench 160 and its filling material, and a dielectric layer 260a can also be included between the second trench and its filling material, which can be an oxide layer or the like. The first trench 160 in the IGBT region 100 is an active trench, which is used as a trench gate, and an MOS channel is formed along the trench gate by applying a positive voltage in the on state.

[0043] In an embodiment, the semiconductor device can further include N+ buffer layers 170 and 270 located between the first and second collector regions and the first and second drift regions. The first and second drift regions, the N+ buffer layers 170 and 270, and the second contact electrode can span the IGBT region 100 and the FRD region 200.

[0044] In an embodiment, the second element part 200 can further include a fourth base region 230 of the first conductivity type, which is located above the second drift region 220.

[0045] In an embodiment, with reference to Figure 6 , the filling material in the at least one second trench 260 is different from the filling material in the first trench 160, which can include that the filling material in the at least one second trench 260 is undoped.

[0046] In an embodiment, with reference to Figure 6 The polysilicon of the trench gate of the IGBT region can be N-doped, and the polysilicon of the trench gate of the FRD region is not doped. When a positive voltage signal is applied to the driving end, for example, a 15V positive voltage signal is applied, because the trench gate of the FRD region is not doped, the electron outflow is less, so the potential of the trench gate of the FRD region is much lower than that of the trench gate of the IGBT region, it is more difficult to induce an electron conduction channel in the third base region outside it, and the PN short circuit effect of the anode is weakened, so the anode PN junction of the FRD region can open earlier and produce hole injection to the first drift region, reducing the on-state voltage drop of the FRD. The process implementation method of undoping the polysilicon of the trench gate of the FRD region can be to form a mask on the surface of the FRD region during the doping of the polysilicon in the trench gate of the IGBT region in the chip manufacturing process, so that only the polysilicon of the trench gate of the IGBT region is doped.

[0047] In an embodiment, with reference to Figure 7The filling material in the at least one second trench 260 is different from the filling material in the first trench 160, which can include that the filling material in the at least one second trench 260 is of a second conductivity type.

[0048] In an embodiment, referring to Figure 7 The polysilicon of the trench gate in the IGBT region can be doped with N type, and the polysilicon of the trench gate in the FRD region can be doped with P type. When a positive voltage signal is applied to the driving end, for example, a 15V positive voltage signal, because the trench gate in the FRD region is only doped with P type and has few free electrons, the electrons flowing out of the trench gate are less, and thus the potential of the trench gate is much lower than the potential of the trench gate in the IGBT region, and it is difficult to induce an electron conduction channel in the third base region outside the trench gate, and the PN short circuit effect of the anode is weakened, so that the anode PN junction of the FRD region can be opened earlier and produce hole injection, thereby reducing the on-state voltage drop of the FRD. The process for doping the polysilicon of the trench gate in the FRD region with P type can include: in the chip manufacturing process, a mask is formed on the surface of the FRD region before the polysilicon of the trench gate in the IGBT region is doped, so that only the polysilicon of the trench gate in the IGBT region is doped with N type; then the mask on the surface of the FRD region is removed, and a mask is formed on the surface of the IGBT region, and the polysilicon of the trench gate in the FRD region is doped with P type, thereby forming two trench gates with opposite conductivity types. The scheme of the present embodiment can make the short circuit effect of the anode of the FRD region weaker, open the PN junction earlier, and make the on-state voltage drop curve smoother.

[0049] In an embodiment, referring to Figure 8 The filling material in the at least one second trench 260 is different from the filling material in the first trench 160, which can include that the filling material in the at least one second trench 260 is of a second conductivity type.

[0050] In an embodiment, referring to Figure 8 The polysilicon of the trench gate in the FRD region can be doped with mixed doping, for example, part of the polysilicon of the trench gate can be undoped, part of the polysilicon of the trench gate can be doped with N type, and part of the polysilicon of the trench gate can be doped with P type. The order of mixed doping includes but is not limited to that shown in Figure 8 The process for realizing the mixed doping of the present embodiment can include that the trench gate region of the FRD is divided into two times of doping of the polysilicon. The scheme of the present embodiment can adjust the potential of the trench gate of the FRD in a larger range as needed, and realize the device performance meeting the design requirements.

[0051] The embodiment provides a semiconductor device manufacturing method, which can include: forming a first element part on a substrate, the first element part being an operating area of an insulated gate bipolar transistor; and forming a second element part on the substrate, the second element part being an operating area of a diode.

[0052] The forming the first element part on the substrate includes: forming a first collector region of a second conductivity type on the substrate; forming a first drift region of a first conductivity type above the first collector region; forming a first base region of the first conductivity type above the first drift region; forming a second base region of a second conductivity type above the first drift region; forming at least one first contact region of the first conductivity type above the second base region, the at least one first contact region having a higher doping concentration than the first base region; and forming a plurality of first trenches, each of the first trenches extending from a surface of the first element part away from the first collector region, through the second base region, and to the first drift region, each of the first trenches being filled with a filling material of the first conductivity type, wherein the at least one first contact region is adjacent to at least one of the first trenches to form a conductive channel in the second base region along the at least one of the first trenches when the insulated gate bipolar transistor operates.

[0053] The forming the second element part on the substrate includes: forming a second collector region of the first conductivity type on the substrate; forming a second drift region of the first conductivity type above the second collector region; forming a third base region of the second conductivity type above the second drift region; and forming a plurality of second trenches, each of the second trenches extending from a surface of the second element part away from the second collector region, through the third base region, and to the second drift region, the filling material in at least one of the second trenches being different from the filling material in the first trenches to make the at least one of the second trenches have a lower potential than the first trenches.

[0054] The method further includes: forming a first contact electrode electrically connected to the at least one first contact region and the second base region; and forming a second contact electrode electrically connected to the first collector region and the second collector region.

[0055] In an embodiment, the filling material in the at least one second trench is different from the filling material in the first trenches, and the method can include: providing a mask above the at least one second trench of the second element part before doping the first trenches of the first element part, so as to not dope the filling material in the at least one second trench.

[0056] In an embodiment, the filling material in the at least one second trench is different from the filling material in the first trench, and the method can comprise: providing a mask above the at least one second trench of the second element part before doping the first trench of the first element part; providing a mask above the first trench of the first element part and above the remaining second trenches of the second element part before doping the at least one second trench of the second element part, so as to dope the filling material in the at least one second trench of the second element part into the second conductive type.

[0057] In an embodiment, the filling material in the at least one second trench is different from the filling material in the first trench, and the method can comprise: providing a mask above the at least one second trench of the second element part before doping the first trench of the first element part; providing a mask above the first trench of the first element part and above the remaining second trenches of the second element part before doping the at least one second trench of the second element part, so as to dope the filling material in the at least one second trench of the second element part into the second conductive type.

[0058] The embodiment provides an optimization method for turn-on voltage kickback of reverse-conducting IGBT chips, which can comprise: when a first potential is applied to a gate of an IGBT working area of the reverse-conducting IGBT chip, a second potential is applied to a gate of a diode of the reverse-conducting IGBT chip, wherein the second potential is lower than the first potential.

[0059] In an embodiment, the first potential is a positive potential, and the second potential is a negative potential.

[0060] In an embodiment, the first potential is a positive potential, and the second potential is a negative potential. Figure 6 The polycrystalline silicon of the IGBT area trench gate can be doped with N type, and the polycrystalline silicon of the FRD area trench gate is forced to be applied with a negative potential. When the polycrystalline silicon of the FRD area trench gate is applied with a negative potential, a hole inversion layer is induced in the third base area outside the polycrystalline silicon, and the PN short circuit effect of the anode is weakened, so that the anode PN junction of the FRD area can be opened earlier and produce hole injection, thereby reducing the on-voltage drop of the FRD. The implementation mode that the polycrystalline silicon of the FRD area trench gate is applied with a negative potential can be that the polycrystalline silicon of the FRD area trench gate is connected to the negative terminal of a capacitor or the like.

[0061] The present application adjusts the doping type and potential connection of the polycrystalline silicon gate of the FRD area on the reverse-conducting IGBT chip,

[0062] To improve the FRD anode short circuit condition in the initial reverse conduction of the chip, let the FRD anode produce hole injection faster, so as to make the FRD enter the bipolar conduction state as soon as possible, reduce the on-voltage drop, eliminate the back jump, make the on-voltage drop curve smooth, close to the performance of ordinary IGBT chip, and improve the comprehensive performance of the chip.

[0063] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used in this specification and the appended claims, the terms "comprise", "comprising", "include", "including", "contain", "containing" or variations thereof, do not specify an exhaustive or exhaustive list of elements or steps.

[0064] It should be noted that the terms "first", "second", "third", etc. in the specification and claims of the present application and the drawings are used to distinguish similar objects, and are not intended to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0065] It should be noted that the terms "first", "second", "third", etc. in the specification and claims of the present application and the drawings are used to distinguish similar objects, and are not intended to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0066] 5It should be understood that the exemplary embodiments in the specification can be implemented in various forms,

[0067] and should not be interpreted as being limited to the embodiments set forth herein. These embodiments are provided so that the disclosure of the present application is complete and complete, and the concepts of these exemplary embodiments are fully conveyed to those skilled in the art, and should not be understood as limiting the invention.

Claims

1. A semiconductor device, characterized by, Comprising: a first element portion on a substrate, the first element portion being an active region of an insulated gate bipolar transistor; and a second element portion on the substrate, the second element portion being an active region of a diode; wherein the first element portion comprises: a first collector region of a second conductivity type on a substrate; a first drift region of a first conductivity type over the first collector region; a first base region of the first conductivity type over the first drift region; a second base region of a second conductivity type over the first drift region; at least one first contact region of the first conductivity type over the second base region, the first contact region having a higher doping concentration than the first base region; a plurality of first trenches each extending through the second base region from a surface of the first element portion away from the first collector region to the first drift region, each of the first trenches being filled with a first conductivity type filling material, wherein at least one of the first contact regions is adjacent to at least one of the first trenches to form a conductive channel in the second base region along the first trenches when the insulated gate bipolar transistor is in operation; wherein the second element portion comprises: a second collector region of the first conductivity type on the substrate; a second drift region of the first conductivity type over the second collector region; a third base region of the second conductivity type over the second drift region; a plurality of second trenches each extending through the third base region from a surface of the second element portion away from the second collector region to the second drift region, the filling material in at least one of the second trenches being different from the filling material in the first trenches to cause the second trenches to have a lower potential than the first trenches; wherein the semiconductor device further comprises: a first contact electrode electrically connected to at least one of the first contact regions and the second base region; a second contact electrode electrically connected to the first collector region and the second collector region.

2. The semiconductor device according to claim 1, wherein the second element portion further comprises: a fourth base region of the first conductivity type over the second drift region.

3. The semiconductor device of claim 1, wherein the filling material in at least one of the second trenches being different from the filling material in the first trenches comprises: the filling material in at least one of the second trenches being undoped.

4. The semiconductor device of claim 1, wherein the filling material in at least one of the second trenches being different from the filling material in the first trenches comprises: the filling material in at least one of the second trenches being of the second conductivity type.

5. The semiconductor device of claim 1, wherein the filling material in at least one of the second trenches being different from the filling material in the first trenches comprises: the filling material in at least one of the second trenches being undoped, and the filling material in at least one of the second trenches being of the second conductivity type.

6. A method of manufacturing a semiconductor device, characterized by Comprising: forming a first element portion on a substrate, the first element portion being an active region of an insulated gate bipolar transistor; and forming a second element portion on the substrate, the second element portion being an active region of a diode; wherein forming a first element portion on a substrate, comprising: forming a first collector region of a second conductivity type on the substrate; forming a first drift region of a first conductivity type over the first collector region; forming a first base region of the first conductivity type over the first drift region; forming a second base region of a second conductivity type over the first drift region; forming at least one first contact region of the first conductivity type over the second base region, the first contact region having a higher doping concentration than the first base region; forming a plurality of first trenches, each of the first trenches extending from a surface of the first element portion away from the first collector region through the second base region to the first drift region, each of the first trenches being filled with a filling material of the first conductivity type, wherein at least one of the first contact regions is adjacent to at least one of the first trenches to form a conductive channel in the second base region along the first trenches when the insulated gate bipolar transistor is in operation; wherein forming a second element portion on the substrate comprises: forming a second collector region of the first conductivity type on the substrate; forming a second drift region of the first conductivity type over the second collector region; forming a third base region of the second conductivity type over the second drift region; forming a plurality of second trenches, each of the second trenches extending from a surface of the second element portion away from the second collector region through the third base region to the second drift region, the filling material in at least one of the second trenches being different from the filling material in the first trenches to cause the second trenches to have a lower potential than the first trenches; wherein the method further comprises: forming a first contact electrode electrically connected to at least one of the first contact regions and the second base region; forming a second contact electrode electrically connected to the first collector region and the second collector region.

7. The method of manufacturing a semiconductor device according to claim 6, wherein The filling material in at least one of the second trenches is different from the filling material in the first trenches, the method comprising: providing a mask over at least one of the second trenches of the second element portion before doping the first trenches of the first element portion to not dope the filling material in at least one of the second trenches.

8. The method of manufacturing a semiconductor device according to claim 6, wherein The filling material in at least one of the second trenches is different from the filling material in the first trenches, the method comprising: providing a mask over at least one of the second trenches of the second element portion before doping the first trenches of the first element portion. A mask is provided over the first trench of the first element portion and over the remaining second trenches of the second element portion to dope the fill material in the at least one second trench of the second element portion to the second conductivity type before doping the at least one second trench of the second element portion.

9. The method of manufacturing a semiconductor device according to claim 6, wherein The fill material in the at least one second trench is different from the fill material in the first trench, and the method comprises: A mask is provided over the at least two second trenches of the second element portion to not dope the fill material in the at least two second trenches before doping the first trench of the first element portion; A mask is provided over the first trench of the first element portion and over the remaining second trenches of the second element portion to dope the at least one second trench of the at least two second trenches to the second conductivity type before doping the at least one second trench of the at least two second trenches.

10. A method of optimizing the turn-on voltage kick of a semiconductor device as claimed in any one of claims 1 to 5, characterized in that, Comprises: A second electric potential is applied to the gate of the diode of the semiconductor device when a first electric potential is applied to the gate of the operating region of the insulated gate bipolar transistor of the semiconductor device, wherein the second electric potential is lower than the first electric potential.

11. The optimization method of claim 10, wherein, The first electric potential is a positive electric potential and the second electric potential is a negative electric potential.

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