Array substrate, manufacturing method of array substrate, display panel and display

Abstract

The application discloses an array substrate, a manufacturing method of the array substrate, a display panel and a display. The array substrate comprises a substrate, a pixel electrode, a common electrode and at least two thin film transistors. The substrate comprises a display area and a non-display area surrounding the display area. The at least two thin film transistors are arranged in the display area and the non-display area respectively. The thin film transistor comprises a gate electrode, a semiconductor layer arranged below the gate electrode, a first insulating layer arranged between the gate electrode and the semiconductor layer, a source electrode and a drain electrode connected to the semiconductor layer. The projection of the gate electrode on the substrate, the projection of the source electrode on the substrate and the projection of the drain electrode on the substrate do not coincide. The pixel electrode is electrically connected to the source electrode or the drain electrode of the thin film transistor in the display area. The first conductor part of the common electrode is arranged opposite to the pixel electrode in the direction perpendicular to the substrate and is arranged in the same layer as the semiconductor layer. The first conductor part is formed by the semiconductor through the conductorization. The display panel can realize the effects of high refresh rate and wide viewing angle simultaneously.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate, a manufacturing method of the array substrate, a display panel using the array substrate and a display using the display panel. BACKGROUND

[0002] With the development of display panel technology, the demand of users for display panels gradually increases.

[0003] The application of DEMUX (demultiplexer) switching circuit can reduce the number of output channels of the driving chip, thereby reducing the cost, but the DEMUX switching circuit needs to use a thin film transistor structure with extremely small parasitic capacitance. The top gate thin film transistor in the common structure of the thin film transistor can achieve extremely small parasitic capacitance, thereby achieving the effect of high resolution and high refresh rate. The FFS (Fringe Field Switching) display panel has the characteristics of high transmittance and wide viewing angle. The pixel electrode and the common electrode in the FFS display panel need to be arranged on different layers of the array substrate. The traditional display panel only has the DEMUX switching circuit or the FFS display panel structure, and does not have the advantages of both. SUMMARY

[0004] The main purpose of the present application is to provide an array substrate which has the common advantages of DEMUX switching circuit and FFS display panel.

[0005] To achieve the above purpose, the array substrate provided by the present application comprises a substrate and a thin film transistor. The substrate comprises a display area and a non-display area surrounding the display area. The thin film transistor is provided with at least two, and the at least two thin film transistors are arranged in the display area and the non-display area respectively. The thin film transistor comprises a gate, a first insulating layer, a semiconductor layer, a source and a drain which are arranged in layers. The first insulating layer is arranged between the gate and the semiconductor layer, and the source and the drain are connected to the semiconductor layer. The gate is arranged above the semiconductor layer, and the projection of the gate on the substrate, the projection of the source on the substrate and the projection of the drain on the substrate do not coincide. The array substrate further comprises a pixel electrode and a common electrode. The pixel electrode is electrically connected to the source or the drain of the thin film transistor in the display area. The common electrode comprises a first conductor part which is arranged opposite to the pixel electrode in the direction perpendicular to the substrate and is arranged in the same layer as the semiconductor layer. The first conductor part is formed by conductorization of the semiconductor.

[0006] In an embodiment, the array substrate further comprises a second insulating layer, the second insulating layer is arranged on the side of the gate away from the substrate, and the pixel electrode is arranged on the side of the second insulating layer away from the substrate.

[0007] In an embodiment, the common electrode further comprises a second conductor part, the second conductor part is arranged on the side of the first conductor part away from the substrate.

[0008] In an embodiment, the second conductor part is arranged in the same layer as the gate.

[0009] In an embodiment, the source and the drain are both arranged in the same layer as the gate and are respectively arranged on the two sides of the gate; the first insulating layer has a first via hole and a second via hole, and the source and the drain are respectively connected with the semiconductor layer through the first via hole and the second via hole.

[0010] In an embodiment, the part of the semiconductor layer corresponding to the first via hole forms a first connecting part, and the part of the semiconductor layer corresponding to the second via hole forms a second connecting part, and the first connecting part and the second connecting part are both formed into conductors through conductorization.

[0011] The application further provides a manufacturing method of an array substrate, the manufacturing method of the array substrate is based on the above array substrate, and the manufacturing method of the array substrate comprises the following steps:

[0012] The substrate comprises a display area and a non-display area, the display area comprises an opening area and a pixel switch area, a semiconductor layer is plated on one side of the substrate, and the semiconductor layer is subjected to a patterning process;

[0013] A first insulating layer is plated on the side of the semiconductor layer away from the substrate, the first insulating layer is subjected to a patterning process, and the part of the first insulating layer corresponding to the opening area is etched to expose the opposite part of the semiconductor layer corresponding to the opening area; and the part of the first insulating layer corresponding to the pixel switch area and the non-display area is etched to form two communication holes, so that the part of the semiconductor layer corresponding to the two communication holes is exposed to form a first connecting part and a second connecting part;

[0014] The exposed opposite part is subjected to a conductorization process to form a common electrode, and the exposed first connecting part and second connecting part are subjected to a conductorization process.

[0015] A metal layer is plated on the side of the first insulating layer facing away from the substrate, and the metal layer is patterned to include a source electrode, a drain electrode and a gate electrode that are isolated from each other, wherein the source electrode and the drain electrode are in contact with the first connecting portion and the second connecting portion respectively, and the gate electrode is arranged corresponding to the portion of the semiconductor layer that is not conductorized.

[0016] A pixel electrode is arranged, and the pixel electrode and the common electrode are arranged in different layers and are insulated.

[0017] In an embodiment, the step of arranging the pixel electrode and the common electrode in different layers and insulating them comprises:

[0018] A second insulating layer is plated on the side of the metal layer facing away from the substrate, and the second insulating layer is patterned to form a via capable of exposing the source electrode or the drain electrode;

[0019] A pixel electrode is plated on the side of the second insulating layer facing away from the substrate, and the pixel electrode is deposited on the source electrode or the drain electrode through the via.

[0020] The application further provides a display panel, comprising an array substrate, a liquid crystal and the array substrate, the array substrate is arranged opposite to the array substrate, and the array substrate faces the pixel electrode, and the liquid crystal is arranged between the array substrate and the array substrate.

[0021] The application further provides a display, comprising a backlight module and the display panel, and the backlight module is arranged on the light-incident side of the array substrate.

[0022] The technical solution of this invention, by placing the gate above the semiconductor layer, enables the thin-film transistor (TFT) to form a top-gate structure, thereby reducing the size of the TFT and increasing the aperture ratio. Furthermore, by ensuring that the projections of the gate, source, and drain onto the substrate are not coincident, the parasitic capacitance of the TFT is extremely small or negligible, thus meeting the requirements of the DEMUX switching circuit and achieving high resolution and high refresh rate. Additionally, the array substrate of this invention includes pixel electrodes and a common electrode disposed on the substrate. The pixel electrodes are connected to the drain or source of the TFT and are positioned opposite to the first conductor portion of the common electrode in the direction perpendicular to the substrate. This allows the array substrate to simultaneously provide pixel electrodes and a common electrode, which are on different layers, thus meeting the requirements of FFS display panels and achieving wide viewing angles and high transmittance. Furthermore, since the first conductor portion is formed by semiconductor through conductor formation, the first conductor portion of the common electrode can be simultaneously formed with the semiconductor layer located below the gate in one process before being conductor formed. That is, the semiconductor layer can be deposited on the substrate so that the semiconductor layer is at least partially located below the pixel electrode, and then the portion located below the pixel electrode can be conductor formed. This avoids the need to set up a separate conductive layer independent of the semiconductor layer as the common electrode, further reducing the number of process steps and saving costs. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the structure of an array substrate according to Embodiment 1 of the present invention;

[0025] Figure 2 This is a schematic diagram of the process structure for fabricating an array substrate according to Embodiment 2 of the present invention;

[0026] Figure 3 This is a schematic flowchart of the method for fabricating an array substrate according to Embodiment 2 of the present invention;

[0027] Figure 4 This is a detailed flowchart illustrating step 50 of the method for fabricating an array substrate according to Embodiment 2 of the present invention.

[0028] Figure 5 This is a schematic diagram of the structure of a display panel according to Embodiment 3 of the present invention;

[0029] Figure 6 Fig. 4 is a structural schematic diagram of an embodiment of the display of embodiment four of the present application.

[0030] Brief Description of the Drawings

[0031]

[0032] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0034] It should be noted that if the embodiments of the present application involve directionality indication (such as up, down, left, right, front, back, etc.), the directionality indication is only used to explain the relative position relationship, movement condition, etc. between components in a certain specific posture (as shown in the drawings). If the specific posture changes, the directionality indication also changes accordingly.

[0035] In addition, if the embodiments of the present application involve the description of "first", "second", etc., the description of "first", "second", etc. is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the fact that a person skilled in the art can realize it. When the combination of technical solutions contradicts each other or cannot be realized, it should be considered that the combination of technical solutions does not exist and is not within the protection scope of the present application.

[0036] Embodiment one:

[0037] The present application provides an array substrate 100.

[0038] In the embodiments of the present application, as Figure 1As shown in the figure, the array substrate 100 comprises a substrate 110 and a thin film transistor 120; the substrate 110 comprises a display area 101 and a non-display area 102 surrounding the display area 101; the thin film transistor 120 is provided at least two, and the at least two thin film transistors 120 are respectively arranged in the display area 101 and the non-display area 102; the thin film transistor 120 comprises a gate 123, a first insulating layer 122, a semiconductor layer 121, a source 124 and a drain 125 arranged in layers, the first insulating layer 122 is arranged between the gate 123 and the semiconductor layer 121, and the source 124 and the drain 125 are both connected to the semiconductor layer 121; the gate 123 is arranged above the semiconductor layer 121, and the projection of the gate 123 on the substrate 110, the projection of the source 124 on the substrate 110 and the projection of the drain 125 on the substrate 110 do not coincide; the array substrate 100 further comprises a pixel electrode 140 and a common electrode 150, the pixel electrode 140 is electrically connected to the source 124 or the drain 125 of the thin film transistor 120 located in the display area 101; the common electrode 150 comprises the first conductor part 152, the first conductor part 152 is arranged opposite to the pixel electrode 140 in the direction perpendicular to the substrate 110, and is arranged in the same layer as the semiconductor layer 121, and the first conductor part 152 is formed by the semiconductor through conductorization.

[0039] The substrate 110 of the array substrate 100 comprises a display area 101 and a non-display area 102 surrounding the display area 101, wherein the display area 101 is used to display a picture for a user to watch; the non-display area 102 is arranged at the periphery of the display picture, so that some driving chips, DEMUX switching circuits and other structures can be arranged, avoiding affecting the display picture of the display area 101 by shielding the picture passing through the display area 101. In order to make the non-display area 102 not form an image, a light shielding layer 160 can be arranged at the position of the non-display area 102 of the substrate 110, and the light shielding layer 160 can be a metal light shielding layer 160 or an inorganic material. In the DEMUX switching circuit, a thin film transistor 120 with extremely small parasitic capacitance needs to be arranged, and in the present application, the thin film transistor 120 is arranged in the non-display area 102 and the display area 101, and the thin film transistor 120 comprises a gate 123, a first insulating layer 122, a semiconductor layer 121, a source 124 and a drain 125, wherein the first insulating layer 122 is arranged between the semiconductor layer 121 and the gate 123, so as to avoid the short circuit phenomenon between the gate 123 and the semiconductor layer 121. In the present application, the gate 123 is arranged above the semiconductor layer 121, so that the structure of the thin film transistor 120 in the present application is a top gate 123 structure, so that the size of the thin film transistor 120 can be smaller than that of the bottom gate 123 structure, the space occupied by the thin film transistor 120 on the substrate 110 is reduced, and the aperture ratio is further improved. In addition, the projection of the gate 123 on the substrate 110, the projection of the drain 125 on the substrate 110 and the projection of the source 124 on the substrate 110 do not overlap, so that the parasitic capacitance of the thin film transistor 120 in the present application is extremely small or can be ignored, so that the effects of high resolution and high refresh rate can be achieved. The thin film transistor 120 with the top gate 123 structure in the present application refers to the gate 123 being above the semiconductor layer 121, and the "above" in the present application refers to the direction from the substrate 110 to the semiconductor layer 121. Specifically, the drain 125 and the source 124 of the thin film transistor 120 in the present application can be below the gate 123, and further, the drain 125 and the source 124 can be below the semiconductor layer 121, so that the thin film transistor 120 in the present application has two metal layers. Alternatively, the drain 125 and the source 124 of the thin film transistor 120 in the present application can be above the gate 123, and the source 124 and the drain 125 are both connected to the semiconductor layer 121, and the source 124 and the drain 125 are both insulated from the gate 123, that is, an insulating layer is arranged between the source 124 and the drain 125 to isolate the gate 123.Alternatively, the drain 125, the source 124 or the gate 123 of the thin film transistor 120 in the present application can be arranged in the same layer, as long as the source 124 and the drain 125 are both connected to the semiconductor layer 121 and are both insulated from the gate 123. In this way, the total number of layers in which the thin film transistor 120 is arranged can be reduced, and the manufacturing process can be reduced. It should be noted that the thin film transistor 120 in the display area 101 and the non-display area 102 in the present application has the same structure, thereby reducing the process procedure. When the thin film transistor 120 in the display area 101 and the thin film transistor 120 in the non-display area 102 in the present application both adopt the above structure, the effect of reducing parasitic capacitance is achieved, thereby achieving the effects of high resolution and high refresh rate; and the thin film transistor 120 in the display area 101 and the thin film transistor 120 in the non-display area 102 can both have a small occupied size, thereby improving the aperture ratio.

[0040] In addition, the array substrate 100 in the present application further includes a pixel electrode 140 and a common electrode 150. The pixel electrode 140 is connected to the source 124 or the drain 125 of the thin film transistor 120 in the display area 101, thereby enabling the pixel electrode 140 to be powered through the thin film transistor 120, and further controlling the display brightness of the display picture at the corresponding pixel electrode 140 in the display area 101. By oppositely arranging the first conductor part 152 of the common electrode 150 with the pixel electrode 140, the common action of the pixel electrode 140 and the common electrode 150 can control the deflection of the liquid crystal 300 arranged between the array substrate 100 and the opposite substrate 200, and further control the light emitting angle and brightness. The first conductor part 152 in the present application is formed by semiconductor conduction, and the first conductor part 152 is arranged in the same layer as the semiconductor layer 121. Therefore, the first conductor part 152 can be arranged together with the semiconductor layer 121 arranged below the gate 123, that is, the effect of oppositely arranging at least part of the semiconductor with the pixel electrode 140 can be achieved through the process of plating the semiconductor layer 121 once, and further only the part of the semiconductor opposite to the pixel electrode 140 needs to be conducted, thereby enabling at least part of the common electrode 150 to be arranged in the same layer as the semiconductor layer 121, reducing the process procedure, saving the cost, and simplifying the structure of the array substrate 100 and reducing the thickness. Specifically, when the pixel electrode 140 is oppositely arranged with the common electrode 150, the pixel electrode 140 can be arranged above the common electrode 150 or below the common electrode 150, as long as the effect of enabling the pixel electrode 140 to be connected to the source 124 or the drain 125 of the thin film transistor 120 in the display area 101 and oppositely arranged with the common electrode 150 is achieved.

[0041] The thin film transistor 120 in the present application forms a top gate 123 structure, so that the size of the thin film transistor 120 is reduced and the aperture ratio is improved. On the other hand, the projection of the gate 123 on the substrate 110, the projection of the source 124 on the substrate 110 and the projection of the drain 125 on the substrate 110 do not overlap, so that the parasitic capacitance of the thin film transistor 120 in the present application is extremely small or negligible, so as to meet the requirements of the DEMUX switching circuit and realize the effect of high resolution and high refresh rate. In addition, the array substrate 100 in the present application further comprises a pixel electrode 140 and a common electrode 150 arranged on the substrate 110. The pixel electrode 140 is connected with the drain 125 or the source 124 of the thin film transistor 120 and is arranged opposite to the first conductor part 152 of the common electrode 150 in the vertical direction of the substrate 110. Therefore, the array substrate 100 in the present application simultaneously arranges the pixel electrode 140 and the common electrode 150, and the pixel electrode 140 and the common electrode 150 are in different layers, so as to meet the requirements of the FFS display panel and realize the effects of wide viewing angle and high transmittance. Further, the first conductor part 152 is formed by semiconductor conductorization. Before the first conductor part 152 of the common electrode 150 is conductorized, the semiconductor layer 121 located below the gate 123 can be arranged simultaneously through one process. That is, the semiconductor layer 121 is plated on the substrate 110, so that the semiconductor layer 121 is at least partially located below the pixel electrode 140, and then the part below the pixel electrode 140 is conductorized, so as to avoid arranging another conductive layer independent of the semiconductor layer 121 as the common electrode 150, further reduce the process procedure and save the cost.

[0042] In an embodiment, as shown in Figure 1 The array substrate 100 further comprises a second insulating layer 130 arranged on the side of the gate 123 away from the substrate 110, and the pixel electrode 140 is arranged on the side of the second insulating layer 130 away from the substrate 110.

[0043] The second insulating layer 130 is arranged on the side of the gate 123 away from the substrate 110, and the pixel electrode 140 is arranged on the side of the second insulating layer 130 away from the substrate 110, so that the pixel electrode 140 is closer to the source 124 or the drain 125 arranged in the same layer as the gate 123, and the pixel electrode 140 is conveniently connected to the source 124 or the drain 125.

[0044] In an embodiment, as shown in Figure 1 The common electrode 150 further comprises a second conductor part arranged on the side of the first conductor part 152 away from the substrate 110.

[0045] By setting the second conductor part, the common electrode 150 is facilitated to be connected with the external circuit, so that the conductive effect of the common electrode 150 with the external circuit is better. Specifically, when the second conductor part of the common electrode 150 is set on the side of the first conductor part 152 away from the substrate 110, the second conductor part of the common electrode 150 can be set in the same layer as the gate 123 or can be set in different layers from the gate 123, as long as the effect that the second conductor part can be connected with the first conductor part 152 can be achieved.

[0046] In an embodiment, as shown in Figure 1 the second conductor part is set in the same layer as the gate 123.

[0047] By setting the second conductor part on the side of the first conductor part 152 away from the substrate 110 and setting the second conductor part in the same layer as the gate 123, the setting of the gate 123 and the second conductor part of the common electrode 150 can be completed at the same time through only one process, so that the process technology is simplified and the cost is saved. In addition, when the second conductor part is set in the same layer as the gate 123 and is made at the same time through the same process, the second conductor part is also metal, and the setting of the second conductor part can make the first conductor part 152 better connected with the external circuit more stable.

[0048] In an embodiment, as shown in Figure 1 the source 124 and the drain 125 are both set in the same layer as the gate 123 and are respectively set on the two sides of the gate 123; the first insulating layer 122 has a first via hole and a second via hole, and the source 124 and the drain 125 are respectively connected with the semiconductor layer 121 through the first via hole and the second via hole.

[0049] By setting the source 124 and the drain 125 in the same layer as the gate 123 and respectively on the two sides of the gate 123, the source 124, the gate 123 and the drain 125 can be made at the same time through the same process, so that the process technology is simplified and the cost is saved, and at the same time, the size of the thin film transistor 120 can be reduced, the aperture ratio can be increased, and the effects of high refresh rate and high resolution can be achieved. In addition, by patterning the first insulating layer 122 to form the first via hole and the second via hole, the source 124 and the drain 125 are respectively connected with the semiconductor layer 121 through the first via hole and the second via hole, so that when the source 124 and the drain 125 are set in the same layer as the gate 123, the effect of being connected with the semiconductor layer 121 can still be guaranteed.

[0050] Further, as shown in Figure 1As shown, the semiconductor layer 121 corresponds to the first via hole to form a first connecting part 1211, and the semiconductor layer 121 corresponds to the second via hole to form a second connecting part 1212, and the first connecting part 1211 and the second connecting part 1212 are both formed by conductors.

[0051] By forming the first connecting part 1211 by the semiconductor layer 121 corresponding to the first via hole, and forming the second connecting part 1212 by the semiconductor layer 121 corresponding to the second via hole, the effect that the source 124 is connected to the first connecting part 1211 and the drain 125 is connected to the second connecting part 1212 is facilitated. In addition, by forming the first connecting part 1211 and the second connecting part 1212 into conductors, the impedance between the source 124 and the drain 125 is reduced, ensuring a large on-state current and high mobility.

[0052] Embodiment two:

[0053] The application also provides a manufacturing method of the array substrate 100, as shown in Figure 2 and Figure 3 The specific structure of the array substrate 100 in the manufacturing method of the array substrate 100 is referred to the above-mentioned embodiments. Since the manufacturing method of the array substrate 100 adopts all the technical solutions of the above-mentioned embodiments, it at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here. The manufacturing method of the array substrate 100 includes:

[0054] Step 10: The substrate 110 includes a display area 101 and a non-display area 102, the display area 101 includes an opening area 1011 and a pixel switch area 1012, a semiconductor layer 121 is plated on one side of the substrate 110, and the semiconductor layer 121 is patterned.

[0055] By plating the semiconductor layer 121 on one side of the substrate 110 and patterning the semiconductor layer 121, the thin film transistor 120 can be prepared on one side of the substrate 110. Specifically, when the semiconductor layer 121 is patterned, it can usually be realized by a photolithography process, so that the final semiconductor pattern shape can be realized at one time, so as to plate other film layers on the side of the semiconductor layer 121 away from the substrate 110 to form a plurality of thin film transistors 120.

[0056] Before plating the semiconductor layer 121 on one side of the substrate 110, the substrate 110 can be divided into the display area 101 and the non-display area 102 surrounding the display area 101, and the display area 101 can be further divided into a plurality of pixel units, each of which includes a region corresponding to the pixel electrode 140, i.e., the opening area 1011, and each of which also includes a region corresponding to the thin film transistor 120, i.e., the pixel switch area 1012. The semiconductor layer 121 can be plated on the display area 101 and the non-display area 102 at the same time, and the semiconductor layer 121 can be plated on the display area 101 corresponding to the opening area 1011, the pixel switch area 1012, and the non-display area 102. The semiconductor layer 121 mainly serves as a part of the thin film transistor 120, and the thin film transistor 120 is provided in both the non-display area 102 and the display area 101. In order to avoid light leakage in the region where the thin film transistor 120 is provided in the non-display area 102 and the display area 101, a light shielding layer 160 can be plated on the pixel switch area 1012 corresponding to the non-display area 102 and the display area 101 before plating the semiconductor layer 121. The light shielding layer 160 can be metal or inorganic material, as long as it can shield light. Further, an isolation layer 170 can be plated on the side of the light shielding layer 160 away from the substrate 110, so as to avoid electrical connection between the semiconductor layer 121 and the light shielding layer 160 when the light shielding layer 160 is metal, or to achieve a dense effect when the light shielding layer 160 is inorganic material.

[0057] Step 20: Plate a first insulating layer 122 on the side of the semiconductor layer 121 away from the substrate 110, and patternize the first insulating layer 122, and etch the part of the first insulating layer 122 corresponding to the opening area 1011, so that the semiconductor layer 121 corresponding to the opening area 1011 is exposed; and also etch the part of the first insulating layer 122 corresponding to the pixel switch area 1012 and the non-display area 102 to form two communication holes, so that the part of the semiconductor layer 121 corresponding to the two communication holes is exposed, to form a first connection part 1211 and a second connection part 1212.

[0058] By plating the first insulating layer 122 on the side of the semiconductor layer 121 away from the substrate 110, the gate 123 of the thin film transistor 120 of the top gate 123 structure can be easily isolated from the semiconductor layer 121 to prevent the gate 123 from being electrically connected to the semiconductor layer 121. At the same time, by patterning the first insulating layer 122, the portions of the first insulating layer 122 corresponding to the pixel switching region 1012 and the non-display region 102 are etched to form two communication holes, so that the first insulating layer 122 has a via structure, and the portions of the semiconductor layer corresponding to the communication holes are exposed, which facilitates the connection of the source 124 and the drain 125 to the semiconductor layer 121 by passing through the first insulating layer 122. In addition, by etching the portion of the first insulating layer 122 corresponding to the opening region 1011, the portion of the semiconductor layer 121 corresponding to the opening region, i.e. the portion corresponding to the pixel electrode 140, is exposed to form an opposite part, which is further facilitated to be conductive to form the common electrode 150.

[0059] Step 30: conductive treatment is performed on the exposed opposite part to form the common electrode 150; and conductive treatment is performed on the exposed first connecting part 1211 and the second connecting part 1213.

[0060] In this step, the exposed part of the semiconductor layer 121 is conductive. By conductive treatment of the exposed part of the semiconductor layer 121, the exposed part of the semiconductor layer 121 through the first insulating layer 122 becomes a conductor, which facilitates other electrode structures or improves the conductivity, reduces the impedance, etc. Specifically, when the semiconductor layer 121 is conductive, it can be realized by ion implantation, or the surface of the semiconductor layer 121 is treated by H2, N2, etc., or the surface of the semiconductor layer 121 is deposited by chemical vapor deposition to achieve the effect of conductive. By conductive treatment of the exposed opposite part, the opposite part can be used as the common electrode 150, which can reduce the process of separately setting the common electrode 150, simplify the process steps, and save costs. By conductive treatment of the exposed first connecting part 1211 and the second connecting part 1212, the first connecting part 1211 and the second connecting part 1212 form a conductor, which reduces the impedance between the source 124 and the drain 125 connected to the first connecting part 1211 and the second connecting part 1212 respectively, and further increases the on-state current.

[0061] Step 40: plating a metal layer on the side of the first insulating layer 122 away from the substrate 110, and patterning the metal layer, so that the metal layer comprises the source electrode 124, the drain electrode 125 and the gate electrode 123 which are isolated from each other, wherein the source electrode 124 and the drain electrode 125 are in contact with the first connecting part 1211 and the second connecting part 1212 respectively, and the gate electrode 123 is arranged corresponding to the part of the semiconductor layer 121 which is not conductorized.

[0062] When the first insulating layer 122 is patterned, the first insulating layer 122 can also be partially photoetched corresponding to the pixel switch area 1012 of the display area 101 and the non-display area 102, so as to form a via structure, and then the exposed part of the semiconductor layer 121 (i.e. the first connecting part 1211 and the second connecting part 1212) can be conductorized through the via structure, so that the source electrode 124 and / or the drain electrode 125 can be connected to the conductor (i.e. the first connecting part 1211 and the second connecting part 1212 which are conductorized) corresponding to the via of the first insulating layer 122 through the via of the first insulating layer 122, so as to reduce the impedance between the source electrode 124 and the drain electrode 125, and then the on-state current can be increased. When the metal layer is plated on the side of the first insulating layer 122 away from the substrate 110, and the metal layer is patterned, the metal layer can be partially arranged on the first insulating layer 122 and not in contact with the semiconductor layer 121, so that the part of the metal layer not in contact with the semiconductor layer 121 forms the gate electrode 123, so that the thin film transistor 120 in the present application is a top gate electrode 123 structure, and the size of the thin film transistor 120 is small, so that the aperture ratio can be increased and the display effect can be improved; on the other hand, the gate electrode 123, the source electrode 124 and the drain electrode 125 are arranged in the same layer in the present application, so that the projections of the gate electrode 123, the source electrode 124 and the drain electrode 125 on the substrate 110 do not overlap, so that the parasitic capacitance of the thin film transistor 120 is extremely small or even negligible, so that the parasitic capacitance is reduced, and the resolution and refresh rate of the display picture are improved.

[0063] By patterning the first insulating layer 122, the position of the first insulating layer 122 corresponding to the opening region 1011 can be exposed by photolithography, so as to expose the part of the semiconductor layer 121 corresponding to the opening region 1011, i.e. the opposite part of the semiconductor layer 121. After the position of the semiconductor layer 121 corresponding to the opening region 1011 is exposed, if the conductive treatment is continued, the position of the semiconductor layer 121 corresponding to the opening region 1011 becomes a conductor, which can be used as at least a part of the common electrode 150, so that the common electrode 150 is arranged opposite to the pixel electrode 140 of the opening region 1011 to achieve the effect of controlling the deflection of the liquid crystal 300. In this way, the process of separately arranging the common electrode 150 can be reduced, so as to simplify the manufacturing process and save the cost. It can be understood that by plating a metal layer on the side of the first insulating layer 122 away from the substrate 110 and patterning the metal layer, the position of the metal layer corresponding to the opening region 1011 can be exposed by photolithography, so as to avoid the risk that the light cannot be emitted through the opening region 1011 due to the blocking effect of the metal on the light.

[0064] Step 50: arranging the pixel electrode 140, and making the pixel electrode 140 and the common electrode 150 arranged in different layers and insulated.

[0065] The pixel electrode 140 and the common electrode 150 are arranged in different layers and insulated, so that the pixel electrode 140 can be arranged above or below the common electrode 150, so as to make the display panel using the array substrate 100 meet the requirements of the FFS display panel and achieve the effects of high transmittance and wide viewing angle.

[0066] The technical solution of this invention places the gate 123 above the semiconductor layer 121, thereby forming a top gate 123 structure in the thin film transistor 120, which reduces the size of the thin film transistor 120 and increases the aperture ratio. On the other hand, by making the projections of the gate 123 on the substrate 110, the source 124 on the substrate 110, and the drain 125 on the substrate 110 non-overlapping, the parasitic capacitance of the thin film transistor 120 in this invention is extremely small or negligible, thereby meeting the requirements of the DEMUX switching circuit and achieving high resolution and high refresh rate. In addition, the array substrate 100 of the present invention also includes a pixel electrode 140 and a common electrode 150 disposed on the substrate 110. The pixel electrode 140 is connected to the drain 125 or the source 124 of the thin film transistor 120 and is disposed opposite to the first conductor portion 152 of the common electrode 150 in the direction perpendicular to the substrate 110. Thus, the array substrate 100 of the present invention is provided with both the pixel electrode 140 and the common electrode 150, and the pixel electrode 140 and the common electrode 150 are on different layers, thereby meeting the requirements of the FFS display panel and achieving the effects of wide viewing angle and high transmittance. Furthermore, since the first conductor portion 152 is formed by semiconductor through conductor formation, the first conductor portion 152 of the common electrode 150 can be simultaneously formed with the semiconductor layer 121 located below the gate 123 in one process before being conductor formed. That is, the semiconductor layer 121 can be deposited on the substrate 110 so that the semiconductor layer 121 is at least partially located below the pixel electrode 140, and then the portion located below the pixel electrode 140 can be conductor formed. This avoids the need to set up another conductive layer independent of the semiconductor layer 121 as the common electrode 150, further reducing the number of process steps and saving costs.

[0067] Furthermore, such as Figure 4 As shown, step 50: setting the pixel electrode 140, and ensuring that the pixel electrode 140 and the common electrode 150 are located on different layers and are insulated from each other, includes:

[0068] Step 51: Deposit a second insulating layer 130 on the side of the metal layer opposite to the substrate 110, and pattern the second insulating layer 130 to form a via that can expose the source 124 or the drain 125.

[0069] Step 52: Deposit a pixel electrode 140 on the side of the second insulating layer 130 away from the substrate 110. The pixel electrode 140 is deposited onto the source electrode 124 or the drain electrode 125 through the via.

[0070] In this way, the pixel electrode 140 is closer to the source electrode 124 and the drain electrode 125 of the thin film transistor 120, so that the pixel electrode 140 is connected to the source electrode 124 or the drain electrode 125 of the thin film transistor 120, and a better connection effect is achieved.

[0071] Embodiment three:

[0072] The application further provides a display panel, as shown in the drawings, which comprises an array substrate 100, a liquid crystal 300 and a counter substrate 200. Figure 5 The array substrate 100 and the counter substrate 200 are oppositely arranged, and the counter substrate 200 faces the pixel electrode 140, and the liquid crystal 300 is arranged between the array substrate 100 and the counter substrate 200.

[0073] The array substrate 100 and the counter substrate 200 are oppositely arranged, and the liquid crystal 300 is arranged between the array substrate 100 and the counter substrate 200, so that the light passing through the array substrate 100 is controlled by the liquid crystal 300 to change the amount of light passing through the counter substrate 200, thereby controlling the display brightness of the display panel.

[0074] Embodiment four:

[0075] The application further provides a display, as shown in the drawings, which comprises a backlight module 400 and a display panel. Figure 6 The backlight module 400 is arranged on the light-incident side of the array substrate 100.

[0076] The backlight module 400 is arranged on the light-incident side of the array substrate 100, that is, the backlight module 400 is arranged on the side of the array substrate 100 away from the counter substrate 200, so that the light emitted by the backlight module 400 can pass through the array substrate 100 and be emitted to the counter substrate 200, so that the user can view the displayed picture from the side of the counter substrate 200 away from the array substrate 100. The backlight module 400 can be a direct type backlight module 400 or a side type backlight module 400.

[0077] The above merely describes the preferred embodiments of the present application, and is not intended to limit the patent scope of the present application. Any equivalent structural changes made according to the content of the present application specification and drawings, or direct / indirect application in other related technical fields, are included in the patent protection scope of the present application.

Claims

1. An array substrate, comprising a substrate and a thin film transistor; the substrate comprises a display area and a non-display area surrounding the display area; the thin film transistor is provided with at least two, and the at least two thin film transistors are respectively arranged in the display area and the non-display area; the thin film transistor comprises a gate electrode, a first insulating layer, a semiconductor layer, a source electrode and a drain electrode which are arranged in a stack, the first insulating layer is arranged between the gate electrode and the semiconductor layer, and the source electrode and the drain electrode are both connected to the semiconductor layer; characterized in that, The gate is arranged above the semiconductor layer, and a projection of the gate on the substrate, a projection of the source on the substrate and a projection of the drain on the substrate do not coincide; The array substrate further comprises: a pixel electrode, which is electrically connected to the source or the drain of the thin film transistor in the display area; and a common electrode, which comprises a first conductor portion, the first conductor portion is arranged opposite to the pixel electrode in a direction perpendicular to the substrate and is arranged in the same layer as the semiconductor layer, and the first conductor portion is formed by semiconductor conductorization.

2. The array substrate of claim 1, wherein, The array substrate further comprises a second insulating layer, which is arranged on a side of the gate away from the substrate, and the pixel electrode is arranged on a side of the second insulating layer away from the substrate.

3. The array substrate of claim 1, wherein, The common electrode further comprises a second conductor portion, which is arranged on a side of the first conductor portion away from the substrate.

4. The array substrate of claim 3, wherein, The second conductor portion is arranged in the same layer as the gate.

5. The array substrate according to any one of claims 1 to 4, wherein, The source and the drain are both arranged in the same layer as the gate and are arranged on two sides of the gate respectively; the first insulating layer has a first via hole and a second via hole, and the source and the drain are connected to the semiconductor layer through the first via hole and the second via hole respectively.

6. The array substrate of claim 5, wherein, The part of the semiconductor layer corresponding to the first via hole forms a first connecting portion, and the part of the semiconductor layer corresponding to the second via hole forms a second connecting portion, and the first connecting portion and the second connecting portion are both formed by conductorization to form conductors.

7. A manufacturing method of an array substrate, the manufacturing method of an array substrate being based on the array substrate according to any one of claims 1 to 6, characterized by, The manufacturing method of the array substrate comprises: The substrate comprises a display area and a non-display area, the display area comprises an opening area and a pixel switching area, a semiconductor layer is plated on one side of the substrate, and the semiconductor layer is subjected to a patterning process; a first insulating layer is plated on a side of the semiconductor layer away from the substrate, the first insulating layer is subjected to a patterning process, and the part of the first insulating layer corresponding to the opening area is etched to expose the opposite part of the semiconductor layer corresponding to the opening area; and the part of the first insulating layer corresponding to the pixel switching area and the non-display area is also etched to form two communication holes, so that the part of the semiconductor layer corresponding to the two communication holes is exposed to form a first connecting portion and a second connecting portion; the exposed opposite part is subjected to a conductorization process to form a common electrode; and the exposed first connecting portion and the second connecting portion are subjected to a conductorization process; a metal layer is plated on a side of the first insulating layer away from the substrate, and the metal layer is subjected to a patterning process, so that the metal layer comprises a source, a drain and a gate which are isolated from each other, wherein the source and the drain are in contact with the first connecting portion and the second connecting portion respectively, and the gate is arranged corresponding to the part of the semiconductor layer which is not subjected to conductorization; a pixel electrode is arranged, and the pixel electrode and the common electrode are arranged in different layers and are insulated.

8. The method of manufacturing an array substrate according to claim 7, wherein The step of arranging the pixel electrode and arranging the pixel electrode and the common electrode in different layers and insulating the pixel electrode and the common electrode comprises: A second insulating layer is plated on the side of the metal layer away from the substrate, and the second insulating layer is patterned to form a via capable of exposing the source or the drain; A pixel electrode is plated on the side of the second insulating layer away from the substrate, and the pixel electrode is deposited on the source or the drain through the via.

9. A display panel, characterized by, The display panel comprises a pixel electrode, a source, a drain, a first insulating layer, a metal layer, a second insulating layer, and a via.

10. A display, characterized by The display panel comprises a pixel electrode, a source, a drain, a first insulating layer, a metal layer, a second insulating layer, and a via. The display panel comprises a pixel electrode, a source, a drain, a first insulating layer, a metal layer, a second insulating layer, and a via.

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