Voltage reducer with fast response mechanism and method of operating the same

Abstract

A voltage down converter includes a fast response circuit, a compensator coupled to an output, an interleaving logic circuit coupled to the compensator, a plurality of pulse width modulation signal generators, a plurality of OR gates coupled to corresponding pulse width modulation signal generators, a plurality of power stages coupled to corresponding OR gates, a plurality of inductors and an output capacitor. Each pulse width modulation signal generator is coupled to the interleaving logic circuit, the output and an input. The fast response circuit includes a voltage droop sensor coupled to the output, a load frequency sensor coupled to the output, a fast response signal generator coupled to the voltage droop sensor, a maximum fast response signal generator coupled to the voltage droop sensor and the load frequency sensor, and an AND gate coupled to the fast response signal generator, the maximum fast response signal generator and the plurality of OR gates.

Description

Technical Field

[0001] This invention relates to a buck converter, and more particularly to a buck converter with a fast response mechanism and its operating method. Background Technology

[0002] In modern voltage regulation systems used for microprocessor core voltage control, multiphase control is a common approach, meeting the requirements of high power density and high slew rate. However, conventional multiphase control methods are still insufficient to handle the ultra-high load transients specified in modern voltage regulator standards, especially during load application transients. Therefore, an open-loop control mechanism called quickresponse was invented to overcome the undershoot problem. During load application transients, the quickresponse mechanism immediately activates the high-side switches of all phases to fully supply the heavy load current demand, and the output voltage droop is thus controlled to the correct load line specification. Even so, the quickresponse mechanism still has some drawbacks; for example, inaccurate quickresponse on / off may lead to unexpected ringback or a sustained rise in output voltage causing circuit overload.

[0003] To make it clearer, Figure 9The diagram illustrates a prior art buck converter 900 with a fast-response circuit. The buck converter 900 includes multiple pulse width modulation signal generators Ton1 to TonN corresponding to each phase, multiple OR gates OR1 to ORN coupled to their respective Ton1 to TonN, multiple power stages PS1 to PSN coupled to their respective OR gates OR1 to ORN, multiple inductors L1 to LN coupled between their respective power stages PS1 to PSN and the output terminal OUT, an output capacitor Co, and a load Lo coupled between the output terminal OUT and the ground terminal GND. A fast-response signal circuit 910 is coupled between the output terminal OUT and the OR gates OR1 to ORN. Each power stage, such as power stage PS1, includes a buffer 903 coupled to OR gate OR1, an inverter 904 coupled to OR gate OR1, a first transistor 901, and a second transistor 902. The first transistor 901 includes a first terminal for receiving the input voltage Vin, a second terminal coupled to inductor L1, and a control terminal coupled to the buffer 903. The second transistor 902 includes a first terminal coupled to the second terminal of the first transistor 901 and an inductor L1, the second terminal coupled to ground GND, and a control terminal coupled to the inverter 904. The fast response signal circuit 910 generates a fast response signal QR based on the output voltage Vo. The pulse width modulation signal generators Ton1 to TonN for each phase output pulse width modulation generation signals PM1 to PMN based on the input voltage Vin and the output voltage Vo. OR gates OR1 to ORN generate pulse width modulation signals PWM1 to PWMN for each phase based on the pulse width modulation generation signals PM1 to PMN and the fast response signal QR. The pulse width modulation signals PWM1 to PWMN drive power stages PS1 to PSN to provide the output voltage Vo and the load current I. Lo .

[0004] Figure 10 for Figure 9 The timing diagram of the operating signals of the buck converter. At time t1, when the power demand of the load Lo increases, the load current I... Lo The current will rise to a high level, causing the output voltage Vo to begin to drop below the threshold. At this time, the fast response signal circuit 910 can generate a fast response signal QR. The QR signal and the pulse width modulation generation signals PM1 to PMN are ORed by a gate to generate pulse width modulation signals PWM1 to PWMN, which are used to drive the power stages PS1 to PSN to provide the output voltage Vo and the load current I. Lo In detail, the leading edge of the fast response signal QR can turn on the first transistor 901 and turn off the second transistor 902, and the first terminal of the first transistor 901 provides the load current I. LoWhen the first transistor 901 turns on, inductors L1 to LN begin charging, and the total inductance current Isum increases. Simultaneously, part of the current flows to the output capacitor Co to charge it, and the other part flows to the load Lo to provide power to Lo. After the fast response signal QR is pulled low, the first transistor 901 turns off and the second transistor 902 turns on, inductor L begins discharging, and the total inductance current Isum decreases. The output capacitor Co begins discharging to the load Lo, causing the load current I... Lo Maintain high current. At time t2, the load current I... Lo As the current drops to a low level, the output voltage Vo begins to rise, while the total inductor current Isum continues to decrease. At time t3, the load current I... Lo The current rises again to a high level, causing the output voltage Vo to drop below the threshold. At this point, the fast response signal QR is generated again and drives the power stages PS1 to PSN to provide the output voltage Vo and the load current I. Lo The rest of the operation process is the same as at time t1. At time t4, the load current I... Lo As the current drops to a low level, the output voltage Vo begins to rise, and the rest of the operation is the same as at time t2. Between times t5 and t6, the entire circuit operation repeats. However, the load frequency between times t3 and t6 is higher than the load frequency between times t1 and t2, causing the total inductor current Isum and the output voltage Vo to rise again before returning to their original levels. The total inductor current Isum and the output voltage Vo will continue to rise over time, eventually causing a voltage overload. Summary of the Invention

[0005] A buck converter includes a fast-response circuit, a compensator, an interleaved logic circuit, multiple pulse width modulation (PWM) signal generators, multiple OR gates, multiple power stages, multiple inductors, and an output capacitor. The compensator is coupled to the output. The interleaved logic circuit is coupled to the compensator. Multiple power stages are coupled to corresponding OR gates. Each PWM signal generator is coupled to the interleaved logic circuit, its output, and its input. Each OR gate is coupled to its corresponding PWM signal generator. Each inductor is coupled between its corresponding power stage and its output. The output capacitor is coupled between its output and ground. The fast-response circuit includes a voltage droop sensor, a load frequency sensor, a fast-response signal generator, a maximum fast-response signal generator, and an AND gate. The voltage droop sensor is coupled to the output. The load frequency sensor is coupled to the output. The fast-response signal generator is coupled to the voltage droop sensor. The maximum fast-response signal generator is coupled to the output and input of the voltage droop sensor and the load frequency sensor. AND gates are coupled to a fast response signal generator, a maximum fast response signal generator, and multiple OR gates. A voltage droop sensor generates a trigger signal based on the voltage droop of the output voltage. A load frequency sensor outputs a load frequency signal based on the load frequency, and a fast response signal generator generates an initial fast response signal based on the trigger signal. A maximum fast response signal generator generates a maximum fast response signal based on the input voltage, trigger signal, load frequency signal, and output voltage. AND gates generate a fast response signal based on the initial fast response signal and the maximum fast response signal. A compensator generates a compensation signal based on the output voltage and a reference voltage. Interleaving logic circuitry generates an interleaved signal based on the compensation signal, and each pulse width modulation (PWM) signal generator generates a PWM generation signal based on the interleaved signal, output voltage, and input voltage. Each OR gate generates a PWM signal based on the fast response signal and the corresponding PWM generation signal. Multiple power stages generate output voltages based on multiple PWM signals.

[0006] A method for operating a buck converter. The buck converter includes a fast response circuit, a compensator, an interleaved logic circuit, multiple pulse width modulation signal generators, multiple OR gates, multiple power stages, multiple inductors, and an output capacitor. The compensator is coupled to the output terminal. The interleaved logic circuit is coupled to the compensator. Each pulse width modulation signal generator is coupled to the interleaved logic circuit, its output terminal, and its input terminal. Each OR gate is coupled to its corresponding pulse width modulation signal generator. Multiple power stages are coupled to their corresponding OR gates. Each inductor is coupled between its corresponding power stage and its output terminal. The output capacitor is coupled between its output terminal and ground. The fast response circuit includes a voltage droop sensor, a load frequency sensor, a fast response signal generator, a maximum fast response signal generator, and an AND gate. The voltage droop sensor is coupled to the output terminal. The load frequency sensor is coupled to the output terminal. The fast response signal generator is coupled to the voltage droop sensor. The maximum fast response signal generator is coupled to the voltage droop sensor, the load frequency sensor, its output terminal, and its input terminal. The AND gate is coupled to a fast response signal generator, a maximum fast response signal generator, and multiple OR gates. The operation includes a voltage droop sensor generating a trigger signal based on the voltage droop of the output voltage; a load frequency sensor outputting a load frequency signal based on the load frequency; a fast response signal generator generating a start fast response signal based on the trigger signal; a maximum fast response signal generator generating a maximum fast response signal based on the input voltage, the trigger signal, the load frequency signal, and the output voltage; an AND gate generating a fast response signal based on the start fast response signal and the maximum fast response signal; a compensator generating a compensation signal based on the output voltage and a reference voltage; an interleaving logic circuit generating an interleaving signal based on the compensation signal; each of the multiple pulse width modulation (PWM) signal generators generating a PWM generation signal based on the interleaving signal, the output voltage, and the input voltage; each of the multiple OR gates generating a PWM signal based on the fast response signal and the corresponding PWM generation signal; and multiple power stages generating output voltages based on the multiple PWM signals.

[0007] A maximum fast response signal generator includes a current source, a capacitor, a switch, a comparator, and a flip-flop. The capacitor is coupled between the current source and a ground terminal. The switch includes a first terminal coupled to the current source and the capacitor, a second terminal coupled to the ground terminal, and a control terminal. The comparator includes a positive input terminal coupled to the current source, the capacitor, and the first terminal of the switch, a negative input terminal, and an output terminal. The flip-flop includes an input terminal, a timing terminal, an output terminal, an inverting output terminal coupled to the control terminal of the switch, and a reset terminal coupled to the output terminal of the comparator. The current source generates current based on the input voltage and the load frequency signal. The comparator outputs a reset signal at its output terminal based on the response voltage received at the positive input terminal and the output voltage received at the negative input terminal. The flip-flop outputs a maximum fast response signal at its output terminal based on a fixed voltage received at the input terminal, a trigger signal received at the timing terminal, and a reset signal received at the reset terminal.

[0008] A method for operating a maximum fast response signal generator. The maximum fast response signal generator includes a current source, a capacitor, a switch, a comparator, and a flip-flop. The capacitor is coupled between the current source and a ground terminal. The switch includes a first terminal coupled to the current source and the capacitor, a second terminal coupled to the ground terminal, and a control terminal. The comparator includes a positive input terminal coupled to the current source, the capacitor, and the first terminal of the switch, a negative input terminal, and an output terminal. The flip-flop includes an input terminal, a timing terminal, an output terminal, an inverting output terminal coupled to the control terminal of the switch, and a reset terminal coupled to the output terminal of the comparator. The operating method includes the current source generating current according to the input voltage and the load frequency signal; the comparator outputting a reset signal at its output terminal based on the response voltage received at the positive input terminal and the output voltage received at the negative input terminal; and the flip-flop outputting a maximum fast response signal at its output terminal based on a fixed voltage received at the input terminal, a trigger signal received at the timing terminal, and a reset signal received at the reset terminal. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a buck converter according to an embodiment of the present invention.

[0010] Figure 2 for Figure 1 A schematic diagram of the maximum fast response signal generator.

[0011] Figure 3 Figure 3 for Figure 2 Timing diagram of the operating signals of the maximum fast response signal generator.

[0012] Figure 4 for Figure 1 Timing diagram of the operating signals of the buck converter.

[0013] Figure 5 for Figure 1 Another operating signal timing diagram of the buck converter.

[0014] Figure 6 for Figure 1 Another operating signal timing diagram of the buck converter.

[0015] Figure 7 for Figure 1 A flowchart illustrating the operation method of the buck converter.

[0016] Figure 8 for Figure 2 A flowchart of the operation method of the maximum fast response signal generator.

[0017] Figure 9 This is a schematic diagram of a prior art buck converter with a fast response circuit.

[0018] Figure 10for Figure 9 Timing diagram of the operating signals of the buck converter. Detailed Implementation

[0019] Figure 1 This is a schematic diagram of a buck converter 100 according to an embodiment of the present invention. The buck converter 100 is a DC-DC converter that reduces the voltage, with the output voltage OUT being lower than the input voltage Vin at the input terminal IN. The buck converter 100 may include a fast response circuit 10, a compensator 20, an interleaved logic circuit 30, multiple pulse width modulation signal generators Ton1 to TonN, multiple OR gates OR1 to ORN, multiple power stages PS1 to PSN, multiple inductors L1 to LN, an output capacitor Co, and a load Lo. The compensator 20 is coupled to the output terminal OUT. The interleaved logic circuit 30 is coupled to the compensator 20. The pulse width modulation signal generators Ton1 to TonN are coupled to the interleaved logic circuit 30, the input terminal IN, and the output terminal OUT. The OR gates OR1 to ORN are coupled to their corresponding pulse width modulation signal generators Ton1 to TonN. The power stages PS1 to PSN are coupled to their corresponding OR gates OR1 to ORN. Inductors L1 to LN are coupled between the corresponding power stages PS1 to PSN and the output terminal OUT. Output capacitor Co is coupled between the output terminal OUT and the ground terminal GND. Load Lo is coupled between the output terminal OUT and the ground terminal GND. Each pulse width modulation (PWM) signal generator and power stage corresponds to a phase; for example, PWM signal generator Ton1 and power stage PS1 correspond to the first phase, PWM signal generator Ton2 and power stage PS2 correspond to the second phase, and so on.

[0020] The fast response circuit 10 includes a voltage droop sensor 12, a load frequency sensor 14, a fast response signal generator 16, a maximum fast response signal generator 18, and an AND gate. The voltage droop sensor 12 is coupled to the output terminal OUT. The load frequency sensor 14 is coupled to the output terminal OUT. The fast response signal generator 16 is coupled to the voltage droop sensor 12. The maximum fast response signal generator 18 is coupled to the voltage droop sensor 12, the load frequency sensor 14, the input terminal IN, and the output terminal OUT. The AND gate is coupled to the fast response signal generator 16, the maximum fast response signal generator 18, and OR gates OR1 to ORN.

[0021] Voltage droop sensor 12 generates a trigger signal Vsen based on the voltage droop of the output voltage Vo. Load frequency sensor 14 outputs a load frequency signal Fs based on the frequency of the load Lo. Fast response signal generator 16 generates a start fast response signal QRi based on the trigger signal Vsen. Maximum fast response signal generator 18 generates a maximum fast response signal QRmax based on the input voltage Vin, the trigger signal Vsen, the load frequency signal Fs, and the output voltage Vo. AND gate generates a fast response signal QR based on the start fast response signal QRi and the maximum fast response signal QRmax. Compensator 30 generates a compensation signal Vcomp based on the output voltage Vo and the reference voltage Vref. Interleaved logic circuit 30 generates an interleaved signal Vint based on the compensation signal Vcomp. Pulse width modulation signal generators Ton1 to TonN generate pulse width modulation generation signals PM1 to PMN based on the interleaved signal Vint, the output voltage Vo, and the input voltage Vin. OR gates OR1 to ORN are used to generate pulse width modulation signals PWM1 to PWMN based on the fast response signal QR and the corresponding pulse width modulation generation signals PM1 to PMN. Power stages PS1 to PSN are used to generate the output voltage Vo and provide the load current I based on the pulse width modulation signals PWM1 to PWMN. Lo The current flows to the load Lo, and simultaneously generates a total inductance current Isum in inductors L1 to LN. The pulse width modulation generation signals PM1 to PMN and the pulse width modulation signals PWM1 to PWMN correspond to the first phase to the Nth phase, respectively.

[0022] For example, the frequency range of the load Lo of the buck converter 100 can be between 300Hz and 1MHz, the input voltage Vin can be between 6V and 24V, the output voltage Vo can be between 0.2V and 3.05V, the fast response signal QR can be 5V, and the load current I... Lo It can range from 50A to 300A.

[0023] Figure 2 for Figure 1A schematic diagram of the maximum fast response signal generator 18 is shown. The maximum fast response signal generator 18 includes a current source 181, a capacitor C, a switch S, a comparator 182, and a flip-flop SR. The capacitor C is coupled between the current source 181 and the ground terminal GND. The switch S includes a first terminal coupled to the current source 181 and the capacitor C, a second terminal coupled to the ground terminal GND, and a control terminal. The comparator 182 includes a positive input terminal coupled to the current source 181, the capacitor C, and the first terminal of the switch S, and a negative input terminal coupled to the output terminal OUT. The flip-flop SR includes an input terminal D, a reset terminal R coupled to the output terminal of the comparator 182, a timing terminal CK, an output terminal Q, and an inverted output terminal Qb coupled to the control terminal of the switch S. The current source 181 is used to generate a response current Iqr based on the input voltage Vin and the load frequency signal Fs. The comparator 182 is used to generate a reset signal Vrst based on the response voltage Vqr received at the positive input terminal and the output voltage Vo received at the negative input terminal. The trigger SR outputs a maximum fast response signal QRmax at the output Q based on the fixed voltage VHD received at the input D, the trigger signal Vsen received at the timing terminal CK, and the reset signal Vrst received at the reset terminal R. The current source 181 can be implemented using any semiconductor current mirror, and the switch S can be implemented using a field-effect transistor.

[0024] Figure 3 Figure 3 for Figure 2 The following is a timing diagram of the operating signals of the maximum fast response signal generator 18. The process of the maximum fast response signal generator 18 generating the maximum fast response signal QRmax is explained below. At time t1, the trigger signal Vsen is pulled high, causing the maximum fast response signal QRmax output by the output terminal Q of the flip-flop SR to also be pulled high. The response current Iqr begins to charge the capacitor C, and the response voltage Vqr begins to rise. At time t2, when the response voltage Vqr rises to a level exceeding the output voltage Vo, the comparator 182 pulls the reset signal Vrst high. The high-level reset signal Vrst pulls the maximum fast response signal QRmax output by the output terminal Q of the flip-flop SR to low, and also pulls the signal output by the inverted output terminal Qb to high. The high-level signal of the inverted output terminal Qb opens the switch S, guiding the response current Iqr to the ground terminal GND, pulling the response voltage Vqr low, and the reset signal Vrst also returns to low. Because the circuit response time is on the order of nanoseconds, the reset signal Vrst presents a pulse wave.

[0025] At time t3, the trigger signal Vsen is pulled high again, and the entire circuit operation repeats, and so on. The entire circuit operation can be repeated as needed. The on-time of the maximum fast response signal QRmax is the time required for the response voltage Vqr to rise from a low level to the output voltage Vo level. It should be noted that the amplitude of the output voltage Vo is much smaller than that of the response voltage Vqr, so the level of the output voltage Vo appears fixed in the diagram.

[0026] Furthermore, the current source 181 can adjust the response current Iqr according to the load frequency signal Fs and the input voltage Vin. The fixed voltage VHD can be a DC voltage, such as 5V, and can be used to make the high level of the maximum fast response signal QRmax output by the trigger SR equal to the fixed voltage VHD. The width of the maximum fast response signal QRmax can be expressed by the following formula:

[0027]

[0028] Where QRmax is the maximum fast response signal width, C is the capacitance value, Vo is the output voltage, Vin is the input voltage, Rs is the resistance value of the current source 181, and Fs is the load frequency.

[0029] The width of the maximum fast response signal QRmax is the maximum pulse width modulation signal width that the buck converter 100 can withstand. If the pulse width modulation signal exceeds this width, the output voltage Vo will continuously rise, causing voltage overload. The application of the maximum fast response signal generator 18 can prevent voltage overload.

[0030] Figure 4 for Figure 1 The following is a timing diagram of the operating signals of the buck converter 100. The fast response circuit 10 generates a fast response signal QR and its application in providing the output voltage Vo and load current I of the buck converter 100. Lo The process. At time t1, the load current I... LoThe current rises to a high level, causing the output voltage Vo to begin to drop below the threshold. At this point, the voltage droop sensor 12 generates a trigger signal Vsen, which is then sent to the fast response signal generator 16 and the maximum fast response signal generator 18 to generate the initial fast response signal QRi and the maximum fast response signal QRmax, respectively. The fast response signal generator 16 adjusts the width of the initial fast response signal QRi according to the slope of the trigger signal Vsen. The initial fast response signal QRi and the maximum fast response signal QRmax are input to an AND gate. The AND gate performs an AND logic operation on the maximum fast response signal QRmax and the initial fast response signal QRi to generate the fast response signal QR. The fast response signal QR and the pulse width modulation generation signals PM1 to PMN are input to the corresponding OR gates OR1 to ORN, respectively. The OR gates OR1 to ORN perform an OR logic operation on the fast response signal QR and the corresponding pulse width modulation generation signals PM1 to PMN to generate pulse width modulation signals PWM1 to PWMN. The pulse width modulation signals PWM1 to PWMN simultaneously drive the power stages PS1 to PSN to generate the output voltage Vo, and the total inductor current Isum generated by inductors L1 to LN begins to rise. Simultaneously, a portion of the total inductor current Isum flows to the output capacitor Co to charge it, while another portion becomes the load current I flowing to the load Lo. Lo It provides the electrical energy required by the load Lo. The operation of power stages PS1 to PSN is well known to those skilled in the art and will not be described in detail here.

[0031] Between time t1 and time t2, initially, the fast response signal QR quickly provides power, rapidly increasing the total inductor current Isum. Subsequently, because the output voltage Vo is still below the threshold, the compensator 20 outputs a compensation signal Vcomp, causing the interleaved logic circuit 30 to generate an interleaved signal Vint. This drives the pulse width modulation signal generators Ton1 to TonN to generate pulse width modulation generation signals PM1 to PMN in an interleaved manner. These pulse width modulation generation signals PM1 to PMN are the pulse width modulation signals PWM1 to PWMN. The pulse width modulation signals PWM1 to PWMN drive the power stages PS1 to PSN to continuously provide a portion of the load current I. Lo Simultaneously, the output capacitor Co discharges to provide another portion of the load current I. Lo .

[0032] At time t2, the load current I Lo As the current drops to a low level, the output voltage Vo begins to rise, inductors L1 to LN begin to discharge, and the total inductor current Isum begins to decrease to a low level until time t3, at which point the load current I... Lo Further improvements are made. The circuit operation process from time t1 to t2 is repeated during the time period from t3 to t4.

[0033] During time t5 to t6, the load frequency increases. At this time, the fast response signal QR is the pulse width modulation signal PWM1 to PWMN. The pulse width modulation signals PWM1 to PWMN simultaneously drive the power stages PS1 to PSN to generate the output voltage Vo and provide the load current I. Lo Since the pulse width modulation signals PWM1 to PWMN generated by the fast response signal QR already provide sufficient power, the compensator 20 does not need to output a compensation signal Vcomp to cause the pulse width modulation signal generators Ton1 to TonN to output additional pulse width modulation generation signals PM1 to PMN to drive the power stages PS1 to PSN to provide additional current. After the fast response signal QR is pulled low, the inductors L1 to LN begin to discharge, and the total inductor current Isum begins to decrease. Afterwards, the load current I... Lo As the current drops to a low level, the output voltage Vo begins to rise, while the total inductor current Isum continues to decrease until time t7, at which point the load current I... Lo Further improvements are made. Although the frequency of the operating cycles from time t7 to t8 and thereafter may differ, the circuit operation process essentially repeats the cycle from time t5 to t6, and so on. Because the fast response circuit 10 of this invention can control the width of the fast response signal QR, the total inductor current Isum can only be pulled up again after it drops back to its original level, thus preventing additional energy accumulation. Consequently, the output voltage Vo will not be pulled up higher and higher over time, thereby avoiding voltage overload.

[0034] Figure 5 for Figure 1 Another operating signal timing diagram of the buck converter 100. Figure 5 The total inductor current Isum and the fast response signal QR are illustrated to help explain how the width of the maximum fast response signal QRmax is derived. The explanation is as follows:

[0035] The total electrical energy of inductors L1 to LN during one cycle is:

[0036]

[0037] The total electrical energy discharged by inductors L1 to LN in one cycle is:

[0038]

[0039] According to the law of conservation of energy, the total electrical energy of inductors L1 to LN during one cycle of charging is equal to the total electrical energy of inductors L1 to LN during discharging:

[0040]

[0041] Therefore, the maximum pulse width modulation signal width that the buck converter 100 can withstand can be derived from the following formula:

[0042]

[0043]

[0044]

[0045]

[0046]

[0047] Where QRmax is the width of the maximum fast response signal, Vo is the output voltage, Vin is the input voltage, Fs is the load frequency, Ts is the load period, N is the number of phases, and L is the inductance value. As can be seen from the formula, the width of the maximum fast response signal can be determined by the input voltage Vin, the output voltage Vo, and the load frequency.

[0048] Figure 6 for Figure 1 Another timing diagram of the buck converter 100 is shown. The high-level time of the maximum fast response signal QRmax is the time required for the response voltage Vqr to rise from a low level to the output voltage Vo. In period T1, the width of the initial fast response signal QRi is less than the width of the maximum fast response signal QRmax, therefore the fast response signal QR output by the fast response circuit 10 is the initial fast response signal QRi. In period T2, the width of the initial fast response signal QRi is greater than the width of the maximum fast response signal QRmax, therefore the fast response signal QR output by the fast response circuit 10 is the maximum fast response signal QRmax. In period T3, the load frequency increases, and the maximum fast response signal generator 18 reduces the width of the maximum fast response signal QRmax due to the increased load frequency. Therefore, the fast response signal QR output by the fast response circuit 10 is the maximum fast response signal QRmax to avoid circuit overload in the buck converter 100. During period T4, the load frequency decreases. Because of the reduced load frequency, the maximum fast response signal generator 18 increases the width of the maximum fast response signal QRmax. Therefore, the fast response signal QR output by the fast response circuit 10 becomes the initial fast response signal QRi. This method allows for timely adjustment of the width of the fast response signal QR according to the load frequency to avoid voltage overload and achieve optimal energy efficiency.

[0049] Figure 7 for Figure 1 A flowchart of the operation method 700 of the buck converter 100. Method 700 includes the following steps:

[0050] S702: Voltage droop sensor 12 generates a trigger signal Vsen based on the voltage droop of the output voltage Vo;

[0051] S704: Load frequency sensor 14 outputs a load frequency signal Fs based on the frequency of the load Lo;

[0052] S706: Fast response signal generator 16 generates an initial fast response signal QRi based on the trigger signal Vsen;

[0053] S708: Maximum Fast Response Signal Generator 18 generates a maximum fast response signal QRmax based on the input voltage Vin, trigger signal Vsen, load frequency signal Fs, and output voltage Vo;

[0054] S710: The AND gate generates a fast response signal QR based on the initial fast response signal QRi and the maximum fast response signal QRmax;

[0055] S712: Compensator 20 generates a compensation signal Vcomp based on the output voltage Vo and the reference voltage Vref;

[0056] S714: Interleaved logic circuit 30 generates interleaved signal Vint based on compensation signal Vcomp;

[0057] S716: Pulse width modulation signal generators Ton1 to TonN generate corresponding pulse width modulation generation signals PM1 to PMN based on the interleaved signal Vint, the output voltage Vo, and the input voltage Vin;

[0058] S718: OR gates OR1 to ORN generate corresponding pulse width modulation signals PWM1 to PWMN based on the fast response signal QR and the corresponding pulse width modulation generation signals PM1 to PMN; and

[0059] S720: Power stages PS1 to PSN generate output voltage Vo based on pulse width modulation signals PWM1 to PWMN.

[0060] Detailed instructions on how to operate the buck converter 100 are available in the preceding paragraphs and will not be repeated here.

[0061] Figure 8 for Figure 2 A flowchart of the operation method 800 of the maximum fast response signal generator 18. Method 800 includes the following steps:

[0062] S802: Current source 181 generates a response current Iqr based on the input voltage Vin and the load frequency signal Fs;

[0063] S804: Comparator 182 outputs a reset signal Vrst based on the response voltage Vqr received at the positive input terminal and the output voltage Vo received at the negative input terminal; and

[0064] S806: The trigger SR outputs the maximum fast response signal QRmax at the output terminal Q based on the fixed voltage VHD received at the input terminal D, the trigger signal Vsen received at the timing terminal CK, and the reset signal Vrst received at the reset terminal R.

[0065] Detailed instructions on the operation of the maximum fast response signal generator 18 800 can be found in the preceding paragraphs and will not be repeated here.

[0066] In summary, the buck converter with fast response circuitry of this invention effectively avoids the voltage overload problem that may occur during the instantaneous application of load in general fast response circuits. The total inductor current can only be pulled up again after it returns to its original level, thus preventing additional energy accumulation. The output voltage will not be pulled up more and more over time, thereby avoiding voltage overload and improving the energy efficiency of the buck converter.

[0067] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0068] [Symbol Explanation]

[0069] 100,900: Buck converter

[0070] 10,910: Fast response circuit

[0071] 12: Voltage droop sensor

[0072] 14: Load Frequency Sensor

[0073] 16: Fast Response Signal Generator

[0074] 18: Maximum Fast Response Signal Generator

[0075] 20: Compensator

[0076] 30: Interleaved Logic Circuits

[0077] 901, 902: Transistors

[0078] 903: Buffer

[0079] 904: Inverter

[0080] Ton1~TonN: Pulse Width Modulation Signal Generator

[0081] OR1~ORN: OR gate

[0082] PS1~PSN: Power Stage

[0083] L1~LN: Inductors

[0084] AND: AND gate

[0085] Vo: Output voltage

[0086] Vin: Input voltage

[0087] Vsen: Trigger signal

[0088] Lo: Load

[0089] Co: Output capacitor

[0090] Fs: Load frequency signal

[0091] I Lo Load current

[0092] Isum: Total inductance current

[0093] QRi: Start-up Fast Response Signal

[0094] QRmax: Maximum Fast Response Signal

[0095] QR: Quick Response Signal

[0096] Vref: Reference voltage

[0097] Vcomp: Compensation signal

[0098] Vint: Interleaved signal

[0099] PM1~PMN: Pulse width modulation generates signals

[0100] PWM1~PWMN: Pulse Width Modulation Signals

[0101] OUT: Output terminal

[0102] IN: Input terminal

[0103] 181: Current Source

[0104] 182: Comparator

[0105] C: Capacitor

[0106] S: Switch

[0107] SR: Trigger

[0108] GND: Ground terminal

[0109] D: Input terminal

[0110] R: Reset end

[0111] CK: Timing Terminal

[0112] Q: Output terminal

[0113] Qb: Inverted output terminal

[0114] Iqr: Response current

[0115] Vqr: Response voltage

[0116] t1~t8: Time

[0117] T1~T4: Period

[0118] 700, 800: Method

[0119] S702~S720,

[0120] S802~S806: Steps

Claims

1. A step-down converter, comprising: a fast response circuit, comprising: a voltage droop sensor coupled to an output terminal for detecting a voltage droop of an output voltage and generating a trigger signal accordingly; a load frequency sensor coupled to the output terminal for detecting a frequency of a load and outputting a load frequency signal accordingly; a fast response signal generator coupled to the voltage droop sensor for generating an initial fast response signal according to the trigger signal; a maximum fast response signal generator coupled to the voltage droop sensor, the load frequency sensor, the output terminal and an input terminal for generating a maximum fast response signal according to an input voltage, the trigger signal, the load frequency signal and the output voltage; and an AND gate coupled to the fast response signal generator and the maximum fast response signal generator for generating a fast response signal according to the initial fast response signal and the maximum fast response signal; a compensator coupled to the output terminal for generating a compensation signal according to the output voltage and a reference voltage; an interleaving logic coupled to the compensator for generating an interleaving signal according to the compensation signal; a plurality of pulse width modulation signal generators, wherein each pulse width modulation signal generator is coupled to the interleaving logic, the input terminal and the output terminal for generating a pulse width modulation generated signal according to the interleaving signal, the output voltage and the input voltage; a plurality of OR gates, wherein each OR gate is coupled to the AND gate of the fast response circuit and a corresponding pulse width modulation signal generator, the each OR gate for generating a pulse width modulation signal according to the fast response signal and a corresponding pulse width modulation generated signal; a plurality of power stages, wherein each power stage is coupled to a corresponding OR gate for generating the output voltage according to a corresponding pulse width modulation signal; a plurality of inductors, wherein each inductor is coupled between a corresponding power stage and the output terminal; and an output capacitor coupled between the output terminal and a ground terminal.

2. The step-down converter of claim 1, wherein the initial fast response signal, the maximum fast response signal, the fast response signal, the pulse width modulation generated signal and the plurality of pulse width modulation signals generated by the plurality of OR gates are substantially square wave signals.

3. The step-down converter of claim 1, wherein the plurality of pulse width modulation signal generators generate a plurality of pulse width modulation generated signals in interleaved manner.

4. The step-down converter of claim 1, wherein the fast response signal generator is further for adjusting a width of the initial fast response signal according to a slope of the trigger signal.

5. The step-down converter of claim 1, wherein the maximum fast response signal generator is further for adjusting a width of the maximum fast response signal according to the input voltage, the output voltage and the load frequency signal.

6. The voltage reducer of claim 1, wherein the AND gate performs an AND operation on the maximum fast response signal and the initial fast response signal to generate the fast response signal.

7. The voltage reducer of claim 1, wherein each OR gate performs an OR operation on the fast response signal and a corresponding pulse width modulation generate signal to generate the pulse width modulation signal.

8. The voltage reducer of claim 1, wherein the compensator generates the compensation signal when the output voltage drops to less than the reference voltage.

9. The voltage reducer of claim 1, wherein the maximum fast response signal generator comprises: a current source for generating a current according to the input voltage and the load frequency signal; a capacitor coupled between the current source and the ground; a switch comprising: a first terminal coupled to the current source and the capacitor; a second terminal coupled to the ground; and a control terminal; a comparator for generating a reset signal according to a response voltage and the output voltage, the comparator comprising: a positive input terminal coupled to the current source, the capacitor and the first terminal of the switch for receiving the response voltage; and an output terminal for outputting the reset signal; and a flip-flop for generating the maximum fast response signal according to a fixed voltage, the trigger signal and the reset signal, comprising: an input terminal for receiving the fixed voltage; a reset terminal coupled to the output terminal of the comparator for receiving the reset signal; a timing terminal for receiving the trigger signal; an output terminal for outputting the maximum fast response signal; and an inverted output terminal coupled to the control terminal of the switch.

10. A method for operating a voltage reducer, the voltage reducer comprising a fast response circuit, a compensator, an interleaving logic circuit, a plurality of pulse width modulation signal generators, a plurality of OR gates, a plurality of power stages, a plurality of inductors and an output capacitor, the compensator coupled to an output terminal, the interleaving logic circuit coupled to the compensator, each pulse width modulation signal generator coupled to the interleaving logic circuit and an input terminal and the output terminal, respectively, each OR gate coupled to a corresponding pulse width modulation signal generator, a plurality of power stages coupled to corresponding plurality of OR gates, each inductor coupled between a corresponding power stage and the output terminal, the output capacitor coupled between the output terminal and a ground terminal, the fast response circuit comprising a voltage droop sensor, a load frequency sensor, a fast response signal generator, a maximum fast response signal generator, an AND gate, the voltage droop sensor coupled to the output terminal, the load frequency sensor coupled to the output terminal, the fast response signal generator coupled to the voltage droop sensor, the maximum fast response signal generator coupled to the voltage droop sensor, the load frequency sensor, the output terminal and the input terminal, the AND gate coupled to the fast response signal generator, the maximum fast response signal generator and the plurality of OR gates, the method comprising: generating a trigger signal by the voltage droop sensor according to a voltage droop of an output voltage; outputting a load frequency signal by the load frequency sensor according to a frequency of the load; ​ ​ ​ ​ ​ ​ ​ a negative input terminal for receiving the output voltage; ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The fast response signal generator generates a start fast response signal according to the trigger signal; The maximum fast response signal generator generates a maximum fast response signal according to an input voltage, the trigger signal, the load frequency signal and the output voltage; The AND gate generates a fast response signal according to the start fast response signal and the maximum fast response signal; The compensator generates a compensation signal according to the output voltage and a reference voltage; The interleaving logic circuit generates an interleaving signal according to the compensation signal; Each of the plurality of pulse width modulation signal generators generates a pulse width modulation generated signal according to the interleaving signal, the output voltage and the input voltage; Each of the plurality of OR gates generates a pulse width modulation signal according to the fast response signal and a corresponding pulse width modulation generated signal; and The plurality of power stages generates the output voltage according to the plurality of pulse width modulation signals.

11. The method of claim 10, wherein the start fast response signal, the maximum fast response signal, the fast response signal, the pulse width modulation generated signal and the pulse width modulation signal are substantially square wave signals.

12. The method of claim 10, wherein the fast response signal generator generates the start fast response signal according to the trigger signal, comprising: The fast response signal generator adjusts a width of the start fast response signal according to a slope of the trigger signal.

13. The method of claim 10, further comprising the plurality of pulse width modulation signal generators generating the plurality of pulse width modulation generated signals in an interleaved manner.

14. The method of claim 10, wherein the maximum fast response signal generator generates the maximum fast response signal according to the input voltage, the trigger signal, the load frequency signal and the output voltage, comprising: The maximum fast response signal generator adjusts a width of the maximum fast response signal according to the input voltage, the trigger signal, the load frequency signal and the output voltage.

15. The method of claim 10, wherein the AND gate generates the fast response signal according to the start fast response signal and the maximum fast response signal, comprising: The AND gate performs an AND logic operation on the maximum fast response signal and the start fast response signal to generate the fast response signal.

16. The method of claim 10, wherein each of the plurality of OR gates generates the pulse width modulation signal according to the fast response signal and a corresponding pulse width modulation generated signal, comprising: Each of the OR gates performs an OR logic operation on the fast response signal and the corresponding pulse width modulation generated signal to generate the pulse width modulation signal.

17. The method of claim 10, wherein the compensator receives the output voltage and a reference voltage and generates a compensation signal therefrom, comprising: The compensator generates the compensation signal when the output voltage falls below the reference voltage.

18. The method of claim 10, wherein the maximum fast response signal generator generates the maximum fast response signal according to the input voltage, the trigger signal, the load frequency signal and the output voltage, comprising: The maximum fast response signal generator includes a current source, a capacitor, a switch, a comparator, and a trigger. The capacitor is coupled between the current source and a ground terminal. The switch includes a first terminal coupled to the current source and the capacitor, a second terminal coupled to the ground terminal, and a control terminal. The comparator includes a positive input terminal coupled to the first terminal of the current source, the capacitor, and the switch, a negative input terminal, and an output terminal. The trigger terminal includes an input terminal, a reset terminal coupled to the output terminal of the comparator, a timing terminal, an output terminal, and an inverted output terminal coupled to the control terminal of the switch. The method includes: The current source generates a current based on the input voltage and the load frequency signal; The comparator outputs a reset signal at its output terminal based on a response voltage received at the positive input terminal and an output voltage received at the negative input terminal; and The trigger outputs the maximum fast response signal at the output terminal based on a fixed voltage received at the input terminal, a trigger signal received at the timing terminal, and a reset signal received at the reset terminal.

19. A maximum fast response signal generator, comprising: A current source for generating a response current based on an input voltage and a load frequency signal; A capacitor is coupled between the current source and a ground terminal; A switch, comprising: One terminal is coupled to the current source and the capacitor; A second terminal is coupled to the ground terminal; and One control terminal; A comparator for generating a reset signal based on a response voltage and an output voltage, the comparator comprising: A positive input terminal is coupled to the first terminal of the current source, the capacitor and the switch to receive the response voltage; a negative input terminal for receiving the output voltage; and One output terminal is used to output the reset signal; and A trigger for generating a maximum fast response signal based on a fixed voltage, a trigger signal, and the reset signal, comprising: One input terminal is used to receive the fixed voltage; A reset terminal is coupled to the output terminal of the comparator to receive the reset signal; A timing terminal is used to receive the trigger signal; One output terminal is used to output the maximum fast response signal; and One of the output terminals is coupled to the control terminal of the switch.

20. A method of operating a maximum fast response signal generator, the maximum fast response signal generator comprising a current source, a capacitor, a switch, a comparator, and a trigger, the capacitor being coupled between the current source and a ground terminal, the switch comprising a first terminal coupled to the current source and the capacitor, a second terminal coupled to the ground terminal, and a control terminal, the comparator comprising a positive input terminal coupled to the first terminal of the current source, the capacitor, and the switch, a negative input terminal and an output terminal, the trigger comprising an input terminal, a reset terminal coupled to the output terminal of the comparator, a timing terminal, an output terminal and an inverted output terminal coupled to the control terminal of the switch, the method comprising: The current source generates a response current based on an input voltage and a load frequency signal; The comparator outputs a reset signal at its output terminal based on a response voltage received at the positive input terminal and an output voltage received at the negative input terminal; and The trigger outputs a maximum fast response signal at its output terminal based on a fixed voltage received at the input terminal, a trigger signal received at the timing terminal, and a reset signal received at the reset terminal.

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