A ramp compensation circuit, a method for generating a ramp compensation signal and an electronic chip
By combining the signal input module, DC reference module, and compensation output module, and utilizing NMOS and PMOS transistor current mirror units, full-range ramp compensation is achieved, solving the problems of charging waiting time and poor linearity in the current-mode control architecture, and improving the stability and applicability of the system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING MICRO ONE ELECTRONICS
- Filing Date
- 2023-03-02
- Publication Date
- 2026-06-02
AI Technical Summary
Existing slope compensation circuits in current-mode control architectures suffer from charging wait time and poor current linearity, leading to system instability and subharmonic oscillations.
A combination of signal input module, DC reference module and compensation output module is adopted. Full-range ramp compensation is achieved through the current mirror unit of NMOS and PMOS transistors. The linearity of the compensation current is ensured through the negative feedback structure. The charging waiting time is reduced by matching the parameters of the resistor and the current source.
It achieves full-range ramp compensation, reduces charging waiting time, improves current linearity, enhances system stability and applicability, and allows for convenient adjustment of the compensation ramp to achieve the appropriate compensation effect.
Smart Images
Figure CN116015061B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of switching power supply technology, specifically relating to a slope compensation circuit, a method for generating slope compensation signals, and an electronic chip. Background Technology
[0002] In switching power supply circuits, a current-mode control architecture is used. When the system's duty cycle exceeds 50%, subharmonic oscillations occur, manifesting as fluctuating conduction times. This results in large and small waves in the current waveform, which can severely disrupt system operation. To avoid these subharmonic oscillations, a slope compensation circuit is introduced to correct the inductor current waveform, thereby stabilizing system operation.
[0003] like Figure 1 The subharmonic oscillation shown typically occurs in current waveforms with large duty cycles. The solid line represents the inductor current waveform. This represents the inductor current waveform during normal operation. When a current disturbance is introduced... Afterwards, the inductor current waveform changes to the shape shown by the dashed line. As can be seen, the error in the inductor current gradually increases in subsequent cycles, leading to system instability. Furthermore, the oscillation period is mostly twice the switching period, resulting in a large duty cycle. A common suppression method is to add... Figure 2 The slope shown can be compensated by built-in slope to make the original current peak arrive earlier when the duty cycle is too large. Figure 2 The dashed line represents The solid line represents the inductor current waveform when the system becomes unstable after the occurrence of subharmonic oscillation. The waveform of the corrected inductor current after adding the slope signal is shown. It can be seen that after introducing the slope signal, i.e., slope compensation, the amplitude of the current error signal gradually decreases until it stabilizes after each cycle.
[0004] Slope compensation circuits are an indispensable module in current-mode control architectures, and their implementation methods vary. A typical compensation current generation circuit charges a compensation capacitor with current, and the resulting capacitor voltage controls and enhances the gate voltage of an NMOS transistor. The change is used to generate a compensation current.
[0005] The above compensation method has two drawbacks: 1. Before the voltage across the compensation capacitor exceeds the threshold voltage of the enhanced NMOS transistor, a ramp compensation current cannot be generated. Furthermore, the enhanced NMOS transistor requires its gate voltage to conduct. The voltage must first be greater than the threshold voltage of the NMOS transistor. Therefore, the NMOS transistor can only turn on after the compensation capacitor has been charging for a period of time; that is, there is a waiting time during the charging process. 2. Simply through the gate voltage Current generated by the change The linearity is poor because, according to the Sartre equation... The relationship between current and voltage is non-linear. Summary of the Invention
[0006] In view of the above-mentioned problems in the prior art, the purpose of this invention is to provide a simple slope compensation circuit in which NMOS transistors N1 and N2 are not affected by the charging and discharging time of the capacitor, and have the function of full-range slope compensation. Furthermore, the negative feedback structure makes the generated compensation current linear and consistent.
[0007] A simple slope compensation circuit includes:
[0008] The signal input module is used to input the control signal CON. When the external circuit does not require compensation, capacitor C1 is short-circuited.
[0009] The DC reference module is used to provide DC operating current, so that NMOS transistors N1 and N2 are fully turned on, realizing the function of full-range compensation of the ramp compensation circuit. When the external circuit does not need compensation, the compensation output module has no signal output.
[0010] The compensation output module is used to output the slope compensation signal Islope;
[0011] The DC reference module is electrically connected to the signal input module and the compensation output module, respectively.
[0012] The signal input module includes a current source I1, an NMOS transistor N2, an NMOS transistor N3, a resistor R3, and a resistor R2. One end of the current source I1 is electrically connected to the gate of the resistor R3 and the NMOS transistor N2. The source of the NMOS transistor N2 is connected to the resistor R2, and its drain is connected to the compensation output module. The other end of the resistor R2 is grounded. The other end of the resistor R3 is connected to the drain of the capacitor C1 and the NMOS transistor N3. The other end of the capacitor C1 and the source of the NMOS transistor N3 are grounded. The gate of the NMOS transistor N3 is connected to a control signal CON.
[0013] The DC reference module includes a current source I2, a resistor R1, a resistor R4, an NMOS transistor N1, and a first current mirror unit. One end of the current source I2 is electrically connected to the gate of the NMOS transistor N1 and the resistor R4. The drain of the NMOS transistor N1 is connected to the first current mirror unit, and the source is connected to the resistor R1. The other ends of the resistor R1 and the resistor R4 are grounded. The first current mirror unit is connected to the compensation output module.
[0014] Among them, the parameters of current source I1 and current source I2 are the same, the parameters of resistor I1 and resistor II R2 are the same, and the parameters of resistor III R3 and resistor IV R4 are the same.
[0015] To accurately mirror the current, the compensation output module includes a second current mirror unit, which includes a PMOS transistor P3 and a PMOS transistor P4. The gate and drain of the PMOS transistor P3 are electrically connected and are also electrically connected to the gate of the PMOS transistor P4 and the drain of the NMOS transistor N2. The drain of the PMOS transistor P4 outputs a slope compensation signal Islope.
[0016] The first current mirror unit includes a PMOS transistor P1 and a PMOS transistor P2. The gate and drain of the PMOS transistor P1 are shorted to the drain of the NMOS transistor N1. The gate of the PMOS transistor P1 is connected to the gate of the PMOS transistor P2. The drain of the PMOS transistor P2 is electrically connected to the gate and drain of the PMOS transistor P3.
[0017] To facilitate power supply, current source I1 and current source I2 are electrically connected to the power supply, and the sources of PMOS transistors P1, P2, P3, and P4 are all electrically connected to the power supply.
[0018] In a second aspect, the present invention provides a method for generating a ramp compensation signal, wherein when the control signal CON is low, the ramp compensation circuit is in a compensation phase; and when the control signal CON is high, the ramp compensation circuit is in a non-compensation phase, wherein the compensation phase includes the following process:
[0019] When a low-level control signal CON is input, the input switch NMOS transistor N3 is turned off.
[0020] Current source I1 charges capacitor C1 through resistor R3, generating a ramp voltage Vslpoe_in at the gate of NMOS transistor N2. The slope of this ramp voltage is... ;
[0021] The ramp voltage Vslope_in generates a current I_P3 through the common-source amplifier NMOS transistor N2. At this time, the changing current... ;
[0022] By mirroring the current I_P3 using PMOS transistors P3 and P4, the slope compensation current signal Islope can be obtained. When PMOS transistors P3 and P4 are identical, the slope compensation slope is... .
[0023] The non-compensation phase includes the following process:
[0024] When a high-level control signal CON is input, the input switch NMOS transistor N3 is turned on, and the charge of capacitor C1 is completely discharged.
[0025] Since the parameters of current source I1 and current source I2 are the same, and the parameters of resistor R3 and resistor R4 are the same, the gate potentials generated by NMOS transistors N1 and N2 in the common source amplifier are the same, thus ensuring that NMOS transistors N1 and N2 are always on.
[0026] Since resistors R1 and R2 have the same parameters, they generate equal currents. Therefore, the currents flowing through PMOS transistors P1 and PMOS transistor P2 in the first current mirror unit are equal.
[0027] At this time, PMOS transistors P3 and P4 in the second current mirror do not generate current, and the output ramp compensation signal Islope=0.
[0028] A third aspect of the present invention provides an electronic chip comprising:
[0029] A ramp compensation module, which is used to output a ramp compensation signal Islope;
[0030] An enable control module is used to control the enabling of the electronic chip;
[0031] An amplifier used to detect changes in the voltage of the feedback signal FB;
[0032] A comparator is used to compare the output signal of the amplifier with the output signal of the ramp compensation circuit, thereby outputting a signal that can control the duty cycle of the electronic chip.
[0033] A logic control module is used to control the logic changes of the electronic chip, including protection logic, startup logic, and power-on logic.
[0034] The driver module amplifies the logic signals output by the logic control module, thereby controlling the turn-on and turn-off of the upper and lower switching MOSFETs.
[0035] The current limiting detection module is used to detect the magnitude of the current flowing through the switching MOSFET and limit the current in the switching MOSFET to prevent the operating current of the electronic chip from being too high.
[0036] Switching MOSFETs, including NMOS transistor N4 and PMOS transistor P5.
[0037] The amplifier is an error amplifier. The inverting input terminal of the error amplifier receives a feedback signal FB, the non-inverting input terminal is connected to a threshold voltage, and the output terminal is connected to the inverting input terminal of the comparator. The output terminal is also electrically connected to a series resistor R5 and a capacitor C2. The output terminal of the comparator is connected to a logic control module. The logic control module is also connected to a current limiting detection module and a drive module. The current limiting detection module is also electrically connected to a ramp compensation circuit.
[0038] The driving module is connected to the gates of NMOS transistor N4 and PMOS transistor P5 respectively. The source of PMOS transistor P5 is connected to the current limiting detection module, and the drain is connected to the drain of NMOS transistor N4. The drains of NMOS transistor N4 and PMOS transistor P5 are both electrically connected to the SW port, and the source of NMOS transistor N4 is grounded.
[0039] The electronic chip includes a VIN port connected to the current limiting detection module, an EN port connected to the enable control module, and an FB port connected to the inverting input of the error amplifier.
[0040] The beneficial effects of this invention are as follows: the slope compensation circuit, the method for generating slope compensation signals, and the electronic chip, by adding resistors R3 and R4, raise the gate voltages of NMOS transistors N1 and N2, allowing NMOS transistors N1 and N2 to operate throughout their entire range, thus enabling the circuit to achieve full-range slope compensation. Simultaneously, through the source negative feedback resistors R1 and R2, the generated compensation current exhibits linear consistency. Furthermore, by adjusting the ratio of PMOS transistors P3 and P4, without changing the values of capacitor C1, current source I1, and current source I2, the compensation slope can be increased or decreased more conveniently to achieve a suitable compensation effect, making it highly applicable. Attached Figure Description
[0041] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:
[0042] Figure 1 It is the current waveform of subharmonic oscillation in a traditional switching power supply;
[0043] Figure 2 It is the current waveform after slope compensation for subharmonic oscillations in traditional switching power supplies;
[0044] Figure 3 This is a circuit diagram of the present invention;
[0045] Figure 4 This is a flowchart of the compensation stage of the present invention;
[0046] Figure 5 This is a flowchart of the non-compensation stage of the present invention;
[0047] Figure 6 This is a signal waveform diagram of the present invention;
[0048] Figure 7 This is a circuit block diagram of the present invention applied to electronic chips.
[0049] The diagram is labeled as follows: 101, signal input module; 102, DC reference module; 103, compensation output module. Detailed Implementation
[0050] Example 1
[0051] like Figure 3 As shown, a simple slope compensation circuit includes a signal input module, a DC reference module, and a compensation output module. The DC reference module is electrically connected to the signal input module and the compensation output module, respectively, and outputs a slope compensation signal Islope after processing the control signal CON.
[0052] The signal input module is used to input the control signal CON. When the external circuit does not require compensation, capacitor C1 is short-circuited. The DC reference module is used to provide DC operating current, so that NMOS transistors N1 and N2 are fully turned on, realizing the function of full-range compensation of the ramp compensation circuit. When the external circuit does not require compensation, the compensation output module has no signal output. The compensation output module is used to output the ramp compensation signal Islope.
[0053] like Figure 3 As shown, the signal input module 101 includes a current source I1, an NMOS transistor N2, an NMOS transistor N3, a resistor R3, and a resistor R2. The NMOS transistor N3 serves as an input switch, and the NMOS transistor N2 serves as a common-source amplifier.
[0054] Specifically, current source I1 is electrically connected to the power supply. One end of current source I1 is electrically connected to resistor R3 and the gate of NMOS transistor N2. The source of NMOS transistor N2 is connected to resistor R2, and its drain is connected to compensation output module 103. The other end of resistor R2 is grounded. The other end of resistor R3 is connected to capacitor C1 and the drain of NMOS transistor N3. The other end of capacitor C1 and the source of NMOS transistor N3 are grounded. The gate of NMOS transistor N3 is connected to control signal CON.
[0055] like Figure 3As shown, the DC reference module 102 includes a current source I2, a resistor R1, a resistor R4, an NMOS transistor N1, and a first current mirror unit. The current source I2 is electrically connected to the power supply. One end of the current source I2 is electrically connected to the gate of the NMOS transistor N1 and the resistor R4. The drain of the NMOS transistor N1 is connected to the first current mirror unit, and its source is connected to the resistor R1. The other ends of the resistors R1 and R4 are grounded. The first current mirror unit is connected to the compensation output module 103. The first current mirror unit includes a PMOS transistor P1 and a PMOS transistor P2. The gate and drain of the PMOS transistor P1 are shorted to the drain of the NMOS transistor N1. The gate of the PMOS transistor P1 is connected to the gate of the PMOS transistor P2. The drain of the PMOS transistor P2 is electrically connected to the gate and drain of the PMOS transistor P3. The sources of both the PMOS transistor P1 and the PMOS transistor P2 are electrically connected to the power supply.
[0056] Specifically, to ensure that the gate potentials of NMOS transistors N1 and N2 in the common-source amplifier are the same, thus keeping NMOS transistors N1 and N2 always on and reducing charging wait time, the parameters of current sources I1 and I2, as well as the parameters of resistors R3 and R4, need to be identical. Similarly, to ensure that the currents of PMOS transistors P1 and P2 in the first current mirror unit are equal, thereby preventing PMOS transistors P3 and P4 in the second current mirror from generating current, the parameters of resistors R1 and R2 need to be identical.
[0057] like Figure 3 As shown, the compensation output module 103 includes a second current mirror unit, which includes a PMOS transistor P3 and a PMOS transistor P4. The gate and drain of the PMOS transistor P3 are electrically connected and are also electrically connected to the gate of the PMOS transistor P4 and the drain of the NMOS transistor N2. The drain of the PMOS transistor P4 outputs a slope compensation signal Islope. The sources of both the PMOS transistor P3 and the PMOS transistor P4 are electrically connected to the power supply.
[0058] Example 2
[0059] like Figure 4 , Figure 5 As shown, in a second aspect, the present invention provides a method for generating a ramp compensation signal, wherein when the control signal CON is low, the ramp compensation circuit is in the compensation stage; and when the control signal CON is high, the ramp compensation circuit is in the non-compensation stage.
[0060] like Figure 4 As shown, specifically, the compensation phase includes the following processes:
[0061] When a low-level control signal CON is input, the input switch NMOS transistor N3 is turned off.
[0062] Current source I1 charges capacitor C1 through resistor R3, generating a ramp voltage Vslpoe_in at the gate of NMOS transistor N2. The slope of this ramp voltage is... ;
[0063] The ramp voltage Vslope_in generates a current I_P3 through the common-source amplifier NMOS transistor N2. At this time, the changing current... ;
[0064] By mirroring the current I_P3 using PMOS transistors P3 and P4, the slope compensation current signal Islope can be obtained. When PMOS transistors P3 and P4 are identical, the slope compensation slope is... .
[0065] like Figure 5 As shown, specifically, the non-compensation phase includes the following processes:
[0066] When a high-level control signal CON is input, the input switch NMOS transistor N3 is turned on, and the charge of capacitor C1 is completely discharged.
[0067] Since the parameters of current source I1 and current source I2 are the same, and the parameters of resistor R3 and resistor R4 are the same, the gate potentials generated by NMOS transistors N1 and N2 in the common source amplifier are the same, thus ensuring that NMOS transistors N1 and N2 are always on.
[0068] Since resistors R1 and R2 have the same parameters, they generate equal currents. Therefore, the currents flowing through PMOS transistors P1 and PMOS transistor P2 in the first current mirror unit are equal.
[0069] At this time, PMOS transistors P3 and P4 in the second current mirror do not generate current, and the output ramp compensation signal Islope=0.
[0070] In practical applications, if the compensation slope is insufficient or overcompensated, the ratio of PMOS transistor P3 to PMOS transistor P4 can be adjusted. Without changing the values of capacitor C1, current source I1, and current source I2, the compensation slope can be increased or decreased more easily to achieve a suitable compensation effect.
[0071] like Figure 6As shown, when the input signal GON is high, it is the system shutdown moment, and slope compensation is not required at this time; when the input signal GON is low, it is the inductor current charging moment, and the system needs to perform slope compensation.
[0072] like Figure 6 As shown, Vslope_ref is the reference voltage, and Vslope_in is the ramp voltage. When the input signal GON is high, the level of Vslope_in is equal to the level of Vslope_ref, at which point I_P1=I_P2, and the ramp compensation signal Islope=0. When the input signal GON is low, the Vslope_in signal generates a ramp voltage based on the Vslope_ref voltage. Simultaneously, the output terminal generates a corresponding ramp compensation current Islope, which can be used to compensate for the ramp compensation voltage required by the system.
[0073] Example 3
[0074] like Figure 7 As shown, in a third aspect, the present invention provides an electronic chip comprising: a ramp compensation module, an enable control module, an amplifier, a comparator, a logic control module, a drive module, a current limiting detection module, and a switching MOSFET.
[0075] The system includes: a ramp compensation module (the ramp compensation circuit described above) for outputting a ramp compensation signal Islope; an enable control module for enabling the electronic chip; an amplifier for detecting changes in the feedback signal FB voltage; a comparator for comparing the amplifier's output signal with the ramp compensation circuit's output signal to output a signal that controls the electronic chip's duty cycle; a logic control module for controlling the electronic chip's logic changes, including protection logic, startup logic, and power-on logic (this logic control is an application of existing technology and will not be elaborated here); a drive module for amplifying the logic signal output by the logic control module to control the on / off state of the two switching MOSFETs; a current limiting detection module for detecting the current flowing through the switching MOSFETs and limiting the current in the switching MOSFETs to prevent the electronic chip from burning out due to excessive operating current; and switching MOSFETs including NMOS transistor N4 and PMOS transistor P5, which control the charging and discharging of the external inductor by turning the two switching MOSFETs on and off.
[0076] The amplifier is an error amplifier. A feedback signal FB is input to the inverting input terminal of the error amplifier, and a threshold voltage (0.6V) is connected to the non-inverting input terminal. The feedback signal FB is compared with the threshold voltage 0.6V to monitor whether the chip's output is within the threshold range. The output terminal is connected to the inverting input terminal of the comparator, and is also electrically connected to a series resistor R5 and capacitor C2. R5 and C2 are used for loop compensation to ensure the chip's operational stability. The comparator's output terminal is connected to a logic control module, which is also connected to a current limiting detection module and a drive module. The current limiting detection module is also electrically connected to a ramp compensation circuit.
[0077] The driving module is connected to the gates of NMOS transistor N4 and PMOS transistor P5 respectively. The source of PMOS transistor P5 is connected to the current limiting detection module, and the drain is connected to the drain of NMOS transistor N4. The drains of NMOS transistor N4 and PMOS transistor P5 are both electrically connected to the SW port, and the source of NMOS transistor N4 is grounded.
[0078] The electronic chip includes a VIN port connected to the current limiting detection module, an EN port connected to the enable control module, and an FB port connected to the inverting input of the error amplifier. The FB port is used to input the feedback signal FB.
[0079] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A simple slope compensation circuit, characterized in that, include: The signal input module (101) is used to input the control signal CON. When the external circuit does not require compensation, capacitor C1 is short-circuited. The DC reference module (102) is used to provide DC operating current, so that NMOS transistor N1 and NMOS transistor N2 are fully turned on, realizing the function of full-range compensation of the ramp compensation circuit. When the external circuit does not need compensation, the compensation output module (103) has no signal output. The compensation output module (103) is used to output the slope compensation signal Islope; The DC reference module (102) is electrically connected to the signal input module (101) and the compensation output module (103) respectively; The signal input module (101) includes a current source I1, an NMOS transistor N2, an NMOS transistor N3, a resistor R3, and a resistor R2. One end of the current source I1 is electrically connected to the gate of the resistor R3 and the NMOS transistor N2. The source of the NMOS transistor N2 is connected to the resistor R2, and its drain is connected to the compensation output module (103). The other end of the resistor R2 is grounded. The other end of the resistor R3 is connected to the drain of the capacitor C1 and the NMOS transistor N3. The other end of the capacitor C1 and the source of the NMOS transistor N3 are grounded. The gate of the NMOS transistor N3 is connected to a control signal CON. The DC reference module (102) includes a current source I2, a resistor R1, a resistor R4, an NMOS transistor N1, and a first current mirror unit. One end of the current source I2 is electrically connected to the gate of the NMOS transistor N1 and the resistor R4. The drain of the NMOS transistor N1 is connected to the first current mirror unit, and the source is connected to the resistor R1. The other ends of the resistor R1 and the resistor R4 are grounded. The first current mirror unit is connected to the compensation output module (103). Among them, the parameters of current source I1 and current source I2 are the same, the parameters of resistor I1 and resistor II R2 are the same, and the parameters of resistor III R3 and resistor IV R4 are the same.
2. The simple slope compensation circuit according to claim 1, characterized in that, The compensation output module (103) includes a second current mirror unit, which includes a PMOS transistor P3 and a PMOS transistor P4. The gate and drain of the PMOS transistor P3 are electrically connected and are also electrically connected to the gate of the PMOS transistor P4 and the drain of the NMOS transistor N2. The drain of the PMOS transistor P4 outputs a slope compensation signal Islope.
3. The simple slope compensation circuit according to claim 2, characterized in that, The first current mirror unit includes a PMOS transistor P1 and a PMOS transistor P2. The gate and drain of the PMOS transistor P1 are shorted to the drain of the NMOS transistor N1. The gate of the PMOS transistor P1 is connected to the gate of the PMOS transistor P2. The drain of the PMOS transistor P2 is electrically connected to the gate and drain of the PMOS transistor P3.
4. The simple slope compensation circuit according to claim 3, characterized in that, The current source I1 and current source I2 are electrically connected to the power supply, and the sources of the PMOS transistors P1, P2, P3, and P4 are all electrically connected to the power supply.
5. A method for generating a ramp compensation signal, implemented by any one of claims 1 to 4, characterized in that, When the control signal CON is low, the ramp compensation circuit is in the compensation phase; when the control signal CON is high, the ramp compensation circuit is in the non-compensation phase. The compensation phase includes the following process: When a low-level control signal CON is input, the input switch NMOS transistor N3 is turned off. Current source I1 charges capacitor C1 through resistor R3, generating a ramp voltage Vslpoe_in at the gate of NMOS transistor N2. The slope of this ramp voltage is... ; The ramp voltage Vslope_in generates a current I_P3 through the common-source amplifier NMOS transistor N2. At this time, the changing current... ; By mirroring the current I_P3 using PMOS transistors P3 and P4, the slope compensation current signal Islope can be obtained. When PMOS transistors P3 and P4 are identical, the slope compensation slope is... .
6. The method for generating a ramp compensation signal according to claim 5, characterized in that, The non-compensation phase includes the following process: When a high-level control signal CON is input, the input switch NMOS transistor N3 is turned on, and the charge of capacitor C1 is completely discharged. Since the parameters of current source I1 and current source I2 are the same, and the parameters of resistor R3 and resistor R4 are the same, the gate potentials generated by NMOS transistors N1 and N2 in the common source amplifier are the same, thus ensuring that NMOS transistors N1 and N2 are always on. Since resistors R1 and R2 have the same parameters, they generate equal currents. Therefore, the currents flowing through PMOS transistors P1 and PMOS transistor P2 in the first current mirror unit are equal. At this time, PMOS transistors P3 and P4 in the second current mirror do not generate current, and the output ramp compensation signal Islope=0.
7. An electronic chip, characterized in that, include: A ramp compensation module, wherein the ramp compensation module is a simple ramp compensation circuit as described in any one of claims 1 to 4, used to output a ramp compensation signal Islope; An enable control module is used to control the enabling of the electronic chip; An amplifier used to detect changes in the voltage of the feedback signal FB; A comparator is used to compare the output signal of the amplifier with the output signal of the ramp compensation circuit, thereby outputting a signal that can control the duty cycle of the electronic chip. A logic control module is used to control the logic changes of the electronic chip, including protection logic, startup logic, and power-on logic. The driver module amplifies the logic signals output by the logic control module, thereby controlling the turn-on and turn-off of the upper and lower switching MOSFETs. The current limiting detection module is used to detect the magnitude of the current flowing through the switching MOSFET and limit the current in the switching MOSFET to prevent the operating current of the electronic chip from being too high. Switching MOSFETs, including NMOS transistor N4 and PMOS transistor P5.
8. The electronic chip according to claim 7, characterized in that, The amplifier is an error amplifier. The inverting input terminal of the error amplifier receives a feedback signal FB, the non-inverting input terminal is connected to a threshold voltage, and the output terminal is connected to the inverting input terminal of the comparator. The output terminal is also electrically connected to a series resistor R5 and a capacitor C2. The output terminal of the comparator is connected to a logic control module. The logic control module is also connected to a current limiting detection module and a drive module. The current limiting detection module is also electrically connected to a ramp compensation circuit. The driving module is connected to the gates of NMOS transistor N4 and PMOS transistor P5 respectively. The source of PMOS transistor P5 is connected to the current limiting detection module, and the drain is connected to the drain of NMOS transistor N4. The drains of NMOS transistor N4 and PMOS transistor P5 are both electrically connected to the SW port, and the source of NMOS transistor N4 is grounded. The electronic chip includes a VIN port connected to the current limiting detection module, an EN port connected to the enable control module, and an FB port connected to the inverting input of the error amplifier.