An active clamp flyback AC-DC converter

Abstract

The present invention discloses an active-clamp flyback AC-DC converter, comprising a flyback converter power stage circuit and a control chip. The control chip includes a startup and power supply module, a line voltage detection module, a mode control module, a dead-band control module, a main loop control module, and a control logic module. The AC-DC converter employs an active-clamp system architecture, which reduces switching losses and improves overall power density compared to traditional RCD clamping structures. The AC-DC converter incorporates a pseudo-random frequency jitter function, which reduces the system's external electromagnetic radiation. Furthermore, the optimized dead-band control function rapidly achieves zero-voltage switching of the power transistor during frequency jitter, improving overall system efficiency.

Description

Technical Field

[0001] The invention belongs to the technical field of switching power supply control, and in particular relates to an active clamp flyback AC-DC converter. Background Art

[0002] With the popularity of mobile electronic devices such as laptops, tablets, and mobile phones, people have placed higher demands on the effective use time of portable electronic devices. To shorten charging time, adapter manufacturers usually adopt the solution of increasing the output power of the adapter; to improve the portability of the adapter, manufacturers usually focus on increasing the power density of the adapter to reduce its size; to meet the external power supply energy efficiency standards of AC-DC converters and improve the user experience, manufacturers also need to focus on improving the efficiency of the adapter to reduce heat. Therefore, high power, miniaturization, and high efficiency are the three major trends in the current development of AC-DC converters.

[0003] Flyback converters are widely used in low- and medium-power adapters below 100W due to their simple structure and low cost. Flyback converters are primarily categorized into two types: RCD flyback converters and active clamp flyback converters. RCD flyback converters combined with quasi-resonant control are widely used in low-frequency adapters below 65W. However, with the increasing demand for higher power, efficiency, and size in adapters, the inevitable switching losses and leakage inductance energy dissipation of RCD flyback converters have become a major challenge, limiting their application in higher-power adapters.

[0004] The active clamp flyback converter can effectively recover the leakage inductance energy and reduce the switching loss of the switch tube through the reasonable operation of the two complementary switches. In general, the active clamp flyback converter has the following advantages over the RCD flyback converter: First, the energy in the leakage inductance is recovered instead of being dissipated in the absorption resistor, which reduces the system loss; second, the main power tube Q L The drain-source voltage at Q L The active clamping process provides a more ideal waveform for the secondary-side synchronous rectification, eliminating high-frequency oscillations in the secondary current and reducing system noise. Therefore, the active clamp flyback converter is more suitable for small and medium-power power adapters, effectively improving system efficiency and power density, and facilitating adapter power increase, efficiency improvement, and miniaturization.

[0005] Although active-clamp flyback converters offer advantages over RCD flyback converters, such as recovering leakage inductance energy, reducing switching losses, and lowering voltage stress, as operating frequencies increase, the rapidly changing current and voltage within the system generate strong external electromagnetic radiation, which has become a major challenge. To address the electromagnetic interference problem caused by the high-frequency operation of active-clamp flyback converters, frequency-jittering technology has been widely used. However, the change in switching frequency affects the zero-voltage turn-on of the power transistors, reducing system efficiency.

[0006] The literature [Zhou Zheng. Research on frequency jitter technology to suppress converter electromagnetic interference. Nanjing University of Aeronautics and Astronautics, 2008.] adopts two methods to achieve the frequency jitter function and reduce the electromagnetic interference of the flyback converter. One method is to combine the external modulation signal with the traditional PWM control chip, and the other method is to implement it with digital software. Both methods are complex to implement and have low integration. The frequency jitter finally achieved in this literature is periodic, and its EMI reduction effect is not good.

[0007] Chinese patent publication number CN103078489A provides a system and method for reducing electromagnetic interference by utilizing switching frequency jitter. It introduces an RCD flyback converter system operating in quasi-resonant mode using frequency jitter technology. Frequency jittering is achieved by changing the oscillator frequency, which increases system power consumption. Furthermore, applying this technology to an active clamp flyback system can result in significant system losses.

[0008] Existing publicly available frequency jittering technologies are all based on the research of RCD flyback converters, and most of them adopt periodic frequency jittering schemes. When applied to active clamp flyback systems, the EMI reduction effect is low and the system efficiency is affected. Summary of the Invention

[0009] In view of the above, the present invention provides an active clamp flyback AC-DC converter, which uses a pseudo-random frequency jitter scheme combined with a fast ZVS implementation scheme to reduce the system's external electromagnetic interference and improve the operating frequency and overall efficiency.

[0010] An active clamp flyback AC-DC converter includes an active clamp flyback converter and a control chip thereof. The active clamp flyback converter includes a main power tube Q L , clamping tube Q H , transformer, sampling resistor Rs, high voltage detection circuit, line voltage detection circuit and output voltage detection circuit, where:

[0011] The high voltage detection circuit includes a power dissipation device Q1, a Zener diode D1 and a filter capacitor Cs, wherein the drain of Q1 is connected to Q LThe drain of Q1 is connected to the gate of Q1, the gate of Q1 is connected to the fixed bias voltage Vb, the source of Q1 is connected to one end of Cs and the cathode of D1 and serves as the SW point, the other end of Cs is connected to the anode of D1 and one end of the sampling resistor Rs and is grounded, and the other end of the sampling resistor Rs is connected to Q L The source is connected to generate an excitation current voltage Vcs;

[0012] The output voltage detection circuit includes an optocoupler A1, a bias resistor Rbias, and a compensation capacitor C INT1 and C INT2 , compensation resistor R INT1 , output voltage sampling resistor R 01 and R 02 and a three-pin adjustable shunt regulator A2, where one end of Rbias is connected to R 01 One end of Rbias is connected to the output voltage end of the flyback converter, the other end of Rbias is connected to the anode of the optocoupler A1, the emitter of the optocoupler A1 is grounded, the collector of the optocoupler A1 generates a feedback current FB, and the cathode of the optocoupler A1 is connected to R INT1 One end, C INT1 One end of the shunt regulator A2 is connected to the cathode, R INT1 The other end of the C INT2 One end is connected to C INT2 The other end of the C INT1 The other end, R 01 The other end, R 02 One end of the shunt regulator A2 is connected to the reference voltage terminal, R 02 The other end and the anode of the shunt regulator A2 are grounded;

[0013] The line voltage detection circuit includes an auxiliary winding, line voltage sampling resistors Rv1 and Rv2, a diode D0 and a capacitor C0, wherein the auxiliary winding is coupled with the primary and secondary windings of the transformer, the same-name end of the auxiliary winding is connected to one end of Rv2 and grounded, the other end of Rv2 is connected to one end of Rv1 and serves as a line voltage sampling end, the other end of Rv1 is connected to the opposite-name end of the auxiliary winding and the anode of D0, the cathode of D0 is connected to one end of C0, and the other end of C0 is connected to the power supply voltage VDD;

[0014] The control chip includes:

[0015] The startup and power supply module is used to draw power from the SW point during the system startup phase and from the auxiliary winding during the normal operation phase, and then convert it to power the entire chip;

[0016] The line voltage detection compensation module detects the input line voltage V through the line voltage sampling terminal BULK , and then according to V BULKCalculate the compensation value I_line of the power tube dead time;

[0017] A mode control module is used to detect the feedback current FB and generate an operating mode signal Vcst_pre for controlling the system according to the feedback current FB;

[0018] Dead zone control module, used to detect the main power tube Q L The voltage of SW point when it is turned on, and then according to the main power tube Q L The ZVS (zero voltage switching) condition generates the clamping transistor Q H The on-time adjustment value I_tune;

[0019] The main loop control module calculates and generates the excitation current threshold voltage signal Vcst and the clamping tube Q according to the working mode signal Vcst_pre, the compensation value I_line and the on-time adjustment value I_tune H The turn-on voltage threshold Vct;

[0020] The control logic module is used to detect the excitation current voltage Vcs, and then generate the main power tube Q according to the signals Vcst and Vct. L and clamping tube Q H The switching signal.

[0021] Furthermore, the mode control module adjusts the operating mode of the system according to the size of the feedback current FB and generates an operating mode signal Vcst_pre for controlling the control system as a preliminary value of the excitation current threshold voltage; when the system load is heavy, the control system operates in an amplitude modulation mode with a fixed negative current; when the load is reduced to a certain extent, the control system operates in a burst mode.

[0022] Furthermore, the dead zone control module includes:

[0023] ZVS detection circuit, in the main power tube Q L When the switch is turned on, the SW point voltage is detected. When the SW point voltage is detected to drop to the set threshold, the Pulse_ZVS signal is output; when the SW point voltage is detected not to drop to the set threshold, the Pulse_NZVS signal is output.

[0024] The ZVS state monitoring circuit is based on the main power tube Q of multiple switching cycles. L The ZVS condition (Pulse_ZVS signal and Pulse_NZVS signal) outputs an adjustment signal Trim of a change step size to the adaptive adjustment circuit;

[0025] Adaptive adjustment circuit, generates clamping tube Q according to the output signal of ZVS detection circuit and ZVS status monitoring circuit H The on-time adjustment amount I_tune.

[0026] Furthermore, when the Pulse_NZVS signal is received, the adaptive adjustment circuit increases the on-time adjustment value I_tune by one unit, so as to increase the clamping tube Q in the next cycle. H The on-time of the clamping tube Q is increased to meet the set ideal dead time. When the Pulse_ZVS signal is received, the adaptive adjustment circuit reduces the on-time adjustment value I_tune by one unit to reduce the clamping tube Q in the next cycle. H The on-time is used to reduce the negative current so that it meets the set ideal dead time; when the Pulse_ZVS signal or the Pulse_NZVS signal is received for multiple consecutive cycles, the ZVS state monitoring circuit outputs the adjustment signal Trim as a high level, and the adaptive adjustment circuit increases the size of the unit amount to accelerate the ZVS adjustment process.

[0027] Furthermore, the main loop control module includes:

[0028] A frequency dithering circuit generates a current I_dither based on pseudo-random frequency dithering at a certain frequency;

[0029] The on-threshold generation circuit calculates and generates an excitation current threshold voltage signal Vcst and an on-voltage threshold Vct according to the compensation value I_line, the working mode signal Vcst_pre, the current value I_dither, and the on-time adjustment value I_tune.

[0030] Furthermore, the frequency jitter circuit includes a pseudo-random number generation module, seven analog switches K0 to K6, five capacitors C1 to C5, two current sources I1 and I2, an operational amplifier AMP0, an NMOS tube MN1, a resistor R0, and two PMOS tubes MP1 and MP2, wherein the pseudo-random number generation module is used to generate a 4-bit pseudo-random number, and the 4-bit digital number is used to control the on and off of K0, K1, K2, and K3 from high to low, respectively. The input end of the current source I1 is connected to the power supply voltage VDD, the output end of the current source I1 is connected to one end of K4, the other end of K4 is connected to one end of K0, one end of K1, one end of K2, one end of K3, one end of K5, and one end of K6, the other end of K5 is connected to the input end of the current source I2, the output end of the current source I2 is grounded, the other end of K0 is connected to one end of C1, the other end of C1 is grounded, the other end of K1 is connected to one end of C2, the other end of C2 is grounded, and the other end of K2 is connected to one end of C3. The control terminal of K4 is connected to the clock signal CLK1, the control terminal of K6 is connected to the clock signal CLK2, and the control terminal of K5 is connected to the clock signal CLK3. In one switching cycle, the falling edge of CLK3 corresponds to the rising edge of CL1, the falling edge of CL1 corresponds to the rising edge of CL2, and a certain dead time is left between the falling edge of CL2 and the rising edge of CLK3.

[0031] Furthermore, the capacitance ratio of the capacitors C1 to C4 is 8:4:2:1.

[0032] Furthermore, the conduction threshold generating circuit includes two operational amplifiers AMP1 and AMP2, five resistors R1 to R5, three current sources I3 to I5, an NMOS transistor MN2, a capacitor C6, and two PMOS transistors MP3 and MP4, wherein the source of MP3 is connected to the source of MP4 and is connected to the power supply voltage VDD, the positive input terminal of AMP1 is connected to Vcst_pre, the negative input terminal of AMP1 is connected to the source of MN2 and one end of R1, the other end of R1 is grounded, the drain of MN2 is connected to the drain of MP3, the gate of MP3 and the gate of MP4, the input terminals of the current sources I3 to I5 are all connected to the power supply voltage VDD, MP 4 is connected to one end of R2, the output end of current source I3 and the non-inverting input end of AMP2, the other end of R2 is grounded, the output end of current source I4 is connected to the output end of current source I5 and one end of R5 to generate a turn-on voltage threshold Vct, the other end of R5 is connected to the inverting input end of AMP2, the output end of AMP2 and one end of R4, the other end of R4 is connected to one end of C6 and one end of R3 to generate an excitation current threshold voltage signal Vcst, the other end of R3 and the other end of C6 are grounded, the size of current source I3 is I_dither, the size of current source I4 is I_line, and the size of current source I5 is I_tune.

[0033] The AC-DC converter device of the present invention adopts an active clamping system architecture, which can reduce switching losses and improve the power density of the entire device compared to the traditional RCD clamping structure. The AC-DC converter device of the present invention includes a pseudo-random frequency jitter function, which can reduce the system's external electromagnetic radiation. In addition, the optimized dead-zone control function of the present invention can quickly achieve zero-voltage switching of the power tube during the frequency jitter process, thereby improving the overall efficiency of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 The figure is a schematic diagram of the overall structure of the active clamp flyback AC-DC converter of the present invention.

[0035] Figure 2 Schematic diagram of the heavy-load operating mode of the active clamp flyback converter.

[0036] Figure 3 Schematic diagram of signal transmission between the ZVS detection module and the ZVS status monitoring module.

[0037] Figure 4 This is the input and output signal timing diagram of the ZVS status monitoring module.

[0038] Figure 5 Schematic diagram of the structure of the adaptive adjustment circuit.

[0039] Figure 6 This is a structural diagram of the frequency jitter module.

[0040] Figure 7 This is the switching timing diagram of the frequency jitter module.

[0041] Figure 8 This is a structural diagram of the conduction threshold generation module. DETAILED DESCRIPTION

[0042] In order to describe the present invention more specifically, the technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0043] like Figure 1 As shown, the active clamp flyback AC-DC converter of the present invention includes a power stage circuit and a control chip of an active clamp flyback converter. The flyback converter is added with a voltage detection circuit and a line voltage detection circuit. The voltage detection circuit includes a power consumption circuit Q1, a diode D1 and a capacitor Cs. The drain of the power consumption circuit Q1 is connected to the main power tube Q L The drain of the main power tube Q L The source of Q1 is connected to one end of the sampling resistor Rs. The gate of Q1 is connected to a fixed bias voltage Vb. The source of Q1 is connected to the cathode of Zener diode D1 and one end of capacitor Cs. The cathode of Zener diode D1 and the other end of capacitor Cs are connected to the other end of sampling resistor Rs and to ground. The line voltage detection circuit includes a transformer auxiliary winding T0, sampling resistors Rv1 and RV2, a diode D0, and a capacitor C0. The opposite-signal terminal of the transformer auxiliary winding T0 is connected to the anode of diode D0 and to one end of the sampling resistor Rv1. The same-signal terminal of the transformer auxiliary winding T0 is connected to one end of the sampling resistor Rv2. The other ends of the sampling resistors Rv1 and Rv2 are connected and connected to the control chip. The other end of diode D0 is connected to the other end of capacitor C0, and the other end of capacitor C0 is connected to the control chip.

[0044] The control chip includes a startup and power supply module, a line voltage detection module, a mode control module, a dead zone control module, a main loop control module, and a control logic module.

[0045] The startup and power supply module is used to take power from the SW point during the system startup phase. During the normal operation phase, it takes power from the auxiliary winding T0 and converts it to power the entire chip.

[0046] The line voltage detection compensation module is used to detect the line voltage V from the auxiliary winding T0. BULK , according to the line voltage V BULK Calculate the compensation amount I_line of the power tube dead time.

[0047] The mode control module detects the feedback current FB from optocoupler A1, adjusts the system's operating mode based on the magnitude of the feedback current FB, and determines the preliminary value of the excitation current threshold voltage, Vcst_pre. When the system is heavily loaded, the control system operates in fixed negative current amplitude modulation mode. When the load is reduced to a certain level, the system operates in burst mode.

[0048] Figure 2 The waveform of the active clamp flyback converter in heavy load mode is shown below. As the load decreases, the system operates in the peak current control mode where the negative current ILM.neg is fixed and the peak current ILM.pk is automatically adjusted. During normal operation, when Sm is high, the main power tube Q L When the power is turned on, the inductor is excited by the power supply, and the excitation inductor current and the leakage inductor current increase linearly; when Sm becomes low, the main power tube Q L Shut down, main power tube Q L Turn off to clamp tube Q H During the dead time of the on state, the magnetizing inductance current and the leakage inductance current give the main power tube Q L The junction capacitance of the drain node is charged, causing the drain voltage to rise rapidly to near Vbulk+NVo, and the SW node potential rises to Vb+Vth(Q1); when Sc is high, the clamping tube Q is turned on. H , in the clamping tube Q H During the on-time Tc, the leakage inductance resonates with the clamping capacitor, and the difference between the excitation inductance current and the leakage inductance current transfers energy to the secondary side. During this stage, the excitation inductance current drops to negative; when Sc is low, the clamping tube Q is turned off. H , clamping tube Q H After shutdown, the reverse excitation current and leakage current will draw the main power tube Q L The drain node charge and SW point voltage will continue to drop during Tdm. If the main power tube Q is turned on after the SW voltage drops to 0, L , at this time, the main power tube Q can be realized L Zero voltage turn-on.

[0049] The dead zone control module includes a ZVS detection module, a ZVS status monitoring module and an adaptive adjustment circuit; Figure 3 As shown, the ZVS detection module is in the main power tube Q L Detect SW voltage at the time of opening. If the main power tube Q L If the voltage at the SW point does not drop to the set threshold when the switch is turned on, the clamping tube Q will be increased in the next cycle. H The conduction time Tc is used to increase the negative current so that it meets the set ideal dead time; if the main power tube Q L When the SW point voltage drops to the set threshold when it is turned on, the clamping tube Q is reduced in the next cycle. HThe conduction time Tc is used to reduce the negative current so that it meets the set ideal dead time. The specific implementation method is as follows: if the voltage at the SW point does not drop to the set threshold, the ZVS detection module outputs a pulse signal Pulse_NZVS with a fixed pulse width. If the voltage at the SW point drops to the set threshold, the ZVS detection module outputs a pulse signal Pulse_ZVS with a fixed pulse width. Pulse_ZVS and Pulse_NZVS are used to control the charge and discharge switches of the adaptive adjustment circuit to adjust the clamping tube Q. H The on-time of Figure 3 The ZVS state monitoring circuit in the system monitors the ZVS detection results of multiple cycles. If the system detects the same pulse signal for five consecutive cycles, the Trim signal output in the next cycle is high, which changes the charge and discharge current of the adaptive adjustment module, that is, the clamping tube Q in each cycle. H The adjustment amount of the conduction time. Once the system ZVS state changes, the Tim signal will be reset and the original fine-tuning process will be restored. Figure 4 The figure shows the specific adjustment signal changes of the ZVS status monitoring module.

[0050] Figure 5 The adaptive adjustment circuit shown in the figure adjusts the clamping tube Q in each switching cycle according to the output signals of the ZVS detection module and the ZVS status monitoring module. H The on-time of the capacitor C1 is adjusted. Current sources I1 and I2 are the charging currents of the capacitor C1. I1 is n times that of I2. When Trim is at a high level, the charging current becomes n+1 times that of fine tuning to increase the increase of I_tune in each cycle. Current sources I3 and I4 are the discharge currents of the capacitor C1. I4 is n times that of I3. The size of I3 is equal to that of I2. When Trim is at a high level, the discharge current becomes n+1 times that of fine tuning to increase the decrease of I_tune in each cycle. Switches k1 to K4 are charge and discharge control switches. When the Pulse_ZVS pulse comes, switches K1 and K4 are turned on to discharge capacitor C1 for a period of time to reduce I_tune by one unit amount. When the Pulse_NZVS pulse comes, switches K2 and K3 are turned on to charge capacitor C1 for a certain period of time to increase I_tune by one unit amount. At other times when Pulse_ZVS and Pulse_NZVS are low, switches K1 and K2 are opened, and AMP2 is connected in a unity gain form to stabilize the initial voltage of each charge and discharge cycle. Figure 5 AMP3, MN2, R7, MP1, and MP2 form the output circuit for the clamping transistor on-time adjustment value I_tune, with output I_tune = Vc1 / R7. The circuit consisting of AMP1, MN1, MP3, R6, MN2, and MN3 sets the upper limit of the voltage on C1, Vc1_limit = V1 (assuming R6 = R7).

[0051] The main loop control module includes a frequency jitter module and a conduction threshold generation module. The frequency jitter module generates a pseudo-random frequency jitter current I_dither at a certain frequency. The pseudo-random frequency jitter function is achieved by Figure 6 The frequency dithering circuit structure shown is implemented, where I1 and I2 are fixed charge and discharge currents, C1 to C4 are a capacitor array with a capacitance ratio of 8:4:2:1, and their access is controlled by the high level of the outputs K0 to K3 (K0 is the high bit of the counter output, K3 is the low bit) of the pseudo-random number generation module; switch K6 and capacitor C5 form a voltage sampling circuit, AMP0 and MN1, R0, MP1, and MP2 form the output stage, and the frequency dithering current I_dither is output according to the voltage of capacitor C5. The pseudo-random number generation module is reset to 1000 after power-on. It updates the pseudo-random number at the beginning of each frequency jitter cycle, changes the total connection capacity of capacitors C1 to C4, and then opens CLK1 for a fixed time. Current I1 charges the capacitor array. After charging is completed, K4 is turned off, K6 is turned on to sample the voltage on capacitor C5, and then K6 is disconnected and K5 is closed to discharge the capacitor array. The final output is the current I_dither that affects the excitation current threshold voltage signal Vcst, achieving pseudo-random jitter of the switching frequency and reducing the system's external electromagnetic radiation. The switching timing relationship between sampling and charging and discharging is as follows: Figure 7 As shown, because the active clamp flyback converter usually operates at a very high operating frequency and the loop response speed is fast, the effect of frequency jittering will be weakened to a certain extent. At the same time, in order to avoid introducing new audio noise, the carrier frequency of the frequency jittering is set to be above 20Khz in the present invention.

[0052] The conduction threshold generation module obtains the excitation current threshold voltage signal Vcst and the clamping tube Q according to the output of the line voltage monitoring module I_line, the output of the mode control module Vcst_pre, the output of the frequency jitter module I_dither and the conduction time adjustment I_tune. H The turn-on voltage threshold Vct. Figure 8 As shown, Vcst_Pre is converted into a current by the conversion circuit composed of AMP1, MN2, R1, MP3, and MP4, and then added to the current I_dither and converted into a voltage by R2. The voltage is output as Vcst by the output stage composed of AMP2, R5, R3, and R4 and loaded onto the voltage-stabilizing capacitor C6. The resistors R1, R2 and R0 in the frequency dithering module are set to a proportional relationship of unit resistance to improve impedance matching.

[0053] In order to reduce the hard switching problem caused by system state changes during frequency jitter, the output stage compensates the clamping tube conduction voltage threshold Vct according to the excitation inductor current threshold Vcst. The excitation current voltage threshold Vcst = (I_dither + Vcst_pre / R1) * R2 * R3 / (R3 + R4), and the clamping tube conduction voltage threshold Vct = Vcst * (1 + R4 / R3) + (I_line + I_tune) * R4. Because the excitation current voltage threshold Vcst includes the pseudo-random frequency jitter current I_dither, the main power tube Q L The on-time of the switch will undergo pseudo-random changes, thereby realizing pseudo-random jitter of the switching frequency, thereby reducing the system's external electromagnetic radiation; because the clamping tube's on-voltage threshold Vct is compensated to a certain extent according to the change of the excitation inductor current threshold Vcst, the system fluctuation can be reduced during the frequency jitter process, the realization of zero voltage switching can be accelerated, and the system loss can be reduced.

[0054] Excitation current threshold voltage Vcst and clamping tube Q H The turn-on voltage threshold Vct is converted into the main power tube Q in the control logic module. L Shutdown and clamping tube Q H Shutdown control signal.

[0055] The above description of the embodiments is intended to facilitate understanding and application of the present invention by those skilled in the art. It is apparent that those skilled in the art can readily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without requiring creative effort. Therefore, the present invention is not limited to the above embodiments. Any improvements or modifications made by those skilled in the art based on the disclosure of the present invention should fall within the scope of protection of the present invention.

Claims

1. An active clamp flyback AC-DC converter, comprising an active clamp flyback converter and a control chip thereof, wherein the active clamp flyback converter comprises a main power tube Q L , clamping tube Q H , transformer, sampling resistor Rs, high voltage detection circuit, line voltage detection circuit and output voltage detection circuit, characterized in that: The high voltage detection circuit includes a power dissipation device Q1, a Zener diode D1 and a filter capacitor Cs, wherein the drain of Q1 is connected to Q L The drain of Q1 is connected to the gate of Q1, the gate of Q1 is connected to the fixed bias voltage Vb, the source of Q1 is connected to one end of Cs and the cathode of D1 and serves as the SW point, the other end of Cs is connected to the anode of D1 and one end of the sampling resistor Rs and is grounded, and the other end of the sampling resistor Rs is connected to Q L The source is connected to generate an excitation current voltage Vcs; The output voltage detection circuit includes an optocoupler A1, a bias resistor Rbias, and a compensation capacitor C INT1 and C INT2 , compensation resistor R INT1 , output voltage sampling resistor R 01 and R 02 and a three-pin adjustable shunt regulator A2, where one end of Rbias is connected to R 01 One end of Rbias is connected to the output voltage end of the flyback converter, the other end of Rbias is connected to the anode of the optocoupler A1, the emitter of the optocoupler A1 is grounded, the collector of the optocoupler A1 generates a feedback current FB, and the cathode of the optocoupler A1 is connected to R INT1 One end, C INT1 One end of the shunt regulator A2 is connected to the cathode, R INT1 The other end of the C INT2 One end is connected to C INT2 The other end of the C INT1 The other end, R 01 The other end, R 02 One end of the shunt regulator A2 is connected to the reference voltage terminal, R 02 The other end and the anode of the shunt regulator A2 are grounded; The line voltage detection circuit includes an auxiliary winding, line voltage sampling resistors Rv1 and Rv2, a diode D0 and a capacitor C0, wherein the auxiliary winding is coupled with the primary and secondary windings of the transformer, the same-name end of the auxiliary winding is connected to one end of Rv2 and grounded, the other end of Rv2 is connected to one end of Rv1 and serves as a line voltage sampling end, the other end of Rv1 is connected to the opposite-name end of the auxiliary winding and the anode of D0, the cathode of D0 is connected to one end of C0, and the other end of C0 is connected to the power supply voltage VDD; The control chip includes: The startup and power supply module is used to draw power from the SW point during the system startup phase and from the auxiliary winding during the normal operation phase, and then convert it to power the entire chip; The line voltage detection compensation module detects the input line voltage V through the line voltage sampling terminal BULK , and then according to V BULK Calculate the compensation value I_line of the power tube dead time; A mode control module is used to detect the feedback current FB and generate an operating mode signal Vcst_pre for controlling the system according to the feedback current FB; Dead zone control module, used to detect the main power tube Q L The voltage of SW point when it is turned on, and then according to the main power tube Q L The ZVS condition generates the clamping tube Q H The on-time adjustment value I_tune; The main loop control module calculates and generates the excitation current threshold voltage signal Vcst and the clamping tube Q according to the working mode signal Vcst_pre, the compensation value I_line and the on-time adjustment value I_tune H The turn-on voltage threshold Vct; The control logic module is used to detect the excitation current voltage Vcs, and then generate the main power tube Q according to the signals Vcst and Vct. L and clamping tube Q H The switching signal.

2. The active clamp flyback AC-DC converter according to claim 1, wherein: The mode control module adjusts the system's operating mode according to the size of the feedback current FB and generates an operating mode signal Vcst_pre for the control system as a preliminary value of the excitation current threshold voltage; when the system load is heavy, the control system operates in an amplitude modulation mode with a fixed negative current; when the load is reduced to a certain extent, the control system operates in a burst mode.

3. The active clamp flyback AC-DC converter according to claim 1, wherein: The dead zone control module includes: ZVS detection circuit, in the main power tube Q L When the switch is turned on, the SW point voltage is detected. When the SW point voltage is detected to drop to the set threshold, the Pulse_ZVS signal is output; when the SW point voltage is detected not to drop to the set threshold, the Pulse_NZVS signal is output. The ZVS state monitoring circuit is based on the main power tube Q of multiple switching cycles. L The ZVS condition outputs a step-size adjustment signal Trim to the adaptive adjustment circuit; Adaptive adjustment circuit, generates clamping tube Q according to the output signal of ZVS detection circuit and ZVS status monitoring circuit H The on-time adjustment amount I_tune.

4. The active clamp flyback AC-DC converter according to claim 3, wherein: When the Pulse_NZVS signal is received, the adaptive adjustment circuit increases the on-time adjustment value I_tune by one unit to increase the clamping tube Q in the next cycle. H The on-time of the clamping tube Q is increased to meet the set ideal dead time. When the Pulse_ZVS signal is received, the adaptive adjustment circuit reduces the on-time adjustment value I_tune by one unit to reduce the clamping tube Q in the next cycle. H The on-time is used to reduce the negative current so that it meets the set ideal dead time; when the Pulse_ZVS signal or the Pulse_NZVS signal is received for multiple consecutive cycles, the ZVS state monitoring circuit outputs the adjustment signal Trim as a high level, and the adaptive adjustment circuit increases the size of the unit amount to accelerate the ZVS adjustment process.

5. The active clamp flyback AC-DC converter according to claim 1, wherein: The main loop control module includes: A frequency dithering circuit generates a current I_dither based on pseudo-random frequency dithering at a certain frequency; The on-threshold generation circuit calculates and generates an excitation current threshold voltage signal Vcst and an on-voltage threshold Vct according to the compensation value I_line, the working mode signal Vcst_pre, the current value I_dither, and the on-time adjustment value I_tune.

6. The active clamp flyback AC-DC converter according to claim 5, wherein: The frequency jitter circuit includes a pseudo-random number generation module, seven analog switches K0-K6, five capacitors C1-C5, two current sources I1 and I2, an operational amplifier AMP0, an NMOS transistor MN1, a resistor R0, and two PMOS transistors MP1 and MP2. The pseudo-random number generation module is used to generate a 4-bit pseudo-random number. The 4-bit digital number is used to control the on and off of K0, K1, K2, and K3 from high to low. The input end of the current source I1 is connected to the power supply voltage VDD, the output end of the current source I1 is connected to one end of K4, the other end of K4 is connected to one end of K0, one end of K1, one end of K2, one end of K3, one end of K5, and one end of K6, the other end of K5 is connected to the input end of the current source I2, the output end of the current source I2 is grounded, the other end of K0 is connected to one end of C1, the other end of C1 is grounded, the other end of K1 is connected to one end of C2, the other end of C2 is grounded, and the other end of K2 is connected to one end of C3. The other end of C3 is connected to ground, the other end of K3 is connected to one end of C4, the other end of C4 is grounded, the other end of K6 is connected to one end of C5 and the non-inverting input end of AMP0, the other end of C5 is grounded, the inverting input end of AMP0 is connected to the source of MN1 and one end of R0, the other end of R0 is grounded, the output end of AMP0 is connected to the gate of MN1, the drain of MN1 is connected to the drain of MP1, the gate of MP1 and the gate of MP2, the source of MP1 is connected to the source of MP2 and is connected to the power supply voltage VDD, the drain of MP2 generates a current I_dither, the control end of K4 is connected to the clock signal CLK1, the control end of K6 is connected to the clock signal CLK2, and the control end of K5 is connected to the clock signal CLK3; in one switching cycle, the falling edge of CLK3 corresponds to the rising edge of CL1, the falling edge of CL1 corresponds to the rising edge of CL2, and a certain dead time is left between the falling edge of CL2 and the rising edge of CLK3.

7. The active clamp flyback AC-DC converter according to claim 6, wherein: The capacitance ratio of the capacitors C1 to C4 is 8:4:2:

1.

8. The active clamp flyback AC-DC converter according to claim 5, wherein: The conduction threshold generating circuit includes two operational amplifiers AMP1 and AMP2, five resistors R1-R5, three current sources I3-I5, an NMOS transistor MN2, a capacitor C6, and two PMOS transistors MP3 and MP4, wherein the source of MP3 is connected to the source of MP4 and is connected to the power supply voltage VDD, the positive input terminal of AMP1 is connected to Vcst_pre, the negative input terminal of AMP1 is connected to the source of MN2 and one end of R1, the other end of R1 is grounded, the drain of MN2 is connected to the drain of MP3, the gate of MP3 and the gate of MP4, the input terminals of the current sources I3-I5 are all connected to the power supply voltage VDD, the drain of MP4 is connected to Vcst_pre, and the negative input terminal of AMP1 is connected to the source of MN2 and one end of R1. The other end of R1 is grounded. The pole is connected to one end of R2, the output end of current source I3 and the non-inverting input end of AMP2, the other end of R2 is grounded, the output end of current source I4 is connected to the output end of current source I5 and one end of R5 and generates a turn-on voltage threshold Vct, the other end of R5 is connected to the inverting input end of AMP2, the output end of AMP2 and one end of R4, the other end of R4 is connected to one end of C6 and one end of R3 and generates an excitation current threshold voltage signal Vcst, the other end of R3 and the other end of C6 are grounded, the size of current source I3 is I_dither, the size of current source I4 is I_line, and the size of current source I5 is I_tune.

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