A high-speed high-gain operational amplifier structure for a pipelined ADC circuit

Abstract

The application relates to a high-speed high-gain operational amplifier structure for a pipeline ADC circuit and belongs to the technical field of electronics and optoelectronics. The application realizes the high-speed high-gain operational amplifier for the pipeline ADC circuit by using a simple structure.

Description

Technical Field

[0001] This invention belongs to the field of electronic and optoelectronic technology, and relates to a high-speed, high-gain operational amplifier structure for pipeline ADC circuits. Background Technology

[0002] With the continuous development of sensing technology, the speed and accuracy of sensor signal acquisition have been greatly improved. Simultaneously, digital circuits are evolving towards large-scale integrated circuits, and the continuous upgrading of smart portable handheld devices necessitates the continuous improvement of ADC performance, which serves as a bridge between analog and digital signals, moving towards higher speed, higher accuracy, lower voltage, lower power consumption, and single-supply operation. Among various ADC architectures, pipelined ADCs represent a trade-off between speed, accuracy, power consumption, and chip area, making them one of the main structures for high-speed, high-precision ADCs.

[0003] Traditional folded operational amplifier structures struggle to keep up with the demands of high-performance ADCs in terms of speed, accuracy, and power consumption. Summary of the Invention

[0004] (a) Technical problems to be solved

[0005] The technical problem to be solved by this invention is: how to achieve a high-speed, high-gain operational amplifier with a simple structure.

[0006] (II) Technical Solution

[0007] To address the aforementioned technical problems, this invention provides a design method for a high-speed, high-gain operational amplifier structure for pipelined ADC circuits, wherein the high-speed, high-gain operational amplifier structure is designed to include:

[0008] Voltage input path 3 uses a pair of PMOS transistors as the voltage signal input pair.

[0009] The first-stage operational amplifier circuit 1 adopts an operational amplifier with a folded common-source common-gate structure as the first-stage amplifier circuit of the operational amplifier structure.

[0010] The second-stage operational amplifier circuit 2 is composed of an auxiliary operational amplifier stage, which further amplifies the amplification gain of the operational amplifier structure.

[0011] Common-mode feedback circuit 6 is used to implement common-mode feedback and stabilize the output common-mode level;

[0012] When the voltage input path 3 generates a voltage signal, it first passes through the folded common source common gate operational amplifier of the first-stage operational amplifier circuit 1, and then through the gain bootstrap structure of the second-stage operational amplifier circuit 2 to further amplify the operational amplifier.

[0013] A switched capacitor circuit is used as the common-mode feedback circuit 6 for common-mode feedback. The two auxiliary operational amplifier stages of the second-stage operational amplifier circuit 2 use continuous-time common-mode feedback to obtain the common-mode feedback output expression. The actual output common-mode level is subtracted from the ideal common-mode level to obtain the output common-mode level error. This common-mode level error is added to the ideal bias voltage to achieve a stable output common-mode level of the common-mode feedback circuit 6.

[0014] Preferably, the high-speed, high-gain operational amplifier structure further includes: a bias circuit for achieving stable voltage output values. The bias circuit uses two external bias currents to form a wide swing structure, and then generates various voltage values ​​through the series connection of a current mirror and a MOSFET. The output voltage is then obtained by subtracting the common-mode level error.

[0015] Preferably, the bias circuit consists of two bias circuit sub-modules 4 and 5, each bias circuit sub-module generating 4 bias voltages, and the BIAS node in the first bias circuit sub-module 5 is connected to the IBIAS1 node in the second bias circuit sub-module 4.

[0016] Preferably, the gain and bandwidth of the two are allocated according to the Bode plot of the gain-frequency relationship between the auxiliary operational amplifier stage and the main operational amplifier stage with a folded cascode structure.

[0017] Preferably, two filter capacitors are connected between the auxiliary operational amplifier stage and the operational amplifier pair.

[0018] The present invention also provides a high-speed, high-gain operational amplifier structure designed using the method described above.

[0019] The present invention also provides a method of using the aforementioned high-speed, high-gain operational amplifier structure.

[0020] The present invention also provides a pipelined ADC circuit employing the aforementioned high-speed, high-gain operational amplifier structure.

[0021] The present invention also provides an application of the high-speed, high-gain operational amplifier structure in the fields of electronics and optoelectronics.

[0022] The present invention also provides an application of the pipeline ADC circuit in the fields of electronics and optoelectronics.

[0023] (III) Beneficial Effects

[0024] The advantages and significant effects of this invention are:

[0025] 1) Simple structure: It achieves the purpose of a high-speed, high-gain operational amplifier through a simple structure;

[0026] 2) Wide range of applications: The gain bootstrap structure of this invention does not have many requirements on the structure of the operational amplifier, and can be used in various circuits that require feedback amplification;

[0027] 3) The operational amplifier using this structure has the highest unity-gain bandwidth and slew rate at the same process node, and the output swing is also close to the power supply voltage. The operational amplifier designed in this paper can effectively support the performance of a 12-bit 50MSPS pipelined ADC. Attached Figure Description

[0028] Figure 1 The frequency characteristics of the folded cascode operational amplifier with a "gain bootstrapping" structure of the present invention are as follows;

[0029] Figure 2 This invention relates to a folded common-source cascode operational amplifier structure with a "gain bootstrapping" mechanism;

[0030] Figures 3 to 6 This is a structural diagram of each module of the present invention. Detailed Implementation

[0031] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0032] This invention provides a high-speed, high-gain operational amplifier structure applicable to pipelined ADCs. The main parameters determining the performance of a pipelined ADC are the operational amplifier's open-loop gain, unity-gain bandwidth, and slew rate. The gain and bandwidth of the main and auxiliary operational amplifiers are rationally allocated based on the Bode plot of the gain-frequency relationship between the gain-bootstrapping auxiliary operational amplifier and the main operational amplifier. Figure 1 As shown.

[0033] refer to Figures 3 to 6 The present invention discloses a high-speed, high-gain operational amplifier structure for pipelined ADC circuits, which significantly improves the phase margin and gain-bandwidth product of the operational amplifier, and includes the following modules:

[0034] Voltage input path 3 uses a pair of PMOS transistors as the voltage signal input pair.

[0035] The first-stage operational amplifier circuit 1 adopts an operational amplifier with a folded common-source common-gate structure as the first-stage amplifier circuit of the operational amplifier structure.

[0036] The second-stage operational amplifier circuit 2 is composed of an auxiliary operational amplifier stage, which further amplifies the amplification gain of the operational amplifier structure.

[0037] Common-mode feedback circuit 6 realizes common-mode feedback of the circuit and stabilizes the common-mode output level;

[0038] Bias circuitry enables stable voltage output values.

[0039] When voltage input path 3 generates a voltage signal, it first passes through the folded common-source common-gate operational amplifier of the first-stage operational amplifier circuit 1, and then through the gain bootstrap structure of the second-stage operational amplifier circuit 2 for further amplification. Overall, the auxiliary operational amplifier is slower than the main operational amplifier. During the operational amplifier design process, the Bode plots of the auxiliary and main operational amplifiers can be used as a reference. Figure 1 This invention uses a method to rationally allocate the gain and bandwidth of the main operational amplifier (op-amp) and auxiliary operational amplifier (AOP). To achieve a high bandwidth for the overall op-amp, the gain of the main op-amp cannot be too high. Meanwhile, since the auxiliary op-amp does not have very high bandwidth requirements, its current can be appropriately reduced to lower bandwidth and power consumption, while increasing its gain, thereby improving the gain-bandwidth product of the overall op-amp. In this invention, two filter capacitors are connected between the auxiliary op-amps to achieve high-frequency filtering.

[0040] The operational amplifier structure for pipeline ADC of the present invention uses a switched capacitor circuit as a common-mode feedback circuit 6 for common-mode feedback. The two auxiliary operational amplifier stages of the second-stage operational amplifier circuit 2 use continuous-time common-mode feedback to obtain the common-mode feedback output expression. The actual output common-mode level is subtracted from the ideal common-mode level to obtain the output common-mode level error. This common-mode level error is added to the ideal bias voltage to achieve a stable output common-mode level of the common-mode feedback circuit 6.

[0041] The bias circuit of this invention uses two external bias currents to form a wide swing structure. Then, various voltage values ​​are generated by the series connection of a current mirror and a MOSFET. At the same time, the common-mode level error of the ideal bias is subtracted. In order to ensure the stability of each bias voltage, a filter capacitor is added at the output node of the bias voltage.

[0042] In this high-speed, high-gain operational amplifier, the main operational amplifier stage of the first-stage operational amplifier circuit 1, composed of a folded common-source cascode operational amplifier, and the auxiliary operational amplifier stage of the second-stage operational amplifier circuit 2, forms a gain bootstrap structure. This generates a secondary input path 3 further from the origin, improving the system's frequency response and increasing the operational amplifier's bandwidth. The bias circuit consists of two bias circuit sub-modules 4 and 5, each generating four bias voltages. The BIAS node in bias circuit sub-module 5 is connected to the IBIAS1 node in bias circuit sub-module 4. The common-mode feedback circuit 6 uses a switched-capacitor circuit for feedback. This invention improves the circuit's frequency response and phase margin through the gain bootstrap structure, the frequency response relationship between the main and auxiliary operational amplifiers, and the analysis and optimization of the main operational amplifier's poles.

[0043] When the voltage passes through the voltage input path, it is amplified by the first-stage operational amplifier circuit 1 and the second-stage operational amplifier circuit 2. The common-mode feedback circuit 6 (switching common-mode feedback) completes the circuit feedback output of a stable common-mode level, and provides a stable bias voltage to each module through the bias circuit.

[0044] By using gain bootstrapping, the phase margin and gain-bandwidth product of the op-amp are significantly improved, and the op-amp structure used can be effectively applied to pipelined ADC circuits.

[0045] A diode is used to discharge saturation current, but it is not limited to diodes. It can also be used in scenarios where transistors are used as diodes.

[0046] Using PMOS transistors as the input pair of the op-amp results in a secondary pole that is further away from the origin than the secondary pole of a NOMS input pair, which improves the frequency response characteristics of the system and increases the bandwidth of the op-amp.

[0047] The gain and bandwidth of the main and auxiliary op-amps can be reasonably allocated based on the Bode plot of the gain-frequency relationship between the auxiliary and main op-amps. In order to achieve a high bandwidth for the overall op-amp, the gain of the main op-amp cannot be too high. At the same time, since the bandwidth requirement of the auxiliary op-amp is not very high, the current of the auxiliary op-amp can be appropriately reduced to reduce bandwidth and power consumption, but the gain of the auxiliary op-amp can be increased, thereby increasing the gain-bandwidth product of the overall op-amp.

[0048] This invention utilizes a simple structure to realize a high-speed, high-gain operational amplifier for pipelined ADC circuits.

[0049] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A design method for a high-speed, high-gain operational amplifier structure for pipelined ADC circuits, characterized in that, The high-speed, high-gain operational amplifier structure is designed to include: The voltage input path (3) uses a PMOS transistor pair as the voltage signal input pair; The first-stage operational amplifier circuit (1) adopts an operational amplifier with a folded common-source common-gate structure as the first-stage amplifier circuit of the operational amplifier structure. The second-stage operational amplifier circuit (2) is composed of an auxiliary operational amplifier stage, which further amplifies the amplification gain of the operational amplifier structure. The common-mode feedback circuit (6) is used to implement common-mode feedback and stabilize the output common-mode level; When the voltage input path (3) generates a voltage signal, it first passes through the folded common source common gate operational amplifier of the first-stage operational amplifier circuit (1), and then through the gain bootstrap structure of the second-stage operational amplifier circuit (2) to further amplify the operational amplifier. A switched capacitor circuit is used as a common-mode feedback circuit (6) for common-mode feedback. The two auxiliary operational amplifier stages of the second-stage operational amplifier circuit (2) use continuous-time common-mode feedback to obtain the common-mode feedback output expression. The actual output common-mode level is subtracted from the ideal common-mode level to obtain the output common-mode level error. This common-mode level error is added to the ideal bias voltage to achieve a stable output common-mode level of the common-mode feedback circuit (6). The high-speed, high-gain operational amplifier structure also includes: a bias circuit, which is used to achieve stable output voltage values. The bias circuit uses two external bias currents to form a wide swing structure, and then generates various voltage values ​​through the series connection of a current mirror and a MOSFET. The output voltage is then obtained by subtracting the common-mode level error. The bias circuit consists of two bias circuit sub-modules (4, 5). Each bias circuit sub-module generates 4 bias voltages. The BIAS node in the first bias circuit sub-module (5) is connected to the IBIAS1 node in the second bias circuit sub-module (4). The gain and bandwidth of the two are allocated based on the Bode plot of the gain-frequency relationship between the auxiliary operational amplifier stage and the main operational amplifier stage with its folded cascode structure.

2. The method as described in claim 1, characterized in that, Connect two filter capacitors between the auxiliary operational amplifier stage and the operational amplifier pair.

3. A high-speed, high-gain operational amplifier structure designed using the method described in claim 1 or 2.

4. A pipelined ADC circuit employing the high-speed, high-gain operational amplifier structure as described in claim 3.

5. The application of the high-speed, high-gain operational amplifier structure as described in claim 3 in the fields of electronics and optoelectronics.

6. An application of the pipelined ADC circuit as described in claim 4 in the fields of electronics and optoelectronics.

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