Data decoding method and device, electronic equipment and storage medium

Abstract

The present disclosure provides a data decoding method and device, electronic equipment and storage medium, and relates to the technical field of computers. The method comprises the following steps: parsing specified encoded data to obtain decoding information, wherein the decoding information comprises valid data and a valid data length; writing the decoding information into a first cache; writing the valid data in the first cache into a second cache according to the valid data length stored in the first cache; and outputting decoding data corresponding to the specified encoded data through the second cache. In the decoding process, the first cache and the second cache are inserted, thereby improving the real-time data problem caused by the fixed and unpredictable length of the decoding result.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a data decoding method, apparatus, electronic device, and storage medium. Background Technology

[0002] In compression methods for still images and moving videos, the large amount of information and high speed make improving encoding and decoding efficiency imperative. The most common encoding and decoding methods are based on Variable-Length Code (VLC) encoding and decoding, such as Huffman coding. Compared to fixed-length coding, VLC encoding and decoding are more complex. Real-time performance not only requires increasing the clock frequency but also improvements in algorithms and hardware optimization, resulting in significant hardware overhead and development difficulty. Summary of the Invention

[0003] In view of the above, this disclosure provides a data decoding method, apparatus, electronic device, and storage medium.

[0004] In a first aspect, a data decoding method is provided, comprising: parsing specified encoded data to obtain decoding information, the decoding information including valid data and valid data length; writing the decoding information into a first-level cache; writing the valid data in the first-level cache into a second-level cache according to the valid data length stored in the first-level cache; and outputting the decoded data corresponding to the specified encoded data through the second-level cache.

[0005] In some embodiments, parsing specified encoded data to obtain decoded information includes: parsing the encoded data based on at least one decoded block to obtain at least one parsing result, wherein the number of decoded blocks is less than or equal to the smallest encoding unit of the specified encoded data; and concatenating the at least one parsing result to obtain decoded information.

[0006] In some embodiments, writing the decoded information into a first-level cache includes: writing valid data into the first-level cache; adding a header to the valid data written into the first-level cache, the header being used to store the length of the valid data.

[0007] In some embodiments, writing valid data from the first-level cache to the second-level cache according to the valid data length stored in the first-level cache includes: if the first-level cache is not empty, reading the valid data length in the header; and writing the valid data from the first-level cache to the second-level cache according to the valid data length and a preset decoded data bit width.

[0008] In some embodiments, writing valid data from the first-level cache to the second-level cache according to the valid data length and the preset decoded data bit width includes: if the valid data length is greater than or equal to the decoded data bit width, then writing valid data from the first-level cache with a length equal to the decoded data bit width to the second-level cache.

[0009] In some embodiments, writing valid data from the first-level cache to the second-level cache according to the valid data length and the preset decoded data bit width includes: if the valid data length is less than the decoded data bit width, waiting for new decoded information to be written to the first-level cache until the sum of the lengths of all valid data stored in the header is greater than or equal to the decoded data bit width, then writing valid data with a length equal to the decoded data bit width from the first-level cache to the second-level cache.

[0010] In some embodiments, writing valid data from the first-level cache to the second-level cache according to the valid data length and the preset decoded data bit width includes: if the valid data is the last valid data obtained by parsing the specified encoded data, then padding the valid data so that the valid data length is the same as the decoded data bit width; and writing the padded valid data to the second-level cache.

[0011] In a second aspect, a data decoding device is provided, comprising: a parsing module for parsing specified encoded data to obtain decoding information, the decoding information including valid data and valid data length; a first writing module for writing the decoding information into a first-level cache; a second writing module for writing the valid data in the first-level cache into a second-level cache according to the valid data length stored in the first-level cache; and an output module for outputting the decoded data corresponding to the specified encoded data through the second-level cache.

[0012] Thirdly, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the method of the first aspect by executing the executable instructions.

[0013] Fourthly, a computer-readable storage medium is provided having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method of the first aspect described above.

[0014] The data decoding method provided in this disclosure obtains decoding information by parsing specified encoded data. The decoding information includes valid data and the length of the valid data. The decoding information is then written into a primary buffer.

[0015] The data is stored in the first-level cache, and based on the length of the valid data stored in the first-level cache, the valid data in the first-level cache is written to the second-level cache. The decoded data corresponding to the specified encoded data can then be output through the second-level cache. This embodiment of the present disclosure improves the real-time performance of data caused by the variable and unpredictable length of the decoded result by inserting first-level and second-level caches during the decoding process. Attached Figure Description

[0016] Figure 1 A schematic diagram of the system architecture of a data decoding method according to an embodiment of this disclosure is shown.

[0017] Figure 2 A flowchart illustrating a data decoding method according to an embodiment of this disclosure is shown.

[0018] Figure 3 A schematic diagram of the structure of a data decoding device according to an embodiment of the present disclosure is shown.

[0019] Figure 4 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0020] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0021] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. Identical reference numerals in the drawings denote the same or similar parts, and therefore, repeated descriptions of them will be omitted. (See accompanying drawings)

[0022] Some of the block diagrams shown are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0023] 5. To facilitate understanding, the following explanations are provided for several terms used in this disclosure:

[0024] Encoding is the process of converting information from one form or format to another. It involves using pre-defined methods to encode text, numbers, or other objects into digital codes, or to convert information or data into specified electrical pulse signals.

[0025] Variable-length coding refers to a coding method in which the amount of original information contained in coded information of the same length is not fixed or unpredictable.

[0026] Decoding is the process of using specific methods to restore digital data to its original content or to convert electrical pulse signals, optical signals, radio waves, etc., into the information or data they represent. It is the opposite of the encoding process.

[0027] A First In First Out (FIFO) buffer refers to a data buffer that follows the first-in, first-out principle. It has no external read / write address interface, so data can only be written and read sequentially.

[0028] Figure 1 FIG. shows an exemplary system architecture diagram of a data decoding method or a data decoding device that can be applied to embodiments of the present disclosure.

[0029] As Figure 1 shown, the system architecture includes a data distribution module 101, a decoding block 102, a data combination module 103, a write first-level cache module 104, a first-level cache 105, a read first-level cache and write second-level cache module 106, and a second-level cache 107, which are connected in sequence.

[0030] Specifically, the data distribution module 101 is configured to receive the input encoded data and distribute it to each decoding block 102 according to the minimum coding unit. Here, let the minimum coding unit be u, the width of the encoded data be m (m % u == 0), and the parallelism be n (i.e., n is the number of decoding blocks 102). The data distribution module 101 provided in embodiments of the present disclosure can be compatible with both cases of n < u and n == u.

[0031] The decoding block 102 is configured to parse according to the coding rule and output a decoding result.

[0032] The data combination module 103 is configured to merge and combine the decoding results output by each decoding block 102 to obtain decoding information, and fill the decoding information into the data register of the write first-level cache module 104. The decoding information includes valid data and the length of the valid data. The width of the data register of the write first-level cache module 104 is greater than the length of the valid data. The filling position of the decoding information is determined by its position in the original encoded data and the length of the valid data.

[0033] The write first-level cache module 104 is configured to determine whether to write the decoding information into the first-level cache according to the length of the valid data and the data capacity in the first-level cache. When writing the decoding information into the first-level cache, the valid data is directly written into the first-level cache, and the length of the valid data is added to the information header of the valid data. In addition, the information header of the valid data may further include a data end flag, and the data end flag is used to indicate whether the valid data corresponds to the last piece of data in the encoded data.

[0034] The first-level cache 105 is implemented by a FIFO buffer. By setting an almost_full flag, the write first-level cache module 104 can use sequential logic to write the decoding information into the first-level cache, so that the entire system has better timing convergence.

[0035] The read-first-level cache to write-second-level cache module 106 is used to read the first-level cache when the first-level cache 105 is not empty, and write the valid data in the first-level cache to the second-level cache according to the length of the valid data stored in the first-level cache.

[0036] The second-level cache 107 is the same as the first-level cache 105, both implemented by a FIFO cache, which will not be described in detail here.

[0037] The following will describe the exemplary implementation method in detail with reference to the accompanying drawings and embodiments.

[0038] First, this disclosure provides a data decoding method that can be executed by any electronic device with computing capabilities.

[0039] Figure 2 This diagram illustrates a data decoding method according to an embodiment of the present disclosure. Figure 2 As shown, the data decoding method provided in this embodiment includes the following steps.

[0040] S201, parse the specified encoded data to obtain the decoding information, which includes the valid data and the length of the valid data.

[0041] It should be noted that the specified encoded data in the embodiments of this disclosure can be variable-length encoded data. Correspondingly, the valid data is the valid data obtained by parsing the variable-length encoded data. For variable-length encoding, the length of each valid data can be the same or different.

[0042] For example, at least one parsing result can be obtained by parsing the encoded data based on at least one decoding block. Concatenating these at least one parsing result yields the decoded information. The number of decoding blocks is less than or equal to the smallest encoding unit of the specified encoded data, allowing for flexible configuration of the parsing process's parallelism according to hardware overhead requirements, thus avoiding resource waste.

[0043] Specifically, the decoding result includes sub-valid data and sub-valid data length. The valid data and valid data length in the decoded information can be obtained by concatenating at least one sub-valid data in the order of its position in the specified encoded data and accumulating the sub-valid data lengths.

[0044] S202, write the decoded information into the first-level buffer.

[0045] For example, valid data can be directly written to the first-level cache. Simultaneously, a header can be added to the valid data written to the first-level cache; this header stores the length of the valid data. Furthermore, the header of the valid data can also include a data end marker, which indicates whether the valid data corresponds to the last piece of data in the encoded data.

[0046] S203: Write the valid data in the first-level cache to the second-level cache according to the length of the valid data stored in the first-level cache.

[0047] In some embodiments, if the first-level cache is not empty, the effective data length in the header is read. Then, based on the effective data length and a preset decoded data bit width, the effective data in the first-level cache can be written to the second-level cache. The decoded data bit width is the data length that the method provided in this embodiment can output in each clock cycle.

[0048] Specifically, S203 can be divided into the following categories:

[0049] If the length of the valid data is greater than or equal to the width of the decoded data, then valid data of equal length to the width of the decoded data in the first-level cache is written to the second-level cache. If the length of the valid data is greater than the width of the decoded data, then after writing the valid data to the second-level cache, there will still be valid data remaining in the first-level cache. In this case, when determining the relationship between the length of the valid data and the width of the decoded data in the next comparison, the length of the valid data will be the total length of all valid data in the first-level cache, which is the sum of the length of the remaining valid data and the new valid data length.

[0050] If the length of the valid data is less than the width of the decoded data, wait for new decoded information to be written into the first-level cache. When the sum of the lengths of all valid data stored in the header is greater than or equal to the width of the decoded data, write the valid data in the first-level cache with a length equal to the width of the decoded data into the second-level cache.

[0051] If the valid data is the last valid data obtained by parsing the specified encoded data, then the valid data is padded to make its length the same as the width of the decoded data, and then the padded valid data is written to the second-level buffer. The padding method involves adding zeros to the valid data. Furthermore, the data end marker can be used to determine if the valid data is the last valid data obtained by parsing the specified encoded data.

[0052] S204 outputs the decoded data corresponding to the specified encoded data through the second-level buffer.

[0053] It should be noted that the decoded data can be valid data. Specifically, the secondary buffer can sequentially output valid data with a length equal to the preset decoded data bit width.

[0054] The data decoding method provided in this disclosure parses specified encoded data to obtain decoding information, which includes valid data and valid data length. The decoding information is then written to a first-level cache, and based on the valid data length stored in the first-level cache, the valid data in the first-level cache is written to a second-level cache. Finally, the decoded data corresponding to the specified encoded data can be output through the second-level cache. This disclosure improves the real-time performance of data caused by the variable and unpredictable length of the decoding result by inserting first-level and second-level caches during the decoding process, thereby enhancing decoding efficiency.

[0055] Based on the same inventive concept, this disclosure also provides a data decoding device, as described in the following embodiments. Since the principle by which this device solves the problem is similar to that of the method embodiments described above, the implementation of this device embodiment can refer to the implementation of the method embodiments described above, and repeated details will not be repeated.

[0056] Figure 3 This diagram illustrates the structure of a data decoding apparatus according to an embodiment of the present disclosure, such as... Figure 3 As shown, the data decoding device 300 includes: a parsing module 301, a first writing module 302, a second writing module 303, and an output module 304.

[0057] Specifically, the parsing module 301 is used to parse the specified encoded data to obtain decoded information, which includes valid data and the length of valid data. The first writing module 302 is used to write the decoded information into a first-level cache. The second writing module 303 is used to write the valid data in the first-level cache into a second-level cache according to the length of valid data stored in the first-level cache. The output module 304 is used to output the decoded data corresponding to the specified encoded data through the second-level cache.

[0058] In some embodiments, the parsing module 301 is further configured to parse the encoded data based on at least one decoding block to obtain at least one parsing result, wherein the number of decoding blocks is less than or equal to the minimum encoding unit of the specified encoded data; and to concatenate the at least one parsing result to obtain decoded information.

[0059] In some embodiments, the first writing module 302 is further configured to write valid data into the first-level cache; and to add a header to the valid data written into the first-level cache, wherein the header is used to store the length of the valid data.

[0060] In some embodiments, the second writing module 303 is further configured to: if the first-level cache is not empty, read the effective data length in the information header; and write the effective data in the first-level cache into the second-level cache according to the effective data length and the preset decoded data bit width.

[0061] In some embodiments, the second writing module 303 is further configured to write valid data with a length equal to the decoded data bit width from the first-level cache into the second-level cache if the valid data length is greater than or equal to the decoded data bit width.

[0062] In some embodiments, the second writing module 303 is further configured to, if the length of the valid data is less than the width of the decoded data, wait for new decoded information to be written into the first-level cache until the sum of the lengths of all valid data stored in the header is greater than or equal to the width of the decoded data, and then write the valid data in the first-level cache with a length equal to the width of the decoded data into the second-level cache.

[0063] In some embodiments, the second writing module 303 is further configured to, if the valid data is the last valid data obtained by parsing the specified encoded data, fill the valid data so that the length of the valid data is the same as the bit width of the decoded data; and write the filled valid data into the second-level cache.

[0064] It should be noted that the data decoding device provided in the above embodiments is only illustrated by the division of the above functional modules when used for data decoding. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the data decoding device and the data decoding method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0065] Those skilled in the art will understand that various aspects of this disclosure can be implemented as a system, method, or program product. Therefore, various aspects of this disclosure can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software aspects, collectively referred to herein as a "circuit," "module," or "system."

[0066] The following reference Figure 4 To describe an electronic device 400 according to such an embodiment of the present disclosure. Figure 4 The electronic device 400 shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0067] like Figure 4 As shown, the electronic device 400 is manifested in the form of a general-purpose computing device. The components of the electronic device 400 may include, but are not limited to: at least one processing unit 410, at least one storage unit 420, and a bus 430 connecting different system components (including storage unit 420 and processing unit 410).

[0068] The storage unit stores program code, which can be executed by the processing unit 410, causing the processing unit 410 to perform the steps described in the "Exemplary Methods" section above according to various exemplary embodiments of this disclosure.

[0069] In some embodiments, the processing unit 410 may perform the following steps of the above method embodiment: parsing the specified encoded data to obtain decoding information, the decoding information including valid data and valid data length; writing the decoding information into a first-level cache; writing the valid data in the first-level cache into a second-level cache according to the valid data length stored in the first-level cache; and outputting the decoded data corresponding to the specified encoded data through the second-level cache.

[0070] Storage unit 420 may include a readable medium in the form of a volatile storage unit, such as random access memory (RAM) 4201 and / or cache memory 4202, and may further include a read-only memory (ROM) 4203.

[0071] Storage unit 420 may also include a program / utility 4204 having a set (at least one) program module 4205, such program module 4205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0072] Bus 430 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0073] Electronic device 400 can also communicate with one or more external devices 440 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with the electronic device 400, and / or with any device that enables the electronic device 400 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 450. Furthermore, electronic device 400 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 460. Figure 4 As shown, network adapter 460 communicates with other modules of electronic device 400 via bus 430. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with electronic device 400, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0074] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0075] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, which may be a readable signal medium or a readable storage medium. A program product capable of implementing the methods described above is stored thereon. In some possible implementations, various aspects of this disclosure may also be implemented as a program product including program code, which, when run on a terminal device, causes the terminal device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure.

[0076] More specific examples of computer-readable storage media in this disclosure may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0077] In this disclosure, a computer-readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of transmitting, propagating, or transmitting a program for use by or in connection with an instruction execution system, apparatus, or device.

[0078] Optionally, the program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0079] In practical implementation, program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0080] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0081] Furthermore, although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0082] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, mobile terminal, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0083] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A data decoding method, characterized in that, include: Parse the specified encoded data to obtain decoding information, wherein the decoding information includes valid data and the length of valid data, and the specified encoded data includes variable-length encoded data; Write the decoded information into a first-level cache; add a header to the valid data written into the first-level cache, the header being used to store the length of the valid data; Based on the length of the valid data stored in the first-level cache, the valid data in the first-level cache is written into the second-level cache; The secondary cache outputs the decoded data corresponding to the specified encoded data, and the secondary cache sequentially outputs valid data with a length equal to the preset decoded data bit width; The step of writing the valid data in the first-level cache to the second-level cache according to the length of the valid data stored in the first-level cache includes: If the first-level cache is not empty, then read the length of the valid data in the header. Based on the effective data length and the preset decoded data bit width, the effective data in the first-level cache is written into the second-level cache.

2. The method according to claim 1, characterized in that, The process of parsing the specified encoded data to obtain decoded information includes: The encoded data is parsed based on at least one decoding block to obtain at least one parsing result, wherein the number of decoding blocks is less than or equal to the smallest encoding unit of the specified encoded data; The at least one parsing result is concatenated to obtain the decoded information.

3. The method according to claim 1, characterized in that, The step of writing the valid data from the first-level cache to the second-level cache according to the valid data length and the preset decoded data bit width includes: If the length of the valid data is greater than or equal to the width of the decoded data, then the valid data in the first-level cache with a length equal to the width of the decoded data is written into the second-level cache.

4. The method according to claim 1, characterized in that, The step of writing the valid data from the first-level cache to the second-level cache according to the valid data length and the preset decoded data bit width includes: If the length of the valid data is less than the width of the decoded data, then wait for new decoded information to be written into the first-level cache until the sum of the lengths of all valid data stored in the header is greater than or equal to the width of the decoded data, then write the valid data in the first-level cache with a length equal to the width of the decoded data into the second-level cache.

5. The method according to claim 1, characterized in that, The step of writing the valid data from the first-level cache to the second-level cache according to the valid data length and the preset decoded data bit width includes: If the valid data is the last valid data obtained by parsing the specified encoded data, then the valid data is padded so that the length of the valid data is the same as the bit width of the decoded data; Write the padded valid data to the second-level cache.

6. A data decoding device, characterized in that, include: The parsing module is used to parse specified encoded data to obtain decoded information, wherein the decoded information includes valid data and the length of valid data, and the specified encoded data includes variable-length encoded data. The first writing module is used to write the decoded information into a first-level cache; and to add a header to the valid data written into the first-level cache, wherein the header is used to store the length of the valid data; The second write module is used to write the valid data in the first-level cache into the second-level cache according to the length of the valid data stored in the first-level cache; The output module is used to output decoded data corresponding to the specified encoded data through the secondary buffer, wherein the secondary buffer sequentially outputs valid data with a length equal to the preset decoded data bit width; The step of writing the valid data in the first-level cache to the second-level cache according to the length of the valid data stored in the first-level cache includes: If the first-level cache is not empty, then read the length of the valid data in the header. Based on the effective data length and the preset decoded data bit width, the effective data in the first-level cache is written into the second-level cache.

7. An electronic device, characterized in that, include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the method of any one of claims 1 to 5 by executing the executable instructions.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method described in any one of claims 1 to 5.

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