Fft hardware accelerator with random window sampling function

Abstract

The application provides an FFT hardware accelerator with a random window sampling function, which comprises a dual-port SRAM module and an FFT hardware acceleration module. In the application, the FFT hardware accelerator is designed by combining the dual-port SRAM module and the FFT hardware acceleration module. Before the FFT conversion, the data signal is written by random grabbing for multiple times through the enable control of the dual-port SRAM module by a random clock, so that a random sampling signal is obtained. The data signal is grabbed in a sliding window mode, and the grabbing time of the data signal in the window is random. After the multiple grabbing statistics, the sampling signal is transmitted to the FFT hardware acceleration module in the rear stage to perform the fast Fourier transform from the time domain to the frequency domain. The converted signal can effectively reflect the time-varying statistical characteristics of the data signal, so that the time information of the data signal can be more truly obtained.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and in particular to an FFT hardware accelerator with random window sampling function. Background Technology

[0002] The Fourier transform can obtain the spectrum of a signal and has wide applications in signal processing and analysis. The FFT (Fast Fourier Transform) principle is derived from the Fourier transform. In signal processing systems, FFT hardware accelerators can transform signals from the time domain to the frequency domain for processing. However, the Fourier transform relies on the assumption that the signal is stationary, meaning its statistical characteristics do not change over time. But real-world sound signals are generally not stationary; many signals appear and disappear over long periods. If all these signals are subjected to a Fourier transform, the changes in sound over time cannot be reflected. Therefore, it is necessary to incorporate time information into the FFT transformation, especially when the signal is non-stationary, as its statistical characteristics constantly change over time, making it impossible to fully capture the signal's characteristic information.

[0003] The Short-Time Fourier Transform (SFT) was developed to address this issue. However, the SFT extracts a segment of the signal from a long signal, essentially applying a windowing operation to the original signal. In the SFT process, the window length determines the time and frequency resolution of the spectrum. A longer window extracts a longer signal, resulting in higher frequency resolution but lower time resolution after the Fourier transform. Conversely, a shorter window extracts a shorter signal, resulting in lower frequency resolution but better time resolution. In other words, time and frequency resolution are mutually exclusive in the SFT. Therefore, signal extraction requires a windowing function, which introduces new problems. At the edges of the window, the signal is multiplied by a very small number. This means that the data is not fully utilized; the signal between two adjacent windows is not fully reflected in the spectrum.

[0004] Therefore, there is an urgent need for an FFT hardware acceleration technology that can reduce the impact of window truncation and obtain more accurate time information of the signal, so as to solve the technical problem that the signal cannot be effectively extracted within the window spacing. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an FFT hardware accelerator that uses a sliding window method to capture signals. The signal capture time within each window is random. After multiple captures and statistics, the time-varying statistical characteristics of the signal can be effectively reflected, thereby enabling more realistic acquisition of the signal's time information.

[0006] To achieve the above and other related objectives, the technical solution provided by this invention is as follows.

[0007] An FFT hardware accelerator with random window sampling capability includes:

[0008] The dual-port SRAM module receives data signals and, under the enable control of a random clock, performs multiple random fetches and writes on the data signals to obtain multiple sampled signals.

[0009] The FFT hardware acceleration module is connected to the dual-port SRAM module, periodically reads the sampled signal, and performs a fast Fourier transform from the time domain to the frequency domain on the sampled signal.

[0010] Optionally, the dual-port SRAM module includes:

[0011] An SRAM array, comprising multiple SRAM cells arranged in an array;

[0012] A write address decoder is connected to the SRAM array;

[0013] The peripheral write circuit is connected to the write address decoder. Under the enable control of the random clock, the write address decoder randomly captures the data signal and writes it into the SRAM array.

[0014] The address decoder is connected to the SRAM array;

[0015] The peripheral read circuit is connected to the read address decoder. Under the enable control of a fixed clock, the read address decoder reads the data signal from the SRAM array.

[0016] Optionally, the dual-port SRAM module further includes a clock unit that generates the random clock and the fixed clock.

[0017] Optionally, the window parameter size of the random fetch write window of the dual-port SRAM module is positively correlated with the latency of the FFT hardware acceleration module. The larger the window parameter of the random fetch write window, the greater the latency of the FFT hardware acceleration module.

[0018] Optionally, the window parameter of the random fetch write window is greater than the latency of the FFT hardware acceleration module.

[0019] Optionally, the FFT hardware acceleration module includes multiple cascaded FFT operation stages, with multipliers connected in series between adjacent FFT operation stages. Each FFT operation stage includes a butterfly operation unit and a data delay register. The first input terminal of the butterfly operation unit serves as the input terminal of the FFT operation stage, and the first output terminal of the butterfly operation unit serves as the output terminal of the FFT operation stage. The second output terminal of the butterfly operation unit is connected to the input terminal of the data delay register, and the second input terminal of the butterfly operation unit is connected to the output terminal of the data delay register.

[0020] Optionally, along the direction from the first-level FFT operation stage to the last-level FFT operation stage, the delays of the data delay registers in each of the FFT operation stages are distributed in a geometric sequence with a common ratio of 1 / 2.

[0021] Optionally, the FFT hardware acceleration module includes multiple cascaded FFT operation stages. Each FFT operation stage includes a butterfly operation unit, a first data delay register, a second data delay register, a multiplier, a first data selector, and a second data selector. The first input terminal of the butterfly operation unit serves as the first input terminal of the FFT operation stage, and the second input terminal of the butterfly operation unit serves as the second input terminal of the FFT operation stage. The first output terminal of the butterfly operation unit is connected to the first input terminal of the first data selector and the first input terminal of the second data selector after passing through the multiplier and the first data delay register in series. The second output terminal of the butterfly operation unit is connected to the second input terminal of the first data selector and the second input terminal of the second data selector. The output terminal of the first data selector serves as the first output terminal of the butterfly operation unit and is connected to the first input terminal of the next-level butterfly operation unit. The output terminal of the second data selector is connected to the input terminal of the second data delay register and serves as the second output terminal of the butterfly operation unit. The output terminal of the second data delay register is connected to the second input terminal of the next-level butterfly operation unit.

[0022] Optionally, the delay of the first data delay register is equal to the delay of the second data delay register.

[0023] Optionally, along the direction from the first FFT operation stage to the last FFT operation stage, the delays of the first data delay registers in each of the FFT operation stages are distributed in a geometric sequence with a common ratio of 1 / 2.

[0024] As described above, the FFT hardware accelerator with random window sampling function provided by the present invention has at least the following beneficial effects:

[0025] An FFT hardware accelerator is designed by combining a dual-port SRAM module and an FFT hardware acceleration module. Before the FFT transformation, the dual-port SRAM module is enabled by a random clock to randomly capture and write data signals multiple times, resulting in random sampled signals. This is achieved by designing a sliding window method to capture data signals. Within this window, the capture time of the data signal is random. After multiple captures and statistics, the sampled signals are then passed to the subsequent FFT hardware acceleration module for a fast Fourier transform from the time domain to the frequency domain. The transformed signal can effectively reflect the time-varying statistical characteristics of the data signal, thereby enabling a more realistic acquisition of the time information of the data signal. Attached Figure Description

[0026] Figure 1 The diagram shown is a structural block diagram of the FFT hardware accelerator with random window sampling function in this invention.

[0027] Figure 2 Displayed as Figure 1 Block diagram of a dual-port SRAM module.

[0028] Figure 3 The flowchart shows the processing flow of a traditional FFT hardware adder that uses a fixed window to capture signals.

[0029] Figure 4 The diagram shows the processing flow of the FFT hardware accelerator with random window sampling function in this invention.

[0030] Figure 5 The diagram shown is a structural block diagram of the FFT hardware acceleration module in an optional embodiment of the present invention.

[0031] Figure 6 The diagram shown is a structural block diagram of the FFT hardware acceleration module in another optional embodiment of the present invention. Detailed Implementation

[0032] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] Please see Figures 1 to 6It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0034] As mentioned in the background section, the inventors discovered that in signal analysis systems, it is often necessary to convert signals to the frequency domain for processing. Therefore, the system often needs to include a hardware accelerator for FFT processing. However, FFT conversion often only contains frequency domain information and cannot contain time domain change information. Therefore, a hardware structure for short-time FFT transformation is used to complete the signal information conversion and analysis in the signal system. However, since short-time Fourier transform requires windowing, windowing brings new problems. At the edge of the window, the signal will be multiplied by a very small number, which means that the data is not fully utilized. The signal between two adjacent windows is not fully reflected in the spectrum, making it impossible to effectively extract the signal within the window gap.

[0035] Based on this, the present invention provides an FFT hardware acceleration scheme with random window sampling function: a dual-port SRAM module is added before the FFT hardware acceleration module, and the random writing control of the dual-port SRAM module is used to complete the random capture and writing of the signal. The signal capture is completed by a sliding window method. The signal capture time is random each time within the window. After multiple captures and statistics, the sampled signals from multiple random captures are then passed to the subsequent FFT hardware acceleration module for conversion through the dual-port SRAM module. The transformed signal covers information of all time periods, which can avoid missing data signals and effectively reflect the time-varying statistical characteristics of the signal.

[0036] like Figure 1 As shown, the present invention provides an FFT hardware accelerator with random window sampling function, which includes:

[0037] The dual-port SRAM module receives data signals and, under the enable control of a random clock, performs multiple random fetches and writes of the data signals to obtain multiple sampled signals.

[0038] The FFT hardware acceleration module connects to a dual-port SRAM module, periodically reads the sampled signal, and performs a fast Fourier transform from the time domain to the frequency domain on the sampled signal.

[0039] In detail, in an optional embodiment of the invention, such as Figure 2 As shown, the dual-port SRAM module includes:

[0040] An SRAM array, comprising multiple SRAM cells arranged in an array;

[0041] Write address decoder, connected to SRAM array;

[0042] The external write circuit is connected to the write address decoder. Under the enable control of the random clock W_en, the write address decoder randomly captures the data signal and writes it into the SRAM array.

[0043] Read address decoder, connected to SRAM array;

[0044] The external read circuit is connected to the read address decoder. Under the enable control of the fixed clock R_en, the data signal is read from the SRAM array through the read address decoder.

[0045] In detail, such as Figure 2 As shown, the dual-port SRAM module also includes a clock unit, which generates a random clock W_en and a fixed clock R_en; the random clock W_en is a clock signal with random time and frequency generated by combining random numbers, and the fixed clock R_en is a clock signal with a fixed frequency.

[0046] In detail, such as Figure 3 As shown, the traditional method uses a fixed window to capture and transform the signal. The input data signal is windowed and truncated, with the signal captured at a fixed window position. Then, after the window ends, the data is read back at a predetermined position for FFT hardware transformation. This results in the ineffective extraction of signals between two adjacent windows, failing to fully reflect them in the spectrum and causing information loss.

[0047] This invention utilizes a dual-port SRAM module to capture signals and write data signals into the dual-port SRAM module using a random window, thus completing the random window capture operation for signals. Figure 4As shown. For example, within N + 1 time ranges with a time range of 0 to N, the signal window length is M, where M < N. Then the positions where the window can be grabbed can be [0, M - 1], [1, M], [2, M + 1], [3, M + 2], …… [N - M + 1, N], a total of N - M + 2 cases of grabbing windows. Therefore, as long as the write signals of the dual-port SRAM module generated can be equally distributed within the range of N - M + 2 cases, its implementation is a random window grabbing function. To more accurately display the spectral characteristics between the two window functions, the moments of the two data grabbing windows are randomized by randomizing the window grabbing data, so as to avoid ignoring some spectral information when analyzing the signal. At the same time, since the moments of generating the grabbing windows are randomized, as the number of sampling signal periods of the grabbing increases, the statistical characteristics of the data signal changes within the sliding window will be reflected in the final FFT conversion result.

[0048] Specifically, as Figure 2 shown, since the function of randomly window-grabbing data is implemented through a dual-port SRAM module, this dual-port SRAM has a separate read-write control logic circuit, and its read and write addresses each have separate logics. The data signal completes the write operation to the dual-port SRAM module when the write signal of the dual-port SRAM module is enabled, and when the read signal is enabled, it completes the readout of the data stored inside the dual-port SRAM module. Since its read and write addresses are separate, the read and write operation address spaces of the dual-port SRAM module do not conflict. Within N + 1 time ranges with a time range of 0 to N, the signal window length is M, where M < N. Then the positions where the window can be grabbed can be [0, M - 1], [1, M], [2, M + 1], [3, M + 2], …… [N - M + 1, N], a total of N - M + 2 cases of grabbing window enable signals are used to complete the write operation to the dual-port SRAM module.

[0049] Among them, the function of randomly window-grabbing data is implemented by operating the write signal of the dual-port SRAM module. The write enable signal of the dual-port SRAM module is enabled within a window time period, and its enabling is controlled by a random number (i.e., a random clock W_en) for its enabling moment, which ensures that data signal grabbing is performed equally probably at a certain moment within a time window to ensure that the time-domain information of the data signal can be obtained as much as possible. Then all sampling signals perform a readout operation at the same moment and are sent to the subsequent FFT hardware acceleration module.

[0050] In detail, the FFT hardware acceleration module can include various architectures such as the delay feedback DCFFT architecture and the serial conversion SC FFT architecture. The main design method of the delay feedback DCFFT architecture is to feed the output data back to the data buffer, hence the name delay feedback architecture, which has a relatively short latency. The design purpose of the serial conversion SC FFT architecture is to save computing resources but will increase its latency.

[0051] In detail, the specific structural design of the subsequent FFT hardware acceleration module is related to the window parameters of the random fetching from the preceding dual-port SRAM module. The size of the window parameter of the random fetching and writing window of the dual-port SRAM module is positively correlated with the latency of the FFT hardware acceleration module. The larger the window parameter of the random fetching and writing window, the greater the latency of the FFT hardware acceleration module. For example, if a structure with long latency is selected, the FFT hardware implementation overhead is small, and a long window parameter is selected when choosing the window of the front-end random window function. If a structure with low latency is selected, then a small window parameter is selected when choosing the window of the front-end random window function.

[0052] Since the random window capture at the front end needs to be performed within a certain window range, it requires a window time. In order to ensure that the data captured within this window time will not overflow or conflict in the dual-port SRAM module, the captured data needs to be read out and the FFT transformation needs to be completed within a window range. Therefore, the hardware acceleration transformation of FFT needs to be completed within the window time.

[0053] If a 128-point FFT conversion is required, the conversion latency of the FFT hardware acceleration module will vary depending on the structure used. The latency is 64 for a radix-2 MDF structure, 32 for a radix-4 MDF structure, and 16 for a radix-8 MDF structure. If an SDF structure is used, the latency is 127 regardless of whether it is radix-2, radix-4, or radix-8. Therefore, if the size of the designed random window is smaller than the latency of the FFT hardware acceleration module, the data in the dual-port SRAM module will overflow. So, it is generally necessary to choose a window parameter for the random capture and write window that is larger than the latency of the designed FFT hardware acceleration module.

[0054] In addition, when designing an FFT hardware acceleration module, a trade-off is made between overall conversion latency and hardware overhead.

[0055] In an optional embodiment of the present invention, such as Figure 5As shown, the FFT hardware acceleration module adopts a delay feedback DCFFT architecture, which includes multiple cascaded FFT operation stages, with multipliers connected in series between adjacent FFT operation stages. Each FFT operation stage includes a butterfly operation unit and a data delay register. The first input of the butterfly operation unit serves as the input of the FFT operation stage, and the first output of the butterfly operation unit serves as the output of the FFT operation stage. The second output of the butterfly operation unit is connected to the input of the data delay register, and the second input of the butterfly operation unit is connected to the output of the data delay register.

[0056] In detail, such as Figure 5 As shown, along the direction from the first FFT operation stage to the last FFT operation stage, the delay of the data delay register in each FFT operation stage is distributed in a geometric sequence with a common ratio of 1 / 2.

[0057] In another optional embodiment of the invention, such as Figure 6 As shown, the FFT hardware acceleration module adopts a serial conversion SC-type FFT architecture, which includes multiple cascaded FFT operation stages. Each FFT operation stage includes a butterfly operation unit, a first data delay register, a second data delay register, a multiplier, a first data selector, and a second data selector. The first input terminal of the butterfly operation unit serves as the first input terminal of the FFT operation stage, and the second input terminal of the butterfly operation unit serves as the second input terminal of the FFT operation stage. The first output terminal of the butterfly operation unit is connected to the first input terminal of the first data selector and the first input terminal of the second data selector after being connected in series with the multiplier and the first data delay register. The second output terminal of the butterfly operation unit is connected to the second input terminal of the first data selector and the second input terminal of the second data selector. The output terminal of the first data selector serves as the first output terminal of the butterfly operation unit and is connected to the first input terminal of the next-level butterfly operation unit. The output terminal of the second data selector is connected to the input terminal of the second data delay register and serves as the second output terminal of the butterfly operation unit. The output terminal of the second data delay register is connected to the second input terminal of the next-level butterfly operation unit.

[0058] In detail, such as Figure 6 As shown, the delay of the first data delay register is equal to the delay of the second data delay register; along the direction from the first FFT operation stage to the last FFT operation stage, the delay of the first data delay register in each FFT operation stage is distributed in a geometric sequence with a common ratio of 1 / 2.

[0059] In summary, the FFT hardware accelerator with random window sampling function provided by this invention combines a dual-port SRAM module and an FFT hardware acceleration module. Before the FFT transformation, the dual-port SRAM module is enabled by a random clock to randomly capture and write the data signal multiple times, resulting in a random sampled signal. This is achieved by designing a sliding window method to capture the data signal. Within this window, the capture time of the data signal is random. After multiple captures and statistics, the sampled signal is then transmitted to the subsequent FFT hardware acceleration module for a fast Fourier transform from the time domain to the frequency domain. The transformed signal can effectively reflect the time-varying statistical characteristics of the data signal, thereby enabling a more realistic acquisition of the time information of the data signal.

[0060] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An FFT hardware accelerator with random window sampling function, characterized in that, include: The dual-port SRAM module receives data signals and, under the enable control of a random clock, performs multiple random fetches and writes on the data signals to obtain multiple sampled signals. The FFT hardware acceleration module is connected to the dual-port SRAM module, periodically reads the sampled signal, and performs a fast Fourier transform from the time domain to the frequency domain on the sampled signal. The dual-port SRAM module includes: An SRAM array, comprising multiple SRAM cells arranged in an array; A write address decoder is connected to the SRAM array; The peripheral write circuit is connected to the write address decoder. Under the enable control of the random clock, the write address decoder randomly captures the data signal and writes it into the SRAM array. The address decoder is connected to the SRAM array; An external read circuit, connected to the read address decoder, reads the data signal from the SRAM array through the read address decoder under the enable control of a fixed clock. The FFT hardware acceleration module includes multiple cascaded FFT operation stages. Each FFT operation stage includes a butterfly operation unit, a first data delay register, a second data delay register, a multiplier, a first data selector, and a second data selector. The first input of the butterfly operation unit serves as the first input of the FFT operation stage, and the second input of the butterfly operation unit serves as the second input of the FFT operation stage. The first output of the butterfly operation unit is connected to the first input of the first data selector and the first input of the second data selector via the multiplier and the first data delay register connected in series. The second output of the butterfly operation unit is connected to the second input of the first data selector and the second input of the second data selector. The output of the first data selector serves as the first output of the butterfly operation unit and is connected to the first input of the next-level butterfly operation unit. The output of the second data selector is connected to the input of the second data delay register and serves as the second output of the butterfly operation unit. The output of the second data delay register is connected to the second input of the next-level butterfly operation unit.

2. The FFT hardware accelerator with random window sampling function according to claim 1, characterized in that, The dual-port SRAM module also includes a clock unit that generates the random clock and the fixed clock.

3. The FFT hardware accelerator with random window sampling function according to claim 1, characterized in that, The window parameter size of the random fetch write window of the dual-port SRAM module is positively correlated with the latency of the FFT hardware acceleration module. The larger the window parameter of the random fetch write window, the greater the latency of the FFT hardware acceleration module.

4. The FFT hardware accelerator with random window sampling function according to claim 3, characterized in that, The window parameters of the random fetch write window are greater than the latency of the FFT hardware acceleration module.

5. The FFT hardware accelerator with random window sampling function according to claim 1, characterized in that, The FFT hardware acceleration module includes multiple cascaded FFT operation stages, with multipliers connected in series between adjacent FFT operation stages. Each FFT operation stage includes a butterfly operation unit and a data delay register. The first input terminal of the butterfly operation unit serves as the input terminal of the FFT operation stage, and the first output terminal of the butterfly operation unit serves as the output terminal of the FFT operation stage. The second output terminal of the butterfly operation unit is connected to the input terminal of the data delay register, and the second input terminal of the butterfly operation unit is connected to the output terminal of the data delay register.

6. The FFT hardware accelerator with random window sampling function according to claim 5, characterized in that, Along the direction from the first FFT operation stage to the last FFT operation stage, the delays of the data delay registers in each FFT operation stage are distributed in a geometric sequence with a common ratio of 1 / 2.

7. The FFT hardware accelerator with random window sampling function according to claim 1, characterized in that, The delay of the first data delay register is equal to the delay of the second data delay register.

8. The FFT hardware accelerator with random window sampling function according to claim 7, characterized in that, Along the direction from the first FFT operation stage to the last FFT operation stage, the delays of the first data delay registers in each FFT operation stage are distributed in a geometric sequence with a common ratio of 1 / 2.

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