A current subtraction circuit and method applied to an RRAM computing-in-memory circuit

Abstract

The present invention discloses a current subtraction circuit and method applied to an RRAM computing-in-memory circuit, aiming to solve the problems of complex quantization logic and long quantization period existing in the prior art when using a current comparator to perform quantization operations on the computing-in-memory multiply-accumulate result. The circuit includes a first clamping circuit, a second clamping circuit, a PMOS current mirror circuit, and an NMOS current mirror circuit. The PMOS current mirror circuit includes 8 PMOS transistors, and the NMOS current mirror circuit includes 4 NMOS transistors. The sign and magnitude of the multiply-accumulate operation result of the RRAM array are judged by detecting the magnitudes of the currents flowing through two current branches in the subtraction circuit. The present invention realizes subtraction operations through a circuit with a current mirror structure, and the operation logic is relatively simple, reducing the complexity of the circuit and the design difficulty.

Description

Technical Field

[0001] The present invention relates to a current subtraction circuit and method applied to an RRAM computing-in-memory circuit, belonging to the technical field of RRAM computing-in-memory circuits. Background Art

[0002] Traditional current-mode RRAM in-memory computing circuits mainly use current comparators to quantize and read out the multiply-accumulate results. However, using current comparators in multi-bit in-memory computing circuits will lead to overly complex quantization logic, and multi-cycle quantization operations will also make the quantization period longer, resulting in data throughput and energy efficiency losses in the computing-in-memory system. Summary of the Invention

[0003] In order to solve the problems of complex quantization logic and long quantization period in the existing technology when using current comparators to perform quantization operations on the multiply-accumulate results of computing-in-memory, the present invention proposes a current subtraction circuit and method applied to an RRAM computing-in-memory circuit, which realizes subtraction operations through a circuit with a current mirror structure, and the operation logic is relatively simple, reducing the complexity and design difficulty of the circuit.

[0004] To solve the above technical problems, the present invention adopts the following technical means:

[0005] In a first aspect, the present invention proposes a current subtraction circuit applied to an RRAM computing-in-memory circuit, including a first clamping circuit, a second clamping circuit, a PMOS current mirror circuit, and an NMOS current mirror circuit;

[0006] The PMOS current mirror circuit includes 8 PMOS transistors, and the NMOS current mirror circuit includes 4 NMOS transistors;

[0007] The first clamping circuit is connected to the drain and gate terminals of the first PMOS transistor and the gate terminal of the second PMOS transistor; the drain terminal of the second PMOS transistor is connected to the gate and drain terminals of the third PMOS transistor, the gate terminal of the fourth PMOS transistor, the drain terminal of the first NMOS transistor, the drain and gate terminals of the second NMOS transistor, and the gate terminal of the third NMOS transistor; the drain terminal of the third NMOS transistor is connected to the gate and drain terminals of the fifth PMOS transistor and the gate terminal of the sixth PMOS transistor; the gate terminal of the first NMOS transistor is connected to the gate and drain terminals of the fourth NMOS transistor and the drain terminal of the seventh PMOS transistor; the gate terminal of the seventh PMOS transistor is connected to the gate and drain terminals of the eighth PMOS transistor and the second clamping circuit; the source terminals of the first to eighth PMOS transistors are all connected to the power supply voltage; the source terminals of the first to fourth NMOS transistors are all connected to the ground potential.

[0008] In combination with the first aspect, further, the first clamping circuit includes a first RRAM memory array, a fifth NMOS transistor, and a first error amplifier. The positive input terminal of the first error amplifier is connected to the bit line clamping voltage V CLP , the negative input terminal of the first error amplifier is respectively connected to the source terminal of the fifth NMOS transistor and the bit line of the first RRAM memory array, the output terminal of the first error amplifier is connected to the gate terminal of the fifth NMOS transistor, and the drain terminal of the fifth NMOS transistor is respectively connected to the drain terminal and the gate terminal of the first PMOS transistor, and the gate terminal of the second PMOS transistor.

[0009] In combination with the first aspect, further, the second clamping circuit includes a second RRAM memory array, a sixth NMOS transistor, and a second error amplifier. The positive input terminal of the second error amplifier is connected to the bit line clamping voltage V CLP , the negative input terminal of the second error amplifier is respectively connected to the source terminal of the sixth NMOS transistor and the bit line of the second RRAM memory array, the output terminal of the second error amplifier is connected to the gate terminal of the sixth NMOS transistor, and the drain terminal of the sixth NMOS transistor is respectively connected to the gate terminal, the drain terminal of the seventh PMOS transistor, and the gate terminal of the eighth PMOS transistor.

[0010] In combination with the first aspect, further, the first RRAM memory array is used to store the weight data of the RRAM arithmetic circuit, and the second RRAM memory array is used to store the reference weight data of the RRAM arithmetic circuit.

[0011] In a second aspect, based on the current subtraction circuit for an RRAM arithmetic circuit described in the first aspect, the present invention proposes a current subtraction operation method, including the following steps:

[0012] Obtain a first bit line current representing the multiplication and accumulation result of the weight data stored in the first RRAM memory array and the input data through the first clamping circuit;

[0013] Mirror the first bit line current through a PMOS current mirror circuit to obtain a first mirror current;

[0014] Obtain a second bit line current representing the multiplication and accumulation result of the reference weight data stored in the second RRAM memory array and the reference input data through the second clamping circuit;

[0015] Mirror the second bit line current through a PMOS current mirror circuit to obtain a second mirror current;

[0016] Input the first mirror current and the second mirror current into an NMOS current mirror circuit for current subtraction operation to obtain a first output current and a second output current;

[0017] By comparing the magnitudes of the first output current and the second output current, the magnitude relationship between the multiplication and accumulation result of the weight data and the input data in the RRAM arithmetic circuit and the multiplication and accumulation result of the reference weight data and the reference input data is obtained.

[0018] Combined with the second aspect, further, in the PMOS current mirror circuit, the first bit line current is mirrored to the second PMOS transistor through the first PMOS transistor to obtain a first mirror current, and the second bit line current is mirrored to the seventh PMOS transistor through the eighth PMOS transistor to obtain a second mirror current;

[0019] In the NMOS current mirror circuit, the first mirror current is obtained through the first NMOS transistor, and the second mirror current is mirrored into the first NMOS transistor through the fourth NMOS transistor, so that the first mirror current and the second mirror current exist in the same circuit.

[0020] Combined with the second aspect, further, the operation of the current subtraction operation is as follows:

[0021] If the first mirror current is greater than the second mirror current, the third PMOS transistor operates in the cut-off state, and the second NMOS transistor operates in the saturation state. The current flowing through the second NMOS transistor is the difference between the current flowing through the second PMOS transistor and the current flowing through the first NMOS transistor. The second NMOS transistor mirrors the current to the current branch where the third NMOS transistor is located, and the current is mirrored to the sixth PMOS transistor through the fifth PMOS transistor and then output to obtain the first output current. At the same time, the second output current mirrored from the third PMOS transistor to the fourth PMOS transistor approaches 0;

[0022] If the first mirror current is less than the second mirror current, the third PMOS transistor operates in the saturation state, and the second NMOS transistor operates in the cut-off state. The current flowing through the third PMOS transistor is the difference between the current flowing through the first NMOS transistor and the current flowing through the second PMOS transistor. The current is mirrored to the current branch where the fourth PMOS transistor is located through the third PMOS transistor to obtain the second output current. At the same time, the first output current mirrored from the fifth PMOS transistor to the sixth PMOS transistor approaches 0.

[0023] The following advantages can be obtained by adopting the above technical means:

[0024] The present invention proposes a current subtraction circuit and method applied to an RRAM computing-in-memory circuit. By detecting the magnitudes of the currents flowing through two current branches in the subtraction circuit, the sign and magnitude of the multiplication and accumulation operation result of the RRAM array are determined, and the computing-in-memory multiplication and accumulation are compared and quantified. The present invention realizes the subtraction operation through a current mirror structure. Each current branch is composed of 4 PMOS current mirrors and 2 NMOS current mirrors. The circuit structure is relatively simple and symmetric, with a small number of transistors used. Moreover, through the combined use of PMOS current mirrors and NMOS current mirrors, the logic of the subtraction operation is also relatively simple, reducing the circuit complexity and design difficulty. At the same time, through the current mirror structure, the multiplication and accumulation result of the computing-in-memory can be increased or decreased proportionally to obtain a higher-precision quantization result or consume less energy. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 FIG. is a schematic structural diagram of a current subtraction circuit applied to an RRAM computing-in-memory circuit according to the present invention;

[0026] Figure 2 FIG. is a flowchart of the steps of the current subtraction operation method according to the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] The technical solution of the present invention will be further described below with reference to the accompanying drawings:

[0028] Embodiment 1:

[0029] The present invention proposes a current subtraction circuit applied to an RRAM computing-in-memory circuit, as Figure 1 shown, which includes a first clamping circuit, a second clamping circuit, a PMOS current mirror circuit, and an NMOS current mirror circuit.

[0030] The first clamping circuit and the second clamping circuit have the same structure, and each includes 1 RRAM storage array, 1 NMOS transistor, and 1 error amplifier. Specifically, the first clamping circuit includes a first RRAM storage array (RRAM), a fifth NMOS transistor (M N0 ), and a first error amplifier (A0), and the second clamping circuit includes a second RRAM storage array (RRAMR), a sixth NMOS transistor (M N1 ), and a second error amplifier (A1). Transistors M N0 and M N1 are respectively used to adjust the bit line current of the array RRAM or RRAMR.

[0031] The PMOS current mirror circuit includes 8 PMOS transistors, which are denoted as the first to eighth PMOS transistors (M P0 ~M P7 ) for easy distinction.

[0032] The NMOS current mirror circuit includes four NMOS transistors, which are denoted as the first to fourth NMOS transistors (M N0 ~M N3 ) for the sake of easy distinction.

[0033] In the PMOS current mirror circuit and the NMOS current mirror circuit, four PMOS transistors and two NMOS transistors form a current branch.

[0034] In the embodiment of the present invention, the positive input terminal of the first error amplifier is connected to the bit line clamping voltage V CLP , the negative input terminal of the first error amplifier is respectively connected to the source terminal of the fifth NMOS transistor and the bit line of the first RRAM memory array, the output terminal of the first error amplifier is connected to the gate terminal of the fifth NMOS transistor, and the drain terminal of the fifth NMOS transistor is respectively connected to the drain terminal, gate terminal of the first PMOS transistor, and the gate terminal of the second PMOS transistor; the drain terminal of the second PMOS transistor is connected to the gate terminal and drain terminal of the third PMOS transistor, the gate terminal of the fourth PMOS transistor, the drain terminal of the first NMOS transistor, the drain terminal and gate terminal of the second NMOS transistor, and the gate terminal of the third NMOS transistor; the drain terminal of the third NMOS transistor is connected to the drain terminal and gate terminal of the fifth PMOS transistor and the gate terminal of the sixth PMOS transistor; the gate terminal of the first NMOS transistor is connected to the gate terminal and drain terminal of the fourth NMOS transistor and the drain terminal of the seventh PMOS transistor; the gate terminal of the seventh PMOS transistor is connected to the gate terminal and drain terminal of the eighth PMOS transistor and the drain terminal of the sixth NMOS transistor; the positive input terminal of the second error amplifier is connected to the bit line clamping voltage V CLP , and the negative input terminal of the second error amplifier is respectively connected to the source terminal of the sixth NMOS transistor and the bit line of the second RRAM memory array, and the output terminal of the second error amplifier is connected to the gate terminal of the sixth NMOS transistor.

[0035] The source terminals of the first to eighth PMOS transistors are all connected to the power supply voltage; the source terminals of the first to fourth NMOS transistors are all connected to the ground potential.

[0036] In the circuit of the present invention, the first RRAM memory array is used to store the weight data of the RRAM computing circuit, and the second RRAM memory array is used to store the reference weight data of the RRAM computing circuit.

[0037] The sign and magnitude of the multiplication and accumulation operation result of the RRAM array are determined by detecting the magnitudes of the currents flowing through two current branches in the subtraction circuit. The clamping circuit represents the weight data stored in the RRAM storage array with current, and performs a subtraction operation on the current corresponding to the weight data and the current corresponding to the reference weight data through a current mirror circuit. When the current corresponding to the weight data is different from the current corresponding to the reference weight data, the currents (IBL+, IBL-) flowing through the two current branches used to judge the sign and magnitude of the multiplication and accumulation result in the subtraction circuit will also have significant differences. If the current corresponding to the weight data is greater than the current corresponding to the reference weight data, the current IBL+ is significantly greater than the current IBL-; if the current corresponding to the weight data is less than the current corresponding to the reference weight data, the current IBL- is significantly greater than the current IBL+, so as to obtain the subtraction result.

[0038] Embodiment 2:

[0039] Based on the current subtraction circuit in Embodiment 1, the present invention also proposes a current subtraction operation method, as Figure 2 shown, which specifically includes the following steps:

[0040] Step A: Through the "virtual short" characteristic of the first error amplifier, clamp the bit line of the first RRAM storage array to the clamping voltage V CLP , and then obtain the first bit line current (I BL ) representing the multiplication and accumulation result of the weight data and the input data stored in the first RRAM storage array through the first clamping circuit.

[0041] Step B: Mirror the first bit line current through the PMOS current mirror circuit to obtain the first mirror current (I BL0 ), specifically, mirror the first bit line current to the second PMOS transistor through the first PMOS transistor to obtain the first mirror current.

[0042] Step C: Through the "virtual short" characteristic of the second error amplifier, clamp the bit line of the second RRAM storage array to the clamping voltage V CLP , and then obtain the second bit line current (IBLR) representing the multiplication and accumulation result of the reference weight data and the reference input data stored in the second RRAM storage array through the second clamping circuit.

[0043] Step D: Mirror the second bit line current through the PMOS current mirror circuit to obtain the second mirror current (I BL1 ), specifically, mirror the second bit line current to the seventh PMOS transistor through the eighth PMOS transistor to obtain the second mirror current.

[0044] Step E: Input the first mirror current and the second mirror current into the NMOS current mirror circuit to perform a current subtraction operation, obtaining a first output current (IBL+) and a second output current (IBL-).

[0045] Obtain the first mirror current through the first NMOS transistor, and mirror the second mirror current into the first NMOS transistor through the fourth NMOS transistor, so that the first mirror current and the second mirror current exist in the same circuit for subtraction operation.

[0046] The operation of the current subtraction is as follows:

[0047] If the first mirror current is greater than the second mirror current, the third PMOS transistor operates in the cut-off state, and the second NMOS transistor operates in the saturation state. The current flowing through the second NMOS transistor is the difference between the current flowing through the second PMOS transistor and the current flowing through the first NMOS transistor. The second NMOS transistor mirrors the current to the current branch where the third NMOS transistor is located, and the current is mirrored to the sixth PMOS transistor through the fifth PMOS transistor and then output to obtain the larger first output current. At the same time, the second output current mirrored to the fourth PMOS transistor through the third PMOS transistor is smaller and approaches 0.

[0048] If the first mirror current is less than the second mirror current, the third PMOS transistor operates in the saturation state, and the second NMOS transistor operates in the cut-off state. The current flowing through the third PMOS transistor is the difference between the current flowing through the first NMOS transistor and the current flowing through the second PMOS transistor. The current is mirrored to the current branch where the fourth PMOS transistor is located through the third PMOS transistor to obtain the larger second output current. At the same time, the first output current mirrored to the sixth PMOS transistor through the fifth PMOS transistor is smaller and approaches 0.

[0049] Step F: By comparing the magnitudes of the first output current and the second output current, obtain the magnitude relationship between the multiplication and accumulation result of the weight data and the input data and the multiplication and accumulation result of the reference weight data and the reference input data in the RRAM storage and computing circuit.

[0050] The present invention determines the sign and magnitude of the multiplication and accumulation operation result of the RRAM array by detecting the magnitudes of the currents flowing through two current branches in a subtraction circuit, and performs comparison quantization on the in-memory multiplication and accumulation. Compared with the prior art, the present invention realizes subtraction operation through a current mirror structure. Each current branch is composed of 4 PMOS current mirrors and 2 NMOS current mirrors. The circuit structure is relatively simple and symmetric, with a small number of transistors used. Moreover, through the combined use of PMOS current mirrors and NMOS current mirrors, the logic of the subtraction operation is also relatively simple, reducing the circuit complexity and design difficulty. At the same time, through the current mirror structure, the multiplication and accumulation result of the in-memory operation can be increased or decreased proportionally to obtain a higher-precision quantization result or consume less energy.

[0051] In the description of the present invention, it should be noted that the terms "first", "second", and "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0052] The above are only the preferred embodiments of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and deformations can be made, and these improvements and deformations should also be regarded as the protection scope of the present invention.

Claims

1. A current subtraction circuit applied to an RRAM computing-in-memory circuit, characterized in that, It includes a first clamping circuit, a second clamping circuit, a PMOS current mirror circuit, and an NMOS current mirror circuit; The PMOS current mirror circuit includes 8 PMOS transistors, and the NMOS current mirror circuit includes 4 NMOS transistors; The first clamping circuit is connected to the drain terminal and gate terminal of the first PMOS transistor, and the gate terminal of the second PMOS transistor; the drain terminal of the second PMOS transistor is connected to the gate terminal and drain terminal of the third PMOS transistor, the gate terminal of the fourth PMOS transistor, the drain terminal of the first NMOS transistor, the drain terminal and gate terminal of the second NMOS transistor, and the gate terminal of the third NMOS transistor; the drain terminal of the third NMOS transistor is connected to the drain terminal and gate terminal of the fifth PMOS transistor, and the gate terminal of the sixth PMOS transistor; the gate terminal of the first NMOS transistor is connected to the gate terminal and drain terminal of the fourth NMOS transistor, and the drain terminal of the seventh PMOS transistor; the gate terminal of the seventh PMOS transistor is connected to the gate terminal and drain terminal of the eighth PMOS transistor and the second clamping circuit; the source terminals of the first to eighth PMOS transistors are all connected to the power supply voltage; the source terminals of the first to fourth NMOS transistors are all connected to the ground potential.

2. The current subtraction circuit applied to the RRAM arithmetic circuit according to claim 1, characterized in that, The first clamping circuit includes a first RRAM memory array, a fifth NMOS transistor, and a first error amplifier. The positive input terminal of the first error amplifier is connected to the bit line clamping voltage V CLP . The negative input terminal of the first error amplifier is respectively connected to the source terminal of the fifth NMOS transistor and the bit line of the first RRAM memory array. The output terminal of the first error amplifier is connected to the gate terminal of the fifth NMOS transistor. The drain terminal of the fifth NMOS transistor is respectively connected to the drain terminal and the gate terminal of the first PMOS transistor, and the gate terminal of the second PMOS transistor.

3. The current subtraction circuit applied to the RRAM arithmetic circuit according to claim 1, wherein The second clamping circuit includes a second RRAM memory array, a sixth NMOS transistor, and a second error amplifier. The positive input terminal of the second error amplifier is connected to the bit line clamping voltage V CLP , the negative input terminal of the second error amplifier is respectively connected to the source terminal of the sixth NMOS transistor and the bit line of the second RRAM memory array, the output terminal of the second error amplifier is connected to the gate terminal of the sixth NMOS transistor, and the drain terminal of the sixth NMOS transistor is respectively connected to the gate terminals of a seventh PMOS transistor, an eighth PMOS transistor, and the drain terminal of the eighth PMOS transistor.

4. The current subtraction circuit applied to the RRAM arithmetic circuit according to claim 2 or 3, characterized in that, The first RRAM storage array is used to store the weight data of the RRAM arithmetic circuit, and the second RRAM storage array is used to store the reference weight data of the RRAM arithmetic circuit.

5. A current subtraction operation method for a current subtraction circuit applied to an RRAM computing-in-memory circuit according to claim 1, characterized in that, It includes the following steps: Obtain the first bit line current representing the multiplication and accumulation result of the weight data stored in the first RRAM storage array and the input data through the first clamping circuit; Mirror the first bit line current through the PMOS current mirror circuit to obtain the first mirror current; Obtain the second bit line current representing the multiplication and accumulation result of the reference weight data stored in the second RRAM storage array and the reference input data through the second clamping circuit; Mirror the second bit line current through the PMOS current mirror circuit to obtain the second mirror current; Input the first mirror current and the second mirror current into the NMOS current mirror circuit for current subtraction operation to obtain the first output current and the second output current; Obtain the magnitude relationship between the multiplication and accumulation result of the weight data and the input data and the multiplication and accumulation result of the reference weight data and the reference input data in the RRAM arithmetic circuit by comparing the magnitudes of the first output current and the second output current.

6. A method for current subtraction operation according to claim 5, characterized in that, In the PMOS current mirror circuit, mirror the first bit line current to the second PMOS transistor through the first PMOS transistor to obtain the first mirror current, and mirror the second bit line current to the seventh PMOS transistor through the eighth PMOS transistor to obtain the second mirror current; In the NMOS current mirror circuit, obtain the first mirror current through the first NMOS transistor, and mirror the second mirror current to the first NMOS transistor through the fourth NMOS transistor, so that the first mirror current and the second mirror current exist in the same circuit.

7. A method for current subtraction operation according to claim 5, characterized in that The operation of the current subtraction is as follows: If the first mirror current is greater than the second mirror current, the third PMOS transistor operates in the cut-off state, and the second NMOS transistor operates in the saturation state. The current flowing through the second NMOS transistor is the difference between the current flowing through the second PMOS transistor and the current flowing through the first NMOS transistor. The second NMOS transistor mirrors the current to the current branch where the third NMOS transistor is located, and the current is mirrored to the sixth PMOS transistor through the fifth PMOS transistor and then output to obtain the first output current. At the same time, the second output current mirrored to the fourth PMOS transistor through the third PMOS transistor approaches 0; If the first mirror current is less than the second mirror current, the third PMOS transistor operates in the saturation state, and the second NMOS transistor operates in the cut-off state. The current flowing through the third PMOS transistor is the difference between the current flowing through the first NMOS transistor and the current flowing through the second PMOS transistor. The current is mirrored to the current branch where the fourth PMOS transistor is located through the third PMOS transistor to obtain the second output current. At the same time, the first output current mirrored to the sixth PMOS transistor through the fifth PMOS transistor approaches 0.

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