Multilayer ceramic electronic components

Abstract

The present invention provides a laminated ceramic electronic component that can effectively suppress the generation of cracks in the laminated ceramic electronic component and suppress the generation of ion migration. A laminated ceramic capacitor (10) as an example of the laminated ceramic electronic component of the present invention comprises a laminate (12) having a plurality of ceramic layers (14) and a plurality of internal electrode layers (16) stacked thereon, and a pair of external electrodes (30) electrically connected to the internal electrode layers (16) and formed on both end faces of the laminate (12). The pair of external electrodes (30) comprises a base electrode layer (32) including a metal component, a conductive resin layer (34) disposed on the base electrode layer (32) and including a thermosetting resin and a metal component, and a Ni plating layer (36) disposed on the conductive resin layer (34). Stress is applied to the Ni plating layer (36), the stress being greater than 150 MPa and less than 50 MPa, and the end of the Ni plating layer (36) is in contact with the laminate (12).

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic electronic component. Background Art

[0002] In recent years, ceramic electronic components, such as multilayer ceramic capacitors, have been used in harsher environments than ever before. For example, electronic components used in mobile devices such as mobile phones and portable music players are required to withstand the impact of being dropped. Specifically, even in the event of a drop, the electronic components must be prevented from falling off the mounting substrate or from cracking.

[0003] Furthermore, electronic components used in automotive equipment such as ECUs (Electronic Control Units) are required to withstand the impact of thermal cycles. Specifically, they must prevent cracks from forming in electronic components even when subjected to flexural stress caused by the thermal expansion and contraction of the mounting substrate during thermal cycles.

[0004] In response to this, proposals have been made to use thermosetting resin pastes for the external electrodes of ceramic electronic components. For example, Patent Document 1 employs a countermeasure: a thermosetting epoxy resin layer is formed between the conventional electrode layer and the Ni plating layer to prevent cracks from penetrating into the capacitor body (improving flex resistance) even in harsh environments.

[0005] In this structure, when stress is generated by the impact of a drop or flexural stress is generated by thermal expansion of the mounting substrate due to thermal cycling, the stress transmitted to the mounting substrate (deformation of the mounting substrate) is released by peeling between the electrode layer and the epoxy-based thermosetting resin layer starting from the tip of the epoxy-based thermosetting resin, thereby suppressing the intrusion of cracks into the ceramic electronic component body (laminated body).

[0006] Prior art literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Laid-Open No. 11-162771 Summary of the Invention

[0009] Problems to be solved by the invention

[0010] However, in a laminated ceramic electronic component such as Patent Document 1, Ag or Cu is generally used as the metal powder for the thermosetting resin layer. Ag or Cu is an element that easily causes migration. By causing migration, the external electrodes arranged at both ends of the laminated ceramic electronic component may be conductive to each other, causing a short circuit in the laminated ceramic electronic component.

[0011] It should be noted that migration occurs through the mechanism described below.

[0012] Specifically, when voltage is applied to the external electrodes of a multilayer ceramic electronic component, Ag ionizes on the anode side, decomposing water into ions. This ionized Ag reacts with hydroxide ions to form AgOH. AgOH decomposes into silver oxide, which becomes colloidal and migrates to the cathode side. The ionization of silver oxide and the exchange of electrons result in the precipitation of Ag.

[0013] Therefore, a main object of the present invention is to provide a multilayer ceramic electronic component that can effectively suppress the occurrence of cracks in the multilayer ceramic electronic component and suppress the occurrence of ion migration.

[0014] Means used to solve problems

[0015] The laminated ceramic electronic component of the present invention comprises: a laminated body comprising a plurality of stacked ceramic layers, having a first main surface and a second main surface opposite to each other in the height direction, a first side surface and a second side surface opposite to each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface opposite to each other in the length direction perpendicular to the height direction and the width direction; a first internal electrode layer, which is arranged on the plurality of ceramic layers and exposed on the first end surface; a second internal electrode layer, which is arranged on the plurality of ceramic layers and exposed on the second end surface; a first external electrode, which is electrically connected to the first internal electrode layer, and is arranged on the first end surface, a portion of the first main surface, a portion of the second main surface, A portion of the first side surface and a portion of the second side surface; and a second external electrode electrically connected to the second internal electrode layer, arranged on the second end face, a portion of the first main surface, a portion of the second main surface, a portion of the first side surface and a portion of the second side surface, wherein the first external electrode and the second external electrode have a base electrode layer including a metal component, a conductive resin layer arranged on the base electrode layer and including a thermosetting resin and a metal component, and a Ni plating layer arranged on the conductive resin layer, stress is applied to the Ni plating layer, the stress is greater than -150 MPa and less than 50 MPa, and the end of the Ni plating layer is in contact with the stack.

[0016] The multilayer ceramic electronic component of the present invention has a structure in which a stress of -150 MPa to 50 MPa is applied to the Ni plating layer disposed on the conductive resin layer, and the end of the Ni plating layer contacts the laminate. This ensures reliable contact between the laminate and the Ni plating layer, sealing the gap between the laminate and the Ni plating layer. This maintains the effect of suppressing crack formation in the multilayer ceramic electronic component, blocks Ag precipitation pathways, and suppresses ion migration.

[0017] Therefore, it is possible to suppress ion migration while maintaining the effect of suppressing the occurrence of cracks inside the laminated body of the multilayer ceramic electronic component.

[0018] Effects of the Invention

[0019] According to the present invention, it is possible to provide a multilayer ceramic electronic component capable of effectively suppressing the occurrence of cracks in the multilayer ceramic electronic component and suppressing the occurrence of ion migration.

[0020] The above-mentioned object, other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a perspective view showing the appearance of an example of a multilayer ceramic capacitor as a multilayer ceramic electronic component according to an embodiment of the present invention.

[0022] Figure 2 It is a front view showing an example of a multilayer ceramic capacitor as the multilayer ceramic electronic component according to the first embodiment of the present invention.

[0023] Figure 3 yes Figure 1 Cross-sectional view at line III-III.

[0024] Figure 4 yes Figure 1 Cross-sectional view at line IV-IV.

[0025] Figure 5 (a) shows a structure in which the opposing electrode portion of the internal electrode layer of the multilayer ceramic capacitor according to the embodiment of the present invention is divided into two parts. Figure 1 A cross-sectional view of the line II-II, Figure 5 (b) shows a structure in which the opposing electrode portion of the internal electrode layer of the multilayer ceramic capacitor of the present invention is divided into three parts. Figure 1 A cross-sectional view of the line II-II, Figure 5 (c) shows a structure in which the opposing electrode portion of the internal electrode layer of the multilayer ceramic capacitor of the present invention is divided into four parts. Figure 1 Cross-sectional view at line II-II.

[0026] Figure 6 Schematic cross-sectional view illustrating stress acting on the Ni plating layer of a multilayer ceramic capacitor.

[0027] Description of Reference Numerals

[0028] 10 multilayer ceramic capacitors;

[0029] 12 laminates;

[0030] 12a first main surface;

[0031] 12b second main surface;

[0032] 12c first side;

[0033] 12d second side;

[0034] 12e first end surface;

[0035] 12f second end face;

[0036] 14 ceramic layer;

[0037] 16 internal electrode layer;

[0038] 16a first internal electrode layer;

[0039] 16b second internal electrode layer;

[0040] 18 inner part;

[0041] 20a: first main surface side outer layer portion;

[0042] 20b: outer layer portion on the second main surface side;

[0043] 22a: first side outer layer portion;

[0044] 22b: second side outer layer portion;

[0045] 24a: first end surface side outer layer portion;

[0046] 24b: second end surface side outer layer portion;

[0047] 26a: a first counter electrode portion;

[0048] 26b second counter electrode portion;

[0049] 28a: first lead electrode portion;

[0050] 28b second lead electrode portion;

[0051] 30 external electrodes;

[0052] 30a first external electrode;

[0053] 30b second external electrode;

[0054] 32 base electrode layer;

[0055] 32a a first base electrode layer;

[0056] 32b a second base electrode layer;

[0057] 34 conductive resin layer;

[0058] 34a first conductive resin layer;

[0059] 34b second conductive resin layer;

[0060] 36 Ni plating layer;

[0061] 36a first Ni plating layer;

[0062] 36b second Ni plating layer;

[0063] 38 Sn plating layer;

[0064] 38a first Sn plating layer;

[0065] 38b second Sn plating layer;

[0066] x height direction;

[0067] y width direction;

[0068] z length direction. DETAILED DESCRIPTION

[0069] 1. Multilayer ceramic capacitors

[0070] As an example of a multilayer ceramic electronic component according to an embodiment of the present invention, a multilayer ceramic capacitor will be described.

[0071] Figure 1 This is a perspective view showing the appearance of an example of a multilayer ceramic capacitor as a multilayer ceramic electronic component according to an embodiment of the present invention. Figure 2 It is a front view showing an example of a multilayer ceramic capacitor as the multilayer ceramic electronic component according to the first embodiment of the present invention. Figure 3 yes Figure 1 Cross-sectional view at line III-III. Figure 4 yes Figure 1 Cross-sectional view at line IV-IV.

[0072] like Figures 1 to 4 As shown, the multilayer ceramic capacitor 10 includes a rectangular parallelepiped-shaped multilayer body 12 and external electrodes 30 disposed at both ends of the multilayer body 12 .

[0073] The laminate 12 includes a plurality of stacked ceramic layers 14 and a plurality of internal electrode layers 16 stacked on the ceramic layers 14. Furthermore, the laminate 12 includes a first principal surface 12a and a second principal surface 12b that face each other in the height direction x, a first side surface 12c and a second side surface 12d that face each other in the width direction y perpendicular to the height direction x, and a first end surface 12e and a second end surface 12f that face each other in the length direction z perpendicular to the height direction x and the width direction y. The corners and ridges of the laminate 12 are rounded. A corner is defined as the intersection of three adjacent faces of the laminate, and a ridge is defined as the intersection of two adjacent faces of the laminate. Furthermore, concavities and convexities may be formed on part or all of the first principal surface 12a and the second principal surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f. The ceramic layers 14 and the internal electrode layers 16 are stacked in the height direction x.

[0074] The laminate 12 includes an inner layer portion 18 formed of a single or multiple ceramic layers 14 and multiple internal electrode layers 16 disposed on the ceramic layers 14. The internal electrode layers 16 include a first internal electrode layer 16a extending toward a first end face 12e and a second internal electrode layer 16b extending toward a second end face 12f. In the inner layer portion 18, the multiple first internal electrode layers 16a and the second internal electrode layers 16b are opposed to each other with the ceramic layers 14 interposed therebetween.

[0075] The laminate 12 has a first main surface side outer layer portion 20a formed by a plurality of ceramic layers 14 located on the first main surface 12a side and between the first main surface 12a and the outermost surface of the inner layer portion 18 on the first main surface 12a side and an extension of the outermost surface.

[0076] Similarly, the stack 12 has a second main surface side outer layer portion 20b, which is formed by multiple ceramic layers 14 located on the second main surface 12b side and between the second main surface 12b and the outermost surface of the inner layer portion 18 on the second main surface 12b side and the extension line of the outermost surface.

[0077] The laminate 12 includes a first-side outer layer portion 22a formed of a plurality of ceramic layers 14 located on the first side 12c side and between the first side 12c and the outermost surface of the inner layer portion 18 on the first side 12c side.

[0078] Similarly, the laminate 12 includes a second side surface outer layer portion 22b formed of a plurality of ceramic layers 14 located on the second side surface 12d and between the second side surface 12d and the outermost surface of the inner layer portion 18 on the second side surface 12d.

[0079] The laminated body 12 has a first end surface side outer layer portion 24a formed of a plurality of ceramic layers 14 located on the first end surface 12e side and between the first end surface 12e and the outermost surface of the inner layer portion 18 on the first end surface 12e side.

[0080] Similarly, the laminate 12 includes a second end surface side outer layer portion 24b formed of a plurality of ceramic layers 14 located on the second end surface 12f side and between the second end surface 12f and the outermost surface of the inner layer portion 18 on the second end surface 12f side.

[0081] The first principal surface-side outer layer portion 20 a is an assembly of a plurality of ceramic layers 14 located on the first principal surface 12 a side of the laminate 12 and between the first principal surface 12 a and the internal electrode layer 16 closest to the first principal surface 12 a .

[0082] The second principal surface side outer layer portion 20 b is an assembly of a plurality of ceramic layers 14 located on the second principal surface 12 b side of the laminate 12 and between the second principal surface 12 b and the internal electrode layer 16 closest to the second principal surface 12 b .

[0083] The dimensions of the laminate 12 are not particularly limited, but preferably, the dimension in the longitudinal direction z is 0.186 mm to 9.59 mm, the dimension in the width direction y is 0.08 mm to 9.73 mm, and the dimension in the height direction x is 0.08 mm to 9.73 mm.

[0084] Ceramic layer 14 can be formed of, for example, a dielectric material as a ceramic material. Examples of such dielectric materials include dielectric ceramics containing BaTiO3, CaTiO3, SrTiO3, or CaZrO3. When containing the aforementioned dielectric materials as the main component, materials containing a lesser amount of secondary components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds, depending on the desired properties of the laminate 12, may also be used.

[0085] Note that, when a piezoelectric ceramic material is used for the ceramic layer 14 , the multilayer ceramic electronic component functions as a piezoelectric component. Specific examples of piezoelectric ceramic materials include PZT (lead zirconate titanate)-based ceramic materials.

[0086] Furthermore, the multilayer ceramic electronic component functions as a thermistor when a semiconductor ceramic material is used for the ceramic layer 14. Specific examples of the semiconductor ceramic material include spinel-based ceramic materials.

[0087] When a magnetic ceramic material is used for ceramic layer 14, the multilayer ceramic electronic component functions as an inductor. When functioning as an inductor, internal electrode layer 16 becomes a coil-shaped conductor. Specific examples of magnetic ceramic materials include ferrite ceramic materials.

[0088] The thickness of the fired ceramic layer 14 is preferably not less than 0.5 μm and not more than 15 μm. The number of stacked ceramic layers 14 is preferably not less than 10 and not more than 700. It should be noted that the number of ceramic layers 14 is the sum of the number of ceramic layers 14 in the inner layer portion 18 and the number of ceramic layers 14 in the first main surface side outer layer portion 20 a and the second main surface side outer layer portion 20 b.

[0089] The laminate 12 includes, for example, a plurality of substantially rectangular first internal electrode layers 16a and a plurality of second internal electrode layers 16b as the plurality of internal electrode layers 16. The plurality of first internal electrode layers 16a and the plurality of second internal electrode layers 16b are buried and alternately arranged at equal intervals along the height direction x of the laminate 12 with the ceramic layers 14 interposed therebetween.

[0090] The first internal electrode layer 16a is disposed on the plurality of ceramic layers 14 and is located within the laminate 12. The first internal electrode layer 16a includes a first opposing electrode portion 26a that opposes the second internal electrode layer 16b, and a first lead electrode portion 28a located at one end of the first internal electrode layer 16a and extending from the first opposing electrode portion 26a to the first end surface 12e of the laminate 12. The end of the first lead electrode portion 28a is extended to the surface of the first end surface 12e and is exposed from the laminate 12.

[0091] The shape of the first counter electrode portion 26a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or may be inclined (tapered) in plan view. Alternatively, the shape may be tapered, tilting in either direction in plan view.

[0092] The shape of the first lead electrode portion 28a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or may be inclined (tapered) in plan view. Alternatively, the shape may be tapered, tilting in either direction in plan view.

[0093] The width of the first counter electrode portion 26a of the first internal electrode layer 16a and the width of the first lead-out electrode portion 28a of the first internal electrode layer 16a may be the same, or either width may be narrower.

[0094] The second internal electrode layer 16b is disposed on the plurality of ceramic layers 14 and is located within the laminate 12. The second internal electrode layer 16b includes a second opposing electrode portion 26b opposing the first internal electrode layer 16a, and a second lead electrode portion 28b located at one end of the second internal electrode layer 16b and extending from the second opposing electrode portion 26b to the second end face 12f of the laminate 12. The end of the second lead electrode portion 28b is extended to the surface of the second end face 12f and is exposed from the laminate 12.

[0095] The shape of the second counter electrode portion 26b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or may be inclined (tapered) in plan view. Alternatively, the shape may be tapered, tilting in either direction in plan view.

[0096] The shape of the second lead electrode portion 28b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or may be inclined (tapered) in plan view. Alternatively, the shape may be tapered, tilting in either direction in plan view.

[0097] The width of the second counter electrode portion 26b of the second internal electrode layer 16b and the width of the second lead electrode portion 28b of the second internal electrode layer 16b may be the same, or either width may be narrower.

[0098] The first internal electrode layer 16 a and the second internal electrode layer 16 b can be made of an appropriate conductive material such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals such as an Ag—Pd alloy.

[0099] The thickness of each of the internal electrode layers 16 , that is, the first internal electrode layer 16 a and the second internal electrode layer 16 b , is preferably not less than 0.2 μm and not more than 2.0 μm.

[0100] Furthermore, the total number of the first internal electrode layers 16 a and the second internal electrode layers 16 b is preferably 10 or more and 700 or less.

[0101] like Figures 1 to 3 As shown, external electrodes 30 are arranged on the first end surface 12 e side and the second end surface 12 f side of the stacked body 12 .

[0102] The external electrode 30 includes a first external electrode 30 a and a second external electrode 30 b .

[0103] The first external electrode 30a is connected to the first internal electrode layer 16a and is disposed at least on the surface of the first end surface 12e. Alternatively, the first external electrode 30a may extend from the first end surface 12e of the laminate 12 and be disposed on a portion of the first principal surface 12a, a portion of the second principal surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the first external electrode 30a is electrically connected to the first extraction electrode portion 28a of the first internal electrode layer 16a.

[0104] The second external electrode 30b is connected to the second internal electrode layer 16b and is disposed at least on the surface of the second end surface 12f. Alternatively, the second external electrode 30b may extend from the second end surface 12f and be disposed on a portion of the first principal surface 12a, a portion of the second principal surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the second external electrode 30b is electrically connected to the second extraction electrode portion 28b of the second internal electrode layer 16b.

[0105] The external electrode 30 includes a base electrode layer 32 including a metal component, a conductive resin layer 34 disposed on the base electrode layer 32 and including a thermosetting resin and a metal component, and a Ni plating layer 36 disposed on the conductive resin layer 34 .

[0106] The first external electrode 30a includes a first base electrode layer 32a including a metal component, a first conductive resin layer 34a disposed on the first base electrode layer 32a and including a curable resin and a metal component, and a first Ni plating layer 36a disposed on the first conductive resin layer 34a.

[0107] The second external electrode 30b includes a second base electrode layer 32b including a metal component, a second conductive resin layer 34b including a curable resin and a metal component and disposed on the second base electrode layer 32b, and a second Ni plating layer 36b disposed on the second conductive resin layer 34b.

[0108] Within the laminate 12, the first opposing electrode portion 26a of the first internal electrode layer 16a and the second opposing electrode portion 26b of the second internal electrode layer 16b face each other via the ceramic layer 14, thereby forming an electrostatic capacitor. Consequently, an electrostatic capacitor is obtained between the first external electrode 30a connected to the first internal electrode layer 16a and the second external electrode 30b connected to the second internal electrode layer 16b, exhibiting capacitor characteristics.

[0109] It should be noted that if Figure 5 As shown, Figure 1The laminate 12 shown may also have a structure in which, in addition to the first internal electrode layer 16a and the second internal electrode layer 16b, a floating internal electrode layer 16c that is not extended to either the first end face 12e or the second end face 12f is provided, and the opposing electrode portion 26c is divided into a plurality of parts by the floating internal electrode layer 16c. Figure 5 The two-layer structure shown in (a) Figure 5 The three-layer structure shown in (b) Figure 5 The four-layer structure shown in (c) can, of course, also have four or more layers. By dividing opposing electrode portion 26c into multiple layers, multiple capacitor components are formed between opposing internal electrode layers 16a, 16b, and 16c, and these capacitor components are connected in series. This reduces the voltage applied to each capacitor component, enabling a higher withstand voltage for multilayer ceramic capacitor 10.

[0110] The foundation electrode layer 32 includes a first foundation electrode layer 32 a and a second foundation electrode layer 32 b .

[0111] The first foundation electrode layer 32a is connected to the first internal electrode layer 16a and is disposed on the surface of the first end surface 12e. Alternatively, the first foundation electrode layer 32a may extend from the first end surface 12e and be disposed on a portion of the first principal surface 12a, a portion of the second principal surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the first foundation electrode layer 32a is electrically connected to the first extraction electrode portion 28a of the first internal electrode layer 16a.

[0112] The second foundation electrode layer 32b is connected to the second internal electrode layer 16b and is disposed on the surface of the second end surface 12f. Alternatively, the second foundation electrode layer 32b may extend from the second end surface 12f and be disposed on a portion of the first principal surface 12a, a portion of the second principal surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the second foundation electrode layer 32b is electrically connected to the second extraction electrode portion 28b of the second internal electrode layer 16b.

[0113] The base electrode layer 32 includes a metal component. Alternatively, the base electrode layer 32 preferably includes a glass component or a ceramic component. This improves the adhesion between the laminate 12 and the base electrode layer 32. It should be noted that the base electrode layer 32 may include both a glass component and a ceramic component.

[0114] The metal component included in the base electrode layer 32 includes, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, and the like. The glass component included in the base electrode layer 32 includes, for example, at least one selected from B, Si, Ba, Mg, Al, Li, and the like. The ceramic component may be the same or a different type of ceramic material as the ceramic layer 14. For example, the ceramic component includes, for example, at least one selected from BaTiO3, CaTiO3, (Ba, Ca)TiO3, SrTiO3, and CaZrO3.

[0115] The base electrode layer 32 may be composed of multiple layers.

[0116] In the case where the base electrode layer 32 includes a metal component and a glass component, the base electrode layer 32 is formed by applying a conductive paste including a glass component and a metal component to the stack 12 and sintering it. It can also be formed by sintering it simultaneously with the internal electrode layer 16, or it can be formed by sintering it after sintering the internal electrode layer 16.

[0117] The thickness of the first foundation electrode layer 32a located at the center of the first end face 12e in the height direction x in the longitudinal direction z connecting the first end face 12e and the second end face 12f is preferably about 2 μm or more and 220 μm or less, for example.

[0118] The thickness of the second foundation electrode layer 32b located at the center of the second end surface 12f in the height direction x in the longitudinal direction z connecting the first end surface 12e and the second end surface 12f is preferably about 2 μm to 220 μm, for example.

[0119] The thickness in the height direction x connecting the first main surface 12a and the second main surface 12b of the first base electrode layer 32a located in a part of the first main surface 12a and a part of the second main surface 12b in the center portion in the length direction z connecting the first end surface 12e and the second end surface 12f is preferably about 4 μm or more and 40 μm or less.

[0120] The thickness in the height direction x connecting the first main surface 12a and the second main surface 12b of the second base electrode layer 32b located in a portion of the first main surface 12a and a portion of the second main surface 12b in the center portion in the length direction z connecting the first end surface 12e and the second end surface 12f is preferably, for example, greater than or equal to 4 μm and less than or equal to 40 μm.

[0121] The thickness in the width direction y connecting the first side surface 12c and the second side surface 12d of the first base electrode layer 32a located at a portion of the first side surface 12c and a portion of the second side surface 12d in the center portion in the length direction z connecting the first end surface 12e and the second end surface 12f is preferably about 4 μm or more and 40 μm or less.

[0122] The thickness in the width direction y connecting the first side surface 12c and the second side surface 12d of the second base electrode layer 32b located at a portion of the first side surface 12c and a portion of the second side surface 12d in the center portion in the length direction z connecting the first end surface 12e and the second end surface 12f is preferably about 4 μm or more and 40 μm or less.

[0123] Furthermore, on the foundation electrode layer 32 , there is a conductive resin layer 34 which is disposed on the foundation electrode layer 32 and includes a resin component and a metal component.

[0124] The conductive resin layer 34 includes a first conductive resin layer 34 a and a second conductive resin layer 34 b .

[0125] The first conductive resin layer 34 a is disposed on the first underlying electrode layer 32 a . It is preferred that the first conductive resin layer 34 a be disposed to cover the first underlying electrode layer 32 a , and that an end portion of the first conductive resin layer 34 a be in contact with the laminate 12 .

[0126] The second conductive resin layer 34 b is disposed on the second foundation electrode layer 32 b . It should be noted that the second conductive resin layer 34 b is preferably disposed to cover the second foundation electrode layer 32 b , and an end portion of the second conductive resin layer 34 b is in contact with the laminate 12 .

[0127] Because the conductive resin layer 34 includes a thermosetting resin as its resin component, it is more flexible than, for example, the base electrode layer 32, which includes a plated film or a fired product of a metal component and a glass component. Therefore, even when the multilayer ceramic capacitor 10 is subjected to physical impact or shock due to thermal cycling caused by the application of flexural stress to the mounting substrate, the conductive resin layer 34 functions as a buffer layer, preventing cracks from forming in the multilayer ceramic capacitor 10.

[0128] As the thermosetting resin of the conductive resin layer 34, various known thermosetting resins such as epoxy resin, phenoxy resin, phenolic resin, polyurethane resin, silicone resin, and polyimide resin can be used. Among them, epoxy resin is one of the most suitable resins due to its excellent heat resistance, moisture resistance, and adhesion.

[0129] Furthermore, the conductive resin layer 34 preferably includes a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known epoxy resin curing agents such as phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, and amide-imide-based compounds can be used.

[0130] The metal component included in the conductive resin layer 34 is preferably a metal filler, preferably including Ag. It can be Ag alone, or an alloy including Ag or a metal powder coated with Ag on the surface of the metal powder can also be used. When using a metal powder coated with Ag on the surface of the metal powder, it is preferred to use Cu, Ni, Sn, Bi or their alloy powders as the metal powder. The reason for using Ag as the metal filler is that Ag has the lowest resistivity among metals and is suitable for electrode materials, and Ag is a precious metal, so it does not oxidize and has high weather resistance. In addition, it is because the metal of the base material can be made cheap while maintaining the above-mentioned characteristics of Ag.

[0131] The shape of the metal filler included in the conductive resin layer 34 is not particularly limited. The metal filler may be spherical, flat, etc. Alternatively, spherical metal powder and flat metal powder may be mixed.

[0132] There is no particular limitation on the average particle size of the metal filler included in the conductive resin layer 34. The average particle size of the metal filler may be, for example, approximately 0.3 μm or more and 10 μm or less.

[0133] The average particle size of the metal filler included in the conductive resin layer 34 can be measured by the following method.

[0134] First, the multilayer ceramic capacitor 10 is cross-sectioned and polished from the first side surface 12c or the second side surface 12d to the 1 / 2W position to expose a specific LT cross section. Alternatively, the multilayer ceramic capacitor 10 is cross-sectioned and polished from the first main surface 12a or the second main surface 12b to the 1 / 2T position to expose a specific LW cross section.

[0135] The cross section exposed by the above method is coated for SEM imaging. A coating agent is used whose composition does not overlap with the metal filler included in the conductive resin layer. If the metal filler is Ag or Cu, Pt or Au is used as the coating agent.

[0136] After that, an SEM image near the center of the end face of the conductive resin layer is obtained. Here, the SEM used for shooting is selected to be an SEM that can identify the particle size of the metal filler and other components included in the conductive resin layer. As such an SEM, for example, a desktop SEM, a general-purpose SEM, a FE-SEM, etc. can be used. It should be noted that as conditions for obtaining an SEM image, a shooting mode, an acceleration voltage, and a magnification are selected so that an image that clearly shows the particle size of the metal filler can be obtained. As conditions for obtaining an SEM image, for example, the shooting mode is set to a secondary electron image, the acceleration voltage is set to 15kV, and the magnification is set to a magnification that allows about 100 fillers to enter.

[0137] Next, the captured SEM image is loaded into analysis software (e.g., imageJ, QuickGrain, etc.) capable of binarizing the image, and the metal filler particles are measured. Analysis software for binarizing the SEM image, such as imageJ or QuickGrain, can be used.

[0138] Finally, the average of the equivalent circle diameters of approximately 100 metal fillers was calculated to calculate the average particle size of the metal fillers included in the first conductive resin layer and the second conductive resin layer.

[0139] The metal fillers included in the conductive resin layer 34 are mainly responsible for the electrical conductivity of the conductive resin layer 34. Specifically, the metal fillers are in contact with each other, thereby forming an electrical conduction path inside the conductive resin layer 34.

[0140] The thickness of the conductive resin layer 34 is preferably about 10 μm or more and 200 μm or less, for example.

[0141] Next, refer to Figure 3 and Figure 4 Next, the Ni plating layer 36 disposed on the conductive resin layer 34 , ie, the first Ni plating layer 36 a and the second Ni plating layer 36 b will be described.

[0142] The Ni plating layer 36 is arranged on the conductive resin layer 34 so that its end portion is in contact with the surface of the laminate 12 .

[0143] The first Ni plating layer 36a is arranged such that its end portion contacts the surface of the laminate 12 and covers the first conductive resin layer 34a. In this embodiment, the first Ni plating layer 36a also extends from the first end surface 12e and is arranged on a portion of the first main surface 12a and a portion of the second main surface 12b, as well as a portion of the first side surface 12c and a portion of the second side surface 12d, with its end portion contacting the surface of the laminate 12.

[0144] The second Ni plating layer 36b is arranged such that its end portion contacts the surface of the laminate 12 and covers the second conductive resin layer 34b. In this embodiment, the second Ni plating layer 36b also extends from the second end surface 12f and is arranged on a portion of the first main surface 12a and a portion of the second main surface 12b, as well as a portion of the first side surface 12c and a portion of the second side surface 12d, with its end portion contacting the surface of the laminate 12.

[0145] Stress is applied to the first Ni plating layer 36a and the second Ni plating layer 36b. The stress is from -150 MPa to 50 MPa. When the stress is represented by a negative magnitude, it represents a compressive stress in the direction from the Ni plating layer 36 toward the stack 12, and when the stress is represented by a positive magnitude, it represents a tensile stress in the direction from the stack 12 toward the Ni plating layer 36. Therefore, -150 MPa represents a compressive stress in the direction from the Ni plating layer 36 toward the stack 12, and 50 MPa represents a tensile stress in the direction from the stack 12 toward the Ni plating layer 36. Thus, as Figure 6 As shown, when Ni plating layer 36 is securely in contact with laminate 12, the gap between laminate 12 and Ni plating layer 36 can be sealed, thereby blocking the Ag precipitation path and suppressing ion migration. Therefore, conductive resin layer 34 can suppress ion migration while maintaining the effect of suppressing cracks in laminated ceramic capacitor 10.

[0146] It should be noted that when the stress of the Ni plating layer 36 is less than -150 MPa, the compressive stress of the Ni plating layer 36 increases, thereby increasing the clamping stress on the laminate 12. Therefore, when external stress is applied, cracks are likely to enter the laminated ceramic capacitor, resulting in a decrease in the mechanical strength of the laminated ceramic capacitor.

[0147] Furthermore, when the stress of the Ni plating layer 36 is greater than 50 MPa, the tensile stress of the Ni plating layer increases, and thus the end of the Ni plating layer 36 rises and floats from the surface of the laminate 12. Consequently, a gap is generated between the laminate 12 and the end of the Ni plating layer 36, forming a precipitation path for Ag and causing ion migration.

[0148] Furthermore, the stress applied to the first Ni plating layer 36 a and the second Ni plating layer 36 b is preferably not less than −143 MPa and not more than −51 MPa.

[0149] The stress of the Ni plating layer 36 can be measured by the following method.

[0150] First, the multilayer ceramic capacitor 10 was immersed in a Melstrip (HN980M) liquid for 5 minutes, and then rinsed with water to remove the Sn plating layer 38 (described later).

[0151] Next, the tip of the Ni plating layer 36 on the first main surface 12a or the second main surface 12b or the first side surface 12c or the second side surface 12d of the multilayer ceramic capacitor 10 was measured using X-ray diffraction (μ-XRD) within a range of φ100 μm.

[0152] It is known that the stress of the Ni plating layer 36 varies depending on the current density. The current density applied to the multilayer ceramic capacitor 10 is random. At the tip of the Ni plating layer 36 located on the first principal surface 12a, the second principal surface 12b, the first side surface 12c, or the second side surface 12d, the average current density applied from the initial stage of Ni plating formation until the thickness reaches, for example, 3 μm is the same across all surfaces, as long as the tip of the Ni plating layer 36 is located on the first principal surface 12a, the second principal surface 12b, the first side surface 12c, or the second side surface 12d. Therefore, the same stress acts on all surfaces of the Ni plating layer 36 located on the first principal surface 12a, the second principal surface 12b, the first side surface 12c, or the second side surface 12d, allowing stress measurement at a single location within a single sample without specifying the measurement surface. That is, the stress measurement site can be the tip of the Ni plating layer 36 located on the first main surface 12a or the second main surface 12b, or on the first side surface 12c or the second side surface 12d in the center in the width direction y or the height direction x.

[0153] The thickness of each of the first Ni plating layer 36 a and the second Ni plating layer 36 b is preferably 1 μm or more and 15 μm or less.

[0154] Furthermore, the Ni plating layer 36 also has a function of preventing the conductive resin layer 34 and the base electrode layer 32 from being corroded by the solder used for mounting when the multilayer ceramic capacitor 10 is mounted on a mounting substrate or the like.

[0155] In addition, in this embodiment, if Figure 3 As shown, a Sn plating layer 38 is preferably disposed on the Ni plating layer 36. Specifically, the first Sn plating layer 38a is preferably disposed so as to cover the first Ni plating layer 36a, and the second Sn plating layer 38b is preferably disposed so as to cover the second Ni plating layer 36b. This improves the wettability of the solder used for mounting when the multilayer ceramic capacitor 10 is mounted on a mounting substrate, facilitating mounting. It should be noted that the Sn plating layer 38 is not necessarily required.

[0156] The thickness of each of the first Sn plating layer 38 a and the second Sn plating layer 38 b is preferably 1 μm or more and 15 μm or less.

[0157] The dimension of the multilayer ceramic capacitor 10 including the stack 12, the first external electrode 30a, and the second external electrode 30b in the length direction z is set as L dimension, the dimension of the multilayer ceramic capacitor 10 including the stack 12, the first external electrode 30a, and the second external electrode 30b in the height direction x is set as T dimension, and the dimension of the multilayer ceramic capacitor 10 including the stack 12, the first external electrode 30a, and the second external electrode 30b in the width direction y is set as W dimension.

[0158] The dimensions of the multilayer ceramic capacitor 10 are as follows: L in the length direction z is 0.2 mm to 10.0 mm, W in the width direction y is 0.1 mm to 10.0 mm, and T in the height direction x is 0.1 mm to 10.0 mm. The dimensions of the multilayer ceramic capacitor 10 can be measured using a microscope.

[0159] Figure 1 The illustrated multilayer ceramic capacitor 10 has a structure in which stress of -150 MPa to 50 MPa is applied to the Ni plating layer 36 disposed on the conductive resin layer 34, and the end of the Ni plating layer 36 is in contact with the laminate 12. This ensures reliable contact between the laminate 12 and the Ni plating layer 36, and seals the gap between the laminate 12 and the Ni plating layer 36. Consequently, the effect of suppressing crack formation in the multilayer ceramic capacitor 10 is maintained, and the precipitation path of Ag is blocked, thereby suppressing ion migration.

[0160] Therefore, it is possible to suppress ion migration while maintaining the effect of suppressing the occurrence of cracks inside the laminated body 12 of the laminated ceramic capacitor 10 .

[0161] 2. Manufacturing Method of Multilayer Ceramic Capacitors

[0162] Next, a method for manufacturing a multilayer ceramic capacitor will be described.

[0163] First, a dielectric sheet for the ceramic layer and a conductive paste for the internal electrode layer are prepared. The conductive paste for the dielectric sheet and the internal electrode layer includes a binder and a solvent. The binder and solvent may also be known.

[0164] Then, conductive paste for the internal electrode layer is printed on the dielectric sheet in a predetermined pattern by screen printing or gravure printing, etc. Thus, a dielectric sheet having a pattern for the first internal electrode layer and a dielectric sheet having a pattern for the second internal electrode layer are prepared.

[0165] In addition, regarding the dielectric sheet, a dielectric sheet for an outer layer on which the pattern of the internal electrode layer is not printed is also prepared.

[0166] Next, a predetermined number of outer layer dielectric sheets, not printed with the internal electrode layer pattern, are stacked to form a portion of the second principal surface that will become the outer layer portion. Then, a dielectric sheet printed with the first internal electrode layer pattern and a dielectric sheet printed with the second internal electrode layer pattern are sequentially stacked on the portion that will become the outer layer portion of the second principal surface, achieving the structure of the present invention. This forms the portion that will become the inner layer portion. A predetermined number of outer layer dielectric sheets, not printed with the internal electrode layer pattern, are stacked on the portion that will become the inner layer portion, thereby forming a portion of the first principal surface that will become the outer layer portion of the first principal surface. This produces a laminated sheet.

[0167] Next, the laminated sheets are pressed in the lamination direction by an isostatic press or the like, thereby producing a laminated block.

[0168] Then, the laminated block is cut into predetermined sizes to produce laminated chips. At this time, the corners and ridges of the laminated chips may be rounded by barrel grinding or the like.

[0169] Next, the stacked small pieces are fired to produce the stacked body 12. The firing temperature is determined based on the materials of the ceramic layers or internal electrode layers serving as dielectrics, but is preferably 900°C or higher and 1400°C or lower.

[0170] Next, a conductive paste, which will serve as the base electrode layer, is applied to the first and second end faces of the laminate to form the base electrode layer. When forming a sintered layer as the base electrode layer, a conductive paste containing a glass component and a metal is applied by a method such as dipping, and then sintered to form the base electrode layer. The sintering temperature is preferably between 700°C and 950°C.

[0171] When the base electrode layer is formed of a sintered layer, the sintered layer may contain a ceramic component. In this case, the ceramic component may be contained instead of the glass component, or both.

[0172] The ceramic component is preferably the same type of ceramic material as the laminate. When the sintered layer contains a ceramic component, it is preferable to apply a conductive paste to the pre-fired laminated pieces, and then simultaneously sinter (fire) the pre-fired laminated pieces and the conductive paste applied to the pre-fired laminated pieces to form a laminated body with the sintered layer. The sintering temperature (firing temperature) is preferably 900°C or higher and 1400°C or lower.

[0173] Furthermore, a conductive resin layer is formed on the base electrode layer.

[0174] The conductive resin layer is formed by preparing a conductive resin paste containing a resin component and a metal component and applying it to the base electrode layer using a dipping process. The resin is then heat-treated at a temperature between 200°C and 550°C to cure the paste, forming the conductive electrode layer.

[0175] The atmosphere during the heat treatment at this time is preferably an N2 atmosphere.

[0176] Furthermore, in order to prevent scattering of the resin and oxidation of various metal components, the oxygen concentration is preferably suppressed to 100 ppm or less.

[0177] Next, Ni plating layers as the first Ni plating layer and the second Ni plating layer are formed on the surface of the conductive resin layer. Electroplating is used as a method for forming the first Ni plating layer and the second Ni plating layer. Barrel plating is preferably used as a plating process.

[0178] It should be noted that in order to achieve the stress value of the first Ni plating layer and the second Ni plating layer of the present invention, that is, greater than -150 MPa and less than 50 MPa, the stress can be controlled by the following method. It is known that in a conventional Watt bath, the stress of the plated film represents tensile stress. In contrast, stress relaxants or plating additives called brighteners are sometimes used. It is known that when these additives are used, the stress of the plated film becomes low stress (compressive stress). As the above-mentioned additives, saccharin, sodium naphthalenesulfonate, butynediol, propargyl alcohol, coumarin, thiourea, zinc, etc. can be used. By using these additives alone or simultaneously, the stress of the plated film can be controlled. For example, by adding sulfur-containing primary brighteners such as saccharin and sodium naphthalenesulfonate at a concentration of more than 1 g / L and less than 5 g / L, and secondary brighteners such as butynediol, propargyl alcohol, and coumarin at a concentration of more than 0.1 g / L and less than 0.5 g / L, the internal stress of the Ni plated film can be made compressive stress.

[0179] As another method, a nickel sulfamate plating solution (sulfamate bath) can be used. The sulfamate bath is characterized by low internal stress and is a plating solution that can adjust from tensile stress to compressive stress. In addition, the use of the above-mentioned additives can change the internal stress.

[0180] exist Figures 1 to 4 In the embodiment shown, a Sn plating layer is further formed on the Ni plating layer. Specifically, a first Sn plating layer is formed on the first Ni plating layer, and a second Sn plating layer is formed on the second Ni plating layer. Thus, when the multilayer ceramic capacitor is mounted on a mounting substrate, etc., the wettability of the solder used for mounting can be improved, enabling easy mounting. Electroplating is used as a method for forming the Sn plating layer. Barrel plating is preferably used as a plating process.

[0181] In the above-described manner, the multilayer ceramic capacitor 10 of the present embodiment is manufactured.

[0182] 3. Experimental Examples

[0183] Using the above-described manufacturing method, multilayer ceramic capacitors were fabricated as samples, serving as multilayer ceramic electronic components. The amount of migration and mechanical strength defects were confirmed. For each sample, the stress of the Ni plating layer was controlled to achieve the stresses shown in Table 1 using the above-described manufacturing method. Forty-six samples were fabricated under various stress conditions.

[0184] (a) Specifications of the samples used in the experimental examples

[0185] In the experimental example, it is set Figures 1 to 4 Using the structure shown, a multilayer ceramic capacitor with the following specifications was prepared.

[0186] Dimensions of multilayer ceramic capacitors (design values): L × W × T = 1.0 mm × 0.5 mm × 0.5 mm

[0187] Main component of ceramic layer: BaTiO3

[0188] Capacitance: 0.01μF

[0189] Rated voltage: 50V

[0190] Specifications of external electrode layer

[0191] Specifications of base electrode layer

[0192] Base electrode layer: a sintered layer consisting of conductive metal and glass components

[0193] Conductive metal: Cu

[0194] Thickness of the base electrode layer

[0195] Thickness of the base electrode layer at the center of the first and second end surfaces in the height direction x: 15 μm

[0196] Thickness of the foundation electrode layer in the center of the first and second principal surfaces and the first and second side surfaces in the longitudinal direction z (thickness of the foundation electrode layer in the center of the e-inch): 4 μm

[0197] Specifications of the conductive resin layer

[0198] Metal filler: Ag

[0199] ·Thermosetting resin component: Epoxy

[0200] Curing temperature of thermosetting resin: 200℃

[0201] Thickness of the conductive resin layer at the center of the conductive resin layer in the height direction x on the first and second end faces: 20 μm

[0202] The thickness of the conductive resin layer in the center of the length direction z of the conductive resin layer on the first and second main surfaces and the first and second side surfaces (the thickness of the base electrode layer in the center of the length direction z): 20 μm

[0203] Specifications of the plating layer: A double-layer structure in which a Ni plating layer is formed on the conductive resin layer, and a Sn plating layer is formed on the Ni plating layer.

[0204] Thickness of Ni plating layer:

[0205] Thickness of the Ni plating layer at the center of the Ni plating layer in the height direction x on the first and second end faces: 2.0 μm

[0206] Thickness of the Ni plating layer in the center of the length direction z of the Ni plating layer on the first and second main surfaces and the first and second side surfaces (thickness of the base electrode layer in the center of the length direction e): 2.0 μm

[0207] Thickness of Sn plating layer:

[0208] Thickness of the Sn plating layer at the center of the first and second end faces in the height direction x: 1.5 μm

[0209] Thickness of the Sn plating layer in the center of the length direction z of the Sn plating layer on the first and second main surfaces and the first and second side surfaces (thickness of the base electrode layer in the center of the length direction e): 1.0 μm

[0210] (b) Method for measuring stress of Ni plating layer

[0211] The stress of the Ni plating layer was measured by the following method.

[0212] Specifically, first, a multilayer ceramic capacitor as a sample was immersed in a Melstrip (NH980M) liquid for 5 minutes, and then rinsed with water to remove the Sn plating layer.

[0213] Next, the tip of the Ni plating layer on the first or second main surface or the first or second side surface of the laminated ceramic capacitor from which the Sn plating layer had been peeled was measured using X-ray diffraction (μ-XRD) within a range of φ100 μm.

[0214] It should be noted that the stress of the plating varies according to the current density. The current density applied to the stacked ceramic capacitor acts randomly, and at the front end of the Ni plating layer located on the first main surface or the second main surface or on the first side or the second side, as long as it is the front end of the Ni plating layer located on the first main surface or the second main surface or on the first side or the second side, the average current density applied from the initial stage of Ni plating film formation to, for example, a thickness of 3 μm is the same on any surface. Therefore, as long as it is the Ni plating layer on the first main surface, the second main surface, the first side or the second side, the same stress acts on any surface, so that the stress of one part of a sample is measured without specifying the measurement surface. Specifically, the stress measurement site is the front end of the Ni plating layer on the first main surface or the second main surface, or on the first side or the second side, located in the center of the width direction y or the height direction x.

[0215] (c) Confirmation method of migration based on wet load test

[0216] A wet load test was conducted by applying a 50V DC current to a sample of a multilayer ceramic capacitor in an environment with a humidity of 90% to 95% RH and a temperature of 85°C. The test lasted for 4000 hours. During this time, the insulation resistance value was measured while the test was conducted. The test results showed that the insulation resistance value was 1×10 6 When the value is Ω or less and Ag is deposited in a dendrite-like manner on at least one of the four surfaces: the first main surface, the second main surface, the first side surface, and the second side surface, it is determined that ion migration exists.

[0217] In addition, the insulation resistance value measurement and appearance observation were carried out under the following conditions.

[0218] Insulation resistance measurement

[0219] Equipment: IR tester

[0220] Measurement time: 60 seconds

[0221] ・Appearance observation (confirmation of dendritic precipitates)

[0222] Equipment: Metal microscope

[0223] Field of view: bright field or polarized light

[0224] Magnification: 500 times

[0225] ·Appearance observation (Ag confirmation)

[0226] Equipment: SEM-EDX

[0227] Electron image: reflected electrons

[0228] Accelerating voltage: 15kV

[0229] Magnification: 2000 times

[0230] Detection element: Ag

[0231] (d) Method for confirming mechanical strength defects based on flexural strength test

[0232] First, a sample multilayer ceramic capacitor was mounted on a 1.6 mm thick mounting substrate using solder paste. A pressing rod with a curvature radius of 1 μm was then used to bend the mounting substrate from the back side, where the multilayer ceramic capacitor was not mounted, to apply mechanical stress.

[0233] At this time, the deflection was 5 mm, and the deflection lasted for 60 seconds. After the substrate was bent, the multilayer ceramic capacitor was removed from the mounting substrate, cross-sectioned, and the interior of the multilayer body was observed for cracks. The crack observation was performed by grinding from the first side surface or second side surface, or the first principal surface or second principal surface of the multilayer ceramic capacitor to the LT cross-section or LW cross-section immediately after the internal electrode layer was exposed, and by grinding from the first side surface or second side surface or the first principal surface or second principal surface of the multilayer ceramic capacitor to a position 1 / 2W of the width direction y connecting the first and second side surfaces. Cases where cracks were confirmed to have penetrated into the interior of the multilayer body were counted as poor mechanical strength.

[0234] (f) Results

[0235] Table 1 shows the results of confirming the presence of migration by a wet load test and the presence of cracks inside the laminate by a flexural strength test for each sample. Note that the samples marked with an * in the table are outside the scope of the present invention.

[0236] [Table 1]

[0237]

[0238] According to Table 1, mechanical strength failure occurred in 8 out of 10 samples of Sample No. 1 and 5 out of 10 samples of Sample No. 2, respectively. This is considered to be because the compressive stress of the Ni plating layer in these samples was less than -150 MPa, and thus the clamping stress on the laminated body became stronger, causing cracks to enter the interior of the laminated body under the action of external stress in the flexural strength test.

[0239] In addition, in samples No. 12 to No. 14, defects due to ion migration occurred in 20 out of 36, 29 out of 36, and 33 out of 36, respectively. This is believed to be because the tensile stress of the Ni plating layer in these samples was greater than 50 MPa, causing the ends of the Ni plating layer to rise, resulting in a state where the surface of the laminate was floating. This created a gap between the laminate and the end of the Ni plating layer, forming a precipitation path for Ag and causing ion migration.

[0240] On the other hand, in samples No. 3 to No. 11, the stress of the Ni plating layer was greater than -150 MPa and less than 50 MPa. Therefore, for each sample, the number of ion migrations was less than 2 in 36, and the number of mechanical strength defects was less than 1 in 10, resulting in good results.

[0241] In addition, especially in samples No. 3 to No. 8, the stress of the Ni plating layer was greater than -143 MPa and less than -51 MPa. Therefore, for each sample, the number of ion migrations was 0 in 36, and the number of mechanical strength defects was 0 in 10, resulting in better results.

[0242] The above results demonstrate that, according to the present invention, by setting the stress of the Ni plating layer disposed on the conductive resin layer to between -150 MPa and 50 MPa, the Ni plating layer can reliably contact the laminate, sealing the gap between the laminate and the Ni plating layer. This maintains the effect of suppressing crack formation in the laminate, blocks Ag precipitation pathways, and suppresses ion migration.

[0243] Furthermore, it is found that by setting the stress of the Ni plating layer to -143 MPa or more and -51 MPa or less, the effects of the present invention can be more pronounced, and the occurrence of cracks and ion migration in the multilayer ceramic capacitor can be further suppressed.

[0244] It should be noted that, as described above, the embodiments of the present invention are disclosed through the above description, but the present invention is not limited thereto.

[0245] That is, various changes in mechanism, shape, material, number, position, arrangement, etc. can be added to the above-described embodiment without departing from the technical concept and purpose of the present invention, and these changes are included in the present invention.

Claims

1. A laminated ceramic electronic component comprising: A laminate comprising a plurality of laminated ceramic layers, the laminate having a first main surface and a second main surface opposing each other in a height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction and the width direction; a first internal electrode layer disposed on the plurality of ceramic layers and exposed at the first end surface; a second internal electrode layer disposed on the plurality of ceramic layers and exposed at the second end surface; a first external electrode electrically connected to the first internal electrode layer, disposed on the first end surface, a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface; as well as a second external electrode electrically connected to the second internal electrode layer, and arranged on the second end surface, a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface; in, The first external electrode and the second external electrode include a base electrode layer including a metal component, a conductive resin layer including a thermosetting resin and a metal component and disposed on the base electrode layer, and a Ni plating layer disposed on the conductive resin layer. A stress of -143 MPa to -28 MPa is applied to the Ni plating layer, and an end portion of the Ni plating layer is in direct contact with the laminate. When stress is represented by a negative magnitude, it indicates compressive stress in the direction from the Ni plating layer toward the laminated body.

2. The multilayer ceramic electronic component according to claim 1, wherein The stress is greater than or equal to -143 MPa and less than or equal to -51 MPa.

3. The multilayer ceramic electronic component according to claim 1 or 2, wherein The metal component included in the conductive resin layer includes Ag.

4. The multilayer ceramic electronic component according to claim 1 or 2, wherein A Sn plating layer is disposed on the Ni plating layer.

5. The multilayer ceramic electronic component according to claim 1 or 2, wherein The base electrode layer includes a glass component or a ceramic component.

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