Method for preparing pn junction of solar cell and solar cell

Abstract

The application provides a PN junction preparation method of a solar cell and the solar cell, and relates to the technical field of solar photovoltaics. The method is applied to a textured surface of a silicon wafer, and comprises the following steps: first diffusion of a dopant on the textured surface, wherein the dopant is different from the conductive type of the silicon wafer; oxidation of the textured surface after the first diffusion to obtain an oxide layer; second diffusion of the dopant on the oxide layer, so that the dopant remains in the oxide layer; and pushing the diffused dopant in the oxide layer, so that in the two diffusion processes on the textured surface of the silicon wafer, more dopant enters the silicon wafer from the top of the peak in the first diffusion, and less dopant enters the silicon wafer from the bottom of the valley, and the second diffusion is opposite, so that the total amount of the dopant entering different positions of the silicon wafer is relatively average, and the junction depth uniformity of the PN junction of the silicon wafer is effectively ensured.

Description

Technical Field

[0001] This invention relates to the field of solar photovoltaic technology, and in particular to a method for preparing a PN junction for a solar cell and the solar cell itself. Background Technology

[0002] In the solar photovoltaic industry, in order to reduce reflection loss on the front surface of the cell and improve light absorption, a common practice is to texture the flat surface to form a light-trapping structure, so that the incident light is reflected multiple times on the front surface to reduce reflection loss and increase light absorption.

[0003] However, textured surfaces are uneven, exhibiting differences in size and height. For example, in a pyramidal textured surface, there is a height difference between the apex and the valley, and there are also size differences between different pyramids. When fabricating PN junctions on textured surfaces, the tensile stress at the apex promotes dopant diffusion, while the compressive stress at the valley hinders it. This results in higher dopant content, deeper junction depth, and lower sheet resistance at the apex, while lower dopant content, shallower junction depth, and higher sheet resistance at the valley. Furthermore, due to the varying sizes of the pyramids and the difference in doping levels between the apex and valley, the PN junctions on textured surfaces are thicker at the apex and thinner at the valley, resulting in poor uniformity. This leads to significant differences in sheet resistance and poor uniformity on the front surface of the battery, affecting its conversion efficiency.

[0004] Currently, the density difference can be reduced by decreasing the pyramid size, thereby improving the uniformity of sheet resistance. However, reducing the pyramid size will reduce the multiple reflection effect of the light trapping structure on the incident light, thus causing optical loss. Summary of the Invention

[0005] This invention provides a method for preparing a PN junction for a solar cell and a solar cell, aiming to ensure the PN junction depth and surface doping uniformity of the textured surface of the silicon wafer.

[0006] In a first aspect, embodiments of the present invention provide a method for fabricating a PN junction in a solar cell, the method being applied to a textured surface of a silicon wafer, the method comprising:

[0007] A first diffusion is performed on the textured surface of the silicon wafer using a dopant, wherein the dopant has a different conductivity type than the silicon wafer;

[0008] Oxidize the textured surface after the first diffusion to obtain an oxide layer;

[0009] The dopant is used to perform a second diffusion on the oxide layer, and the diffusion time of the second diffusion is longer than that of the first diffusion.

[0010] The dopant diffused in the oxide layer is advanced.

[0011] Optionally, the diffusion time of the first diffusion is less than or equal to 120 seconds.

[0012] Optionally, the oxidation time is less than or equal to 180 seconds.

[0013] Optionally, the diffusion time of the second diffusion is less than or equal to 180 seconds.

[0014] Optionally, the propulsion temperature is greater than the diffusion temperature of the first diffusion, the oxidation temperature of the oxidation, and the diffusion temperature of the second diffusion.

[0015] Optionally, the diffusion temperature of the first diffusion is 770℃~800℃;

[0016] The oxidation temperature is 770℃~800℃;

[0017] The diffusion temperature of the second diffusion is 770℃~800℃.

[0018] Optionally, the propulsion temperature is 840℃~870℃.

[0019] Optionally, the silicon wafer is a boron-doped silicon wafer, and the dopant is a phosphorus source.

[0020] In a second aspect, embodiments of the present invention also provide a solar cell comprising a silicon wafer with a textured surface, the silicon wafer comprising a PN junction, the PN junction being prepared by the PN junction preparation method described in the first aspect.

[0021] Optionally, the intra-wafer non-uniformity of the silicon wafer in this solar cell is less than 7%.

[0022] The PN junction fabrication method provided in this embodiment of the invention is applied to the textured surface of a silicon wafer. It includes a first diffusion of a dopant onto the textured surface, wherein the dopant has a different conductivity type than the silicon wafer. At this point, the doping is deeper at the peaks of the textured surface and shallower at the valleys. The textured surface after the first diffusion is then oxidized to obtain an oxide layer. At this point, the oxide layer is thicker at the peaks due to the deeper doping and faster oxidation rate, while the oxide layer is thinner at the valleys due to the shallower doping and slower oxidation rate. A second diffusion of the dopant is then performed on the oxide layer, causing the dopant to diffuse across the surface. In the oxide layer, the dopant diffused in the oxide layer is advanced. Because the oxide layer is thicker at the top, the advancement rate is slower, resulting in less dopant re-entering the silicon wafer at the top. At the bottom, the oxide layer is thinner, the advancement rate is faster, resulting in more dopant re-entering the silicon wafer at the bottom. Thus, in the two diffusions on the textured surface of the silicon wafer, the first diffusion has more dopant entering the silicon wafer from the top and less dopant entering from the bottom. The second diffusion is the opposite, making the total amount of dopant entering at different positions of the silicon wafer more even, effectively ensuring the junction depth of the PN junction and the uniformity of surface doping. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This invention illustrates a method for preparing a PN junction in a solar cell according to an embodiment of the present invention;

[0025] Figure 2 This is a cross-sectional schematic diagram of a first-diffusion-processed textured surface of a silicon wafer provided in an embodiment of the present invention;

[0026] Figure 3 This is a cross-sectional schematic diagram of an oxidized textured surface of a silicon wafer provided in an embodiment of the present invention;

[0027] Figure 4 This is a cross-sectional schematic diagram of a test silicon wafer provided in an embodiment of the present invention;

[0028] Figure 5 This is a cross-sectional schematic diagram of a comparative silicon wafer provided in an embodiment of the present invention;

[0029] Figure 6 This is a schematic diagram of an ECV test location provided in an embodiment of the present invention;

[0030] Figure 7This is a schematic diagram of an ECV test curve for a silicon wafer provided in an embodiment of the present invention;

[0031] Figure 8 This is a schematic diagram of the ECV test curve of a comparative silicon wafer provided in an embodiment of the present invention. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] Reference Figure 1 , Figure 1 This invention illustrates a method for fabricating a PN junction in a solar cell, applicable to the textured surface of a silicon wafer. The method includes:

[0034] Step 101: A first diffusion is performed on the textured surface of the silicon wafer using a dopant, wherein the dopant has a different conductivity type than the silicon wafer.

[0035] In this embodiment of the invention, the textured surface of the silicon wafer can be a pyramidal textured surface or other textured structures with periodic protrusions and depressions. Texturing processes such as acid-base texturing, plasma texturing, metal ion catalytic texturing, and nanoimprint texturing create peak-valley structures of varying heights on the silicon wafer surface. The valley bottoms exhibit compressive stress, which hinders dopant diffusion. Therefore, during diffusion junction formation, this results in higher dopant deposition, deeper junctions, and lower sheet resistance at the peaks, while the opposite occurs at the valley bottoms. Based on this, the textured surface described in this embodiment can be a textured surface formed using existing texturing processes. When performing the first diffusion of dopant on the textured surface of the silicon wafer, dopant with a different conductivity type than the silicon wafer can be used to form a PN junction within the silicon wafer.

[0036] In this embodiment of the invention, the conductivity type of the silicon wafer can be N-type or P-type. The conductivity type of the dopant varies. For example, when the conductivity type of the silicon wafer is N-type, the conductivity type of the dopant is P-type, and when the conductivity type of the silicon wafer is P-type, the conductivity type of the dopant is N-type. This allows a PN junction to be formed on the silicon wafer after the dopant is diffused onto the textured surface of the silicon wafer. The silicon wafer can be a phosphorus-doped silicon wafer, a boron-doped silicon wafer, etc., and the dopant can be a phosphorus source, a boron source, etc.

[0037] In this embodiment of the invention, diffusion can be carried out in a tube furnace. Before the first diffusion, the silicon wafer can be placed in a quartz boat and sent into the furnace tube. The airtightness of the furnace tube is tested, and a negative pressure vacuum is drawn to complete the preparation for the first diffusion.

[0038] Optionally, the silicon wafer is a boron-doped silicon wafer, and the dopant is a phosphorus source.

[0039] In this embodiment of the invention, a PN junction can be prepared by diffusing an N-type dopant onto a P-type silicon wafer. The silicon wafer can be a boron-doped silicon wafer, and the dopant can be a phosphorus source.

[0040] Optionally, the diffusion temperature of the first diffusion is 770℃~800℃.

[0041] Optionally, the diffusion time of the first diffusion is less than or equal to 120 seconds.

[0042] In this embodiment of the invention, the diffusion temperature and diffusion time in the first diffusion process can be controlled according to the requirements of diffusion concentration and depth based on process conditions and application needs. The diffusion temperature can be any temperature between 770℃ and 800℃, such as 770℃, 775℃, 780℃, 790℃, 800℃, etc. The diffusion time should be less than or equal to 120 seconds and greater than 0 seconds, such as 120 seconds, 110 seconds, 100 seconds, etc. By controlling the diffusion time, the diffusion depth can be effectively controlled. The first diffusion on the textured surface results in a deeper pyramid apex and a shallower valley bottom, leading to poor sheet resistance uniformity.

[0043] Step 102: Oxidize the textured surface after the first diffusion to obtain an oxide layer.

[0044] In this embodiment of the invention, an oxide layer can be obtained by oxidizing the textured surface of a silicon wafer after the first diffusion at an oxidation temperature. The oxide layer has a blocking effect on element diffusion, thereby reducing the diffusion rate of elements. On this basis, it partially reduces the non-uniformity of diffusion in different parts of the silicon wafer. This oxide layer can be a silicon dioxide layer. Because the pyramid apex knots on the textured surface are deeper and the valley knots are shallower, the oxidation rate at the apex is faster and the oxide layer thickness is thicker, while the oxidation rate at the valley is slower and the oxide layer thickness is thinner. This results in a stronger blocking effect of the oxide layer at the apex and a weaker blocking effect at the valley.

[0045] Optionally, the oxidation temperature is 770℃~800℃.

[0046] Optionally, the oxidation time is less than or equal to 180 seconds.

[0047] In this embodiment of the invention, the oxidation time of the textured surface should be less than or equal to 180 seconds and greater than 0 seconds, such as 180 seconds, 170 seconds, 160 seconds, etc. By controlling the oxidation time, the thickness of the oxide layer can be effectively controlled. The oxidation temperature of the textured surface can be any temperature between 770℃ and 800℃, such as 770℃, 775℃, 780℃, 790℃, 800℃, etc.

[0048] Step 103: Perform a second diffusion on the oxide layer using the dopant, wherein the diffusion time of the second diffusion is longer than that of the first diffusion.

[0049] In this embodiment of the invention, after obtaining the oxide layer, a second diffusion can be performed on the oxide layer using a dopant at the second diffusion temperature. The second diffusion can be described with reference to the aforementioned description of the first diffusion; to avoid repetition, it will not be repeated here. Furthermore, the second diffusion causes phosphorus atoms to accumulate in the oxide layer formed in step 102. The diffusion time of the second diffusion should be greater than the diffusion time of the first diffusion to control the final depth of the PN junction.

[0050] Optionally, the diffusion temperature of the second diffusion is 770℃~800℃.

[0051] Optionally, the diffusion time of the second diffusion is less than or equal to 180 seconds.

[0052] In this embodiment of the invention, the diffusion time of the second diffusion should be greater than the diffusion time of the first diffusion, provided that it is less than or equal to 180 seconds and greater than 0. For example, when the first diffusion time is 120 seconds, the diffusion time of the second diffusion should be greater than 120 seconds and less than or equal to 180 seconds; when the first diffusion time is 100 seconds, the diffusion time of the second diffusion should be greater than 100 seconds and less than or equal to 180 seconds, etc. The diffusion temperature of the second diffusion can be any temperature between 770℃ and 800℃, such as 770℃, 775℃, 780℃, 790℃, 800℃, etc. This embodiment of the invention does not impose specific limitations on this.

[0053] Step 104: Propel the dopant diffused in the oxide layer.

[0054] In this embodiment of the invention, the dopant accumulated in the oxide layer can be advanced, allowing the dopant to diffuse from the oxide layer into the silicon wafer. Since the oxide layer is thicker at the pyramid apex on the textured surface, the diffusion rate of the dopant is slower during the bonding process, while the oxide layer is thinner at the valley bottom, resulting in a faster diffusion rate of the dopant during the bonding process. This can fill the gap in the first diffusion process, where the bonding depth is deeper at the pyramid apex and shallower at the valley bottom on the textured surface, thereby improving the uniformity of diffusion on the silicon wafer surface.

[0055] Optionally, the propulsion temperature is greater than the diffusion temperature of the first diffusion, the oxidation temperature of the oxidation, and the diffusion temperature of the second diffusion.

[0056] Optionally, the propulsion temperature is 840℃~870℃.

[0057] In this embodiment of the invention, a high-temperature propulsion process can be used to propel the dopants accumulated in the oxide layer. Based on this, the propulsion temperature is higher than the diffusion temperature of the first diffusion, the oxidation temperature of the oxidation, and the diffusion temperature of the second diffusion. The propulsion temperature can be any temperature between 840°C and 870°C, such as 840°C, 845°C, 850°C, 860°C, 870°C, etc. This embodiment of the invention does not impose specific limitations on this.

[0058] In this embodiment of the invention, when preparing a PN junction using a tube furnace, steps such as cooling, backpressure, and unloading can be performed after junction pushing to obtain a silicon wafer with a PN junction.

[0059] In this embodiment of the invention, test silicon wafers and control silicon wafers were also prepared. The test silicon wafer was prepared using boron-doped silicon, with a phosphorus source as the diffusion source. The surface of the boron-doped silicon wafer was textured. The PN junction in the test silicon wafer was prepared as follows: Figure 1 The PN junction was prepared using the method shown below, and the specific process parameters are shown in Table 1:

[0060] Table 1

[0061]

[0062]

[0063] In Table 1, the preparations for the preparation are carried out in steps 1 to 5, including placing the silicon wafer into a quartz boat and sending it into the furnace tube, and then evacuating the furnace tube, checking for leaks, and heating it.

[0064] In step 6, a phosphorus source is used for power supply, and the textured surface of the silicon wafer is subjected to first diffusion at a temperature of 770℃~800℃ for a diffusion time of less than or equal to 120 seconds.

[0065] Figure 2 This is a cross-sectional schematic diagram of a textured surface of a silicon wafer after first diffusion, provided in an embodiment of the present invention, as shown below. Figure 2 As shown, the phosphorus source diffuses deeper and the knot depth is deeper at the top 201 position, while the phosphorus source diffuses shallower and the knot depth is shallower at the bottom 202 position, resulting in an uneven distribution of knot depth on the textured surface.

[0066] In step 7, the surface after the first diffusion is oxidized. An oxide layer is prepared on the textured surface of the silicon wafer at a temperature of 770°C to 800°C for an oxidation time of less than or equal to 180 seconds.

[0067] Figure 3 This is a cross-sectional schematic diagram of the textured surface of an oxidized silicon wafer provided in an embodiment of the present invention, as shown below. Figure 3 As shown, in Figure 2 Based on this, the textured surface of the silicon wafer is oxidized to form a silicon dioxide (SiO2) layer. Due to different oxidation rates, the silicon dioxide layer at the top 201 position is thicker after oxidation, while the silicon dioxide layer at the bottom 202 position is thinner.

[0068] In step 8, a phosphorus source is used for power supply. At a temperature of 770℃ to 800℃, the oxide layer undergoes a second diffusion. The diffusion time is greater than the diffusion time of the first diffusion and less than or equal to 180 seconds.

[0069] In steps 9 and 10, phosphorus atoms diffused in the oxide layer are advanced at 840°C to 870°C.

[0070] In subsequent steps 11 to 18, processes such as cooling, power supply, propulsion, oxidation, back pressure, and unloading are performed to obtain the test silicon wafer.

[0071] Figure 4 This is a cross-sectional schematic diagram of a test silicon wafer provided in an embodiment of the present invention, as shown below. Figure 4 As shown, in Figure 3 Based on this, a second diffusion process is performed on the silicon dioxide layer, allowing phosphorus atoms to diffuse into the silicon dioxide layer and propel them forward. The propagation rate is slower at the thicker peak 201 position and faster at the thinner valley 202 position. As a result, the junction depth at the valley 202 position increases faster than that at the peak 201 position during the propagation process, resulting in a consistency in junction depth between the peak 201 and valley 202 positions on the final tested silicon wafer surface.

[0072] In contrast, the PN junction in the silicon wafer is prepared using a conventional pre-oxidation process, with specific process parameters shown in Table 2 below:

[0073] Table 2

[0074]

[0075]

[0076] In Table 2, the preparations for the preparation are carried out in steps 1 to 5, including placing the silicon wafer into a quartz boat and sending it into the furnace tube, and then evacuating the furnace tube, checking for leaks, and heating it.

[0077] In step 6, the textured surface of the silicon wafer is oxidized. An oxide layer is prepared on the textured surface of the silicon wafer at a temperature of 770℃~800℃, and the oxidation time is less than or equal to 180 seconds.

[0078] In step 7, a phosphorus source is used to conduct a diffusion process on the textured surface of the silicon wafer at a temperature of 770℃~800℃, with a diffusion time of less than or equal to 200 seconds.

[0079] In step 8, a phosphorus source is used for power supply, and a secondary diffusion is performed on the textured surface of the silicon wafer at a temperature of 770℃~800℃. The diffusion time is greater than the diffusion time of the first diffusion and less than or equal to 390 seconds.

[0080] In steps 9 and 10, phosphorus atoms diffused in the oxide layer are advanced at 840°C to 870°C.

[0081] In subsequent steps 11 to 17, processes such as cooling, power supply, propulsion, oxidation, back pressure, and unloading are performed to obtain a comparison silicon wafer.

[0082] Figure 5 This is a cross-sectional schematic diagram of a comparative silicon wafer provided in an embodiment of the present invention, such as... Figure 5 As shown, a silicon dioxide layer is first prepared by oxidation with a phosphorus source on the textured surface of a boron-doped silicon wafer, and then a PN junction is formed by two power supply cycles and two propulsion cycles. Among them, the junction depth is deeper at the top 301 position of the silicon wafer surface and shallower at the bottom 302 position, and the junction depth uniformity is poor.

[0083] Example 1

[0084] Figure 6 This is a schematic diagram of an ECV (Electrochemical Capacitance-Voltage Profiler) test location provided in an embodiment of the present invention. In this ECV, an electrolyte is used to form a potential barrier to measure the carrier concentration. A forward bias is applied to a P-type semiconductor, or a reverse bias is applied to an N-type semiconductor, and surface etching is performed under illumination to remove the electrolyzed material. By repeating the above "etching-measurement" cycle, and then applying Faraday's law to integrate the etching current, the etching depth can be continuously obtained, thus yielding a measurement curve of carrier concentration versus semiconductor depth. Figure 6 As shown, ECV can be used to test the carrier concentration versus semiconductor depth curves at asymmetric positions A1 and B1 on test silicon wafer 1, and at asymmetric positions A2 and B2 on comparison silicon wafer 2.

[0085] Figure 7 This is a schematic diagram of an ECV test curve for a silicon wafer provided in an embodiment of the present invention, as shown below. Figure 7As shown, the carrier concentration and junction depth variation curves at positions A1 and B1 on the test silicon wafer are consistent, indicating good uniformity of junction depth at different positions on the test silicon wafer. Since the test silicon wafer has a textured surface and the pyramid distribution is random, it can be determined that the doping concentration distribution at the apex and trough of the pyramid structure is relatively uniform. Based on this, the sheet resistance uniformity of the test silicon wafer should be good, and the concentration in the surface area of ​​the test silicon wafer should be more concentrated, which can improve product yield, reduce black spots, and reduce series resistance within a certain range, thereby improving the fill factor and ensuring the conversion efficiency of the solar cell fabricated from the silicon wafer.

[0086] Figure 8 This is a schematic diagram of the ECV test curve of a comparative silicon wafer provided in an embodiment of the present invention, as shown below. Figure 8 As shown, the carrier concentration and junction depth variation curves at positions A2 and B2 on the comparative silicon wafer differ significantly. This indicates that the PN junction depth and concentration vary at different points, and the dopant concentration differs between the apex and valley regions of the textured pyramid. The uniformity of junction depth at different locations on the comparative silicon wafer is poor, confirming that the doping structure differs at different locations. Based on this, the sheet resistance uniformity of the comparative silicon wafer is also poor.

[0087] Furthermore, according to Tables 1 and 2, the diffusion times in steps 7 and 8 of the preparation process for the comparative silicon wafer are greater than the diffusion times in steps 6 and 8 of the preparation process for the test silicon wafer. Figure 7 , 8 As shown, the surface doping concentration of the test silicon wafer and the control silicon wafer are similar, meaning that the test silicon wafer, while ensuring doping quality, further reduced the process time and improved the PN junction fabrication efficiency.

[0088] Example 2

[0089] A four-probe sheet resistance meter was used to test the sheet resistance of test silicon wafers and control silicon wafers based on the five-point method. Specifically, the sheet resistance of 50 test silicon wafers and 50 control silicon wafers were tested using the four-probe sheet resistance meter. The average sheet resistance at five points on each test silicon wafer was taken as the test sheet resistance for that wafer. Similarly, the average sheet resistance at five points on each control silicon wafer was taken as the control sheet resistance for that wafer. The inter-wafer non-uniformity of the 50 test silicon wafers was determined by the ratio of the difference between the maximum and minimum sheet resistance values ​​to the sum of the values. The intra-wafer non-uniformity of the 50 test silicon wafers was determined by the ratio of the difference between the maximum and minimum sheet resistance values ​​to the sum of the values ​​at five points. A sheet resistance center value of 170 Ω / sq was used. The concentration of test silicon wafers within the 170 Ω ± 5 range (165 Ω to 175 Ω) was determined by the ratio of the number of wafers with sheet resistance between 165 Ω and 175 Ω to the total number of wafers. Measurements show that the intra-wafer non-uniformity of a typical silicon wafer is 7.77%, while the intra-wafer non-uniformity of the silicon wafer prepared by the PN junction preparation method of the solar cell provided in this application is less than 7%, which can include any value less than 7%, such as 5%, 5.5%, 6%, 6.5%, 7%.

[0090] Specifically, following the process described above, the inter-wafer non-uniformity, intra-wafer non-uniformity, and concentration of the comparison silicon wafers were determined, as shown in Table 3:

[0091] Table 3

[0092] silicon wafers Concentration (170Ω±5) Intra-film inhomogeneity inter-slice inhomogeneity Shear resistance center value Comparison of silicon wafers 80.6％ 7.77％ 4.09％ 170Ω / sq Test silicon wafer 87.2％ 6.54％ 3.62％ 170Ω / sq

[0093] As shown in Table 3, the concentration of the test silicon wafer with PN junctions prepared by the method provided in this application is significantly higher than that of the comparative silicon wafer prepared by conventional processes. Intra-wafer and inter-wafer non-uniformity are reduced. Based on this, it can be determined that the test silicon wafer has better sheet resistance uniformity, higher yield, and better quality compared to the silicon wafer in the comparative document. This application effectively improves the PN junction uniformity at the pyramid apex and valley of the textured surface by preparing an oxide layer between the two source passes, and avoids limitations on the pyramid size, reducing optical losses on the surface. Simultaneously, since the oxide layer reduces the diffusion rate, preparing the oxide layer between the two diffusion passes ensures no oxide layer obstruction during the first diffusion, thereby reducing the impact of the oxide layer on the diffusion rate and ensuring both diffusion uniformity and overall diffusion efficiency.

[0094] The PN junction fabrication method provided in this embodiment of the invention is applied to the textured surface of a silicon wafer. It includes a first diffusion of a dopant onto the textured surface, wherein the dopant has a different conductivity type than the silicon wafer. At this point, the doping is deeper at the peaks and shallower at the valleys. The textured surface after the first diffusion is then oxidized to obtain an oxide layer. Here, the oxide layer is thicker at the peaks due to the deeper doping and faster oxidation rate, while the oxide layer is thinner at the valleys due to the shallower doping and slower oxidation rate. A second diffusion of the dopant is then performed on the oxide layer, further diffusing the dopant. The diffusion occurs within the oxide layer. The dopant diffuses within the oxide layer, and the diffusion rate is slower at the top due to the thicker oxide layer, resulting in less dopant re-entering the silicon wafer at the top. Conversely, the diffusion rate is faster at the bottom due to the thinner oxide layer, resulting in more dopant re-entering the silicon wafer at the bottom. Thus, in the two diffusion processes on the textured surface of the silicon wafer, the first diffusion results in more dopant entering the silicon wafer from the top and less from the bottom. The second diffusion is the opposite, ensuring a more even distribution of dopant at different locations on the silicon wafer and effectively guaranteeing the uniformity of the PN junction depth.

[0095] This invention also provides a solar cell comprising a textured silicon wafer, the silicon wafer including a PN junction, the PN junction being prepared by the following steps:

[0096] A first diffusion is performed on the textured surface of the silicon wafer using a dopant, wherein the dopant has a different conductivity type than the silicon wafer;

[0097] Oxidize the textured surface after the first diffusion to obtain an oxide layer;

[0098] The dopant is used to perform a second diffusion on the oxide layer, and the diffusion time of the second diffusion is longer than that of the first diffusion.

[0099] The dopant diffused in the oxide layer is advanced.

[0100] Optionally, the intra-wafer non-uniformity of the silicon wafer in the solar cell includes 5% to 7%.

[0101] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of this application are not limited to the described order of actions, because according to the embodiments of this application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily essential to the embodiments of this application.

[0102] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0103] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0104] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A method for fabricating a PN junction in a solar cell, the method being applied to the textured surface of a silicon wafer, characterized in that, The method includes: A first diffusion is performed on the textured surface of the silicon wafer using a dopant, wherein the dopant has a different conductivity type than the silicon wafer, the diffusion time of the first diffusion is less than or equal to 120 seconds, and the diffusion temperature of the first diffusion is 770°C to 800°C. The textured surface after the first diffusion is oxidized to obtain an oxide layer, wherein the oxidation time is less than or equal to 180 seconds and the oxidation temperature is 770℃~800℃. The dopant is used to perform a second diffusion on the oxide layer. The diffusion time of the second diffusion is greater than that of the first diffusion. The diffusion time of the second diffusion is less than or equal to 180 seconds. The diffusion temperature of the second diffusion is 770℃~800℃. The dopant diffused in the oxide layer is advanced.

2. The method according to claim 1, characterized in that, The propulsion temperature is greater than the diffusion temperature of the first diffusion, the oxidation temperature of the oxidation, and the diffusion temperature of the second diffusion.

3. The method according to claim 2, characterized in that, The propulsion temperature is 840℃~870℃.

4. The method according to claim 1, characterized in that, The silicon wafer is a boron-doped silicon wafer, and the dopant is a phosphorus source.

5. A solar cell, characterized in that, The solar cell comprises a textured silicon wafer, the silicon wafer comprising a PN junction, the PN junction being prepared by the following steps: A first diffusion is performed on the textured surface of the silicon wafer using a dopant, wherein the dopant has a different conductivity type than the silicon wafer, the diffusion time of the first diffusion is less than or equal to 120 seconds, and the diffusion temperature of the first diffusion is 770°C to 800°C. The textured surface after the first diffusion is oxidized to obtain an oxide layer, wherein the oxidation time is less than or equal to 180 seconds and the oxidation temperature is 770℃~800℃. The dopant is used to perform a second diffusion on the oxide layer. The diffusion time of the second diffusion is greater than that of the first diffusion. The diffusion time of the second diffusion is less than or equal to 180 seconds. The diffusion temperature of the second diffusion is 770℃~800℃. The dopant diffused in the oxide layer is advanced.

6. The solar cell according to claim 5, characterized in that, The intra-wafer non-uniformity of the silicon wafer in the solar cell is less than 7%.

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