Chip package structure and method of manufacturing the same

Abstract

The application discloses a chip packaging structure and a preparation method thereof, and belongs to the technical field of chip packaging. The method comprises the following steps: packaging a first chip; manufacturing a first rewiring part; packaging a second chip, and connecting the first surface electrode of the second chip and the first surface electrode of the first chip through the first rewiring part; manufacturing a second rewiring part, and connecting the second surface electrode of the first chip or the second surface electrode of the second chip and a bonding pad through the second rewiring part; and manufacturing a third rewiring part, and connecting the first surface electrode of the first chip and the first surface electrode of the second chip and a bonding pad through the first rewiring part and the third rewiring part. According to the method, the interconnection packaging of at least two chips can be realized without the help of a lead frame, and the volume of the packaging structure is greatly reduced. The same electrodes of the two chips arranged in a stack are connected with the bonding pad through the rewiring parts, the electrodes of the chips are interconnected through the rewiring parts, and the packaging parasitic resistance can be reduced.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and in particular to a chip packaging structure and its fabrication method. Background Technology

[0002] Traditional dual-chip packages are planar structures, typically placing two chips parallel to each other on a lead frame. Electrical interconnection between the chips is achieved through the lead frame (the front of the chip is connected to the pins of the lead frame via wire bonding), and then the interconnection is achieved through wire bonding. The final product formed by this packaging structure generally cannot be very thin (including the lead frame thickness) and has a large package size.

[0003] To further reduce the package size of chips and increase the power density of products, existing technologies have proposed a stacked chip package structure based on lead frame design, which involves stacking chip one and chip two and then packaging them. This package structure reduces the package size and increases the integration to a certain extent. However, it still requires the use of lead frames, so its performance in reducing package size is very limited. Summary of the Invention

[0004] The purpose of this invention is to overcome the problems of the prior art and provide a chip packaging structure and its fabrication method.

[0005] The objective of this invention is achieved through the following technical solution: a method for fabricating a chip packaging structure, comprising:

[0006] The first chip is packaged to obtain the first molding layer;

[0007] Fabricate the first wiring component, and connect the first wiring component to the first surface electrode of the first chip;

[0008] A second chip is packaged to obtain a second molding layer stacked on the first molding layer. The first surface electrode of the second chip is connected to the first surface electrode of the first chip via a first rewiring component. The first surface electrode of the first chip and the first surface electrode of the second chip are the same electrode.

[0009] A second rewiring component is fabricated, wherein the second side electrode of the first chip or the second side electrode of the second chip is connected to the pad via the second rewiring component; when the second side electrode of the first chip is connected to the pad via the second rewiring component, the second side electrode of the second chip is connected to the pad; when the second side electrode of the second chip is connected to the pad via the second rewiring component, the second side electrode of the first chip is connected to the pad.

[0010] A third wiring component is fabricated, and the first electrode of the first chip and the first electrode of the second chip are connected to the pads through the first wiring component and the third wiring component.

[0011] In one example, when the first chip and the second chip are configured in the same direction, the method includes the following steps:

[0012] The first chip is attached to the carrier board, and the first chip is encapsulated to obtain the first encapsulation layer. A first wiring layer is fabricated on the first encapsulation layer, and a third encapsulation layer is fabricated on the first wiring layer.

[0013] After removing the carrier board, a second wiring layer is fabricated, and a first dielectric layer is deposited.

[0014] A third inner wiring layer is fabricated within the first dielectric layer, connecting the third inner wiring layer to the second wiring layer, and a third outer wiring layer is fabricated that penetrates the first molding layer and the first dielectric layer.

[0015] A fourth wiring layer is fabricated on the first dielectric layer. The fourth wiring layer is connected to the third outer wiring layer. The first wiring layer, the third outer wiring layer, and the fourth wiring layer constitute the first rewiring component.

[0016] A second chip is attached to the fourth wiring layer, so that the first electrode of the second chip is connected to the fourth wiring layer, and the second chip is encapsulated to obtain a second encapsulation layer.

[0017] A fifth inner wiring layer and a fifth outer wiring layer are fabricated that penetrate the second molding layer. The fifth inner wiring layer is connected to the third inner wiring layer. The second wiring layer, the third inner rewiring layer, and the fifth inner wiring layer form a second rewiring component. The fifth outer wiring layer is a third rewiring component and is connected to the third outer wiring layer.

[0018] Pads are fabricated on the second molding layer, and the fifth inner wiring layer, the fifth outer wiring layer, and the second side electrode of the second chip are connected to the pads.

[0019] In one example, the process of molding the second chip to obtain a second molding layer is replaced by:

[0020] The fourth wiring layer and the second chip are encapsulated to obtain the second encapsulation layer.

[0021] In one example, the process of creating pads on the second molding layer further includes:

[0022] A second dielectric layer is fabricated on the second molding layer;

[0023] A hole is made in the second dielectric layer until the fifth inner wiring layer, the fifth outer wiring layer, and the second surface electrode of the second chip are exposed, thus obtaining several through holes;

[0024] Fill the through-hole with lead metal;

[0025] Pads are fabricated on the second dielectric layer, and the fifth inner wiring layer, the fifth outer wiring layer, and the second surface electrode of the second chip are connected to the pads via lead metal.

[0026] In one example, when the first chip and the second chip are reversed, the method includes the following steps:

[0027] The first chip is attached to the carrier board, and the first chip is encapsulated to obtain the first encapsulation layer. A groove is made in the first encapsulation layer to expose the first electrode of the first chip.

[0028] A first wiring metal layer is fabricated in the groove, and the first wiring metal layer is the first rewiring component;

[0029] A second chip is fabricated on the first wiring metal layer, and the first wiring metal layer is connected to the first surface electrode of the second chip;

[0030] The second chip is encapsulated to obtain a second encapsulation layer, and a second wiring metal layer is fabricated on the second encapsulation layer so that the first electrode of the second chip is connected to the second wiring metal layer. Then, a fourth encapsulation layer is fabricated and the carrier board is removed.

[0031] Flip the current packaging structure and create a third wiring metal layer that penetrates the first molding layer and the second molding layer. Connect the third wiring metal layer with the second wiring metal layer. The second wiring metal layer and the third wiring metal layer form a second wiring component.

[0032] A fourth wiring metal layer is fabricated within the first molding layer, and the fourth wiring metal layer is connected to the first wiring metal layer. The fourth wiring metal layer is a third wiring component.

[0033] A third dielectric layer is fabricated on the first molding layer, and pads are fabricated on the third dielectric layer. The third wiring metal layer, the fourth wiring metal layer, and the second side electrode of the first chip are connected to the pads.

[0034] In one example, the third wiring metal layer includes interconnected third wiring metal sublayer A and third wiring metal sublayer B, with third wiring metal sublayer A penetrating the second molding layer and third wiring metal sublayer B penetrating the first molding layer.

[0035] In one example, the process of molding the second chip to obtain a second molding layer is replaced by:

[0036] The second chip and the first wiring metal layer are encapsulated to obtain the second encapsulation layer.

[0037] In one example, the fabrication of pads on the third dielectric layer further includes:

[0038] A third dielectric layer is fabricated on the first molding layer;

[0039] A hole is made in the third dielectric layer until the third wiring metal layer, the fourth wiring metal layer, and the second surface electrode of the first chip are exposed, thus obtaining several through holes;

[0040] Fill the through-hole with lead metal;

[0041] Pads are fabricated on the third dielectric layer, and the third wiring metal layer, the fourth wiring metal layer, and the second electrode of the first chip are connected to the pads via lead metal.

[0042] It should be further noted that the technical features corresponding to the above examples can be combined or replaced to form new technical solutions.

[0043] The present invention also includes a chip packaging structure, comprising a packaging substructure, which is obtained by the preparation method formed according to any or more of the above examples, comprising a first molding compound and a second molding compound stacked together, wherein a first chip is packaged in the first molding compound and a second chip is packaged in the second molding compound.

[0044] The second electrode of the first chip or the second electrode of the second chip is connected to the pad via a second rewiring component; when the second electrode of the first chip is connected to the pad via the second rewiring component, the second electrode of the second chip is connected to the pad; when the second electrode of the second chip is connected to the pad via the second rewiring component, the second electrode of the first chip is connected to the pad.

[0045] The first electrode of the first chip and the first electrode of the second chip are connected to the pads via the first rewiring component and the third rewiring component.

[0046] In one example, the packaging structure includes several packaging substructures, which are horizontally spliced ​​together to obtain a multi-chip packaging structure.

[0047] Compared with the prior art, the beneficial effects of the present invention are:

[0048] The method of this invention can achieve interconnection packaging of at least two chips without the need for a lead frame. On the one hand, it breaks through the limitation of the lead frame area on the number of chip interconnections, and on the other hand, it greatly reduces the volume of the package structure. In addition, the same electrodes (such as the back electrode) of the two stacked chips are connected to the pads after being connected by a redistribution component, that is, the chip electrode interconnection is achieved through the redistribution component, which can reduce the parasitic resistance of the package. Furthermore, the other electrode of the two chips is also led out and connected to the pads through the redistribution component, without the need to introduce additional leads to bond the chips, further reducing the parasitic resistance of the chip interconnection. Attached Figure Description

[0049] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, which are used to provide a further understanding of the present application and constitute a part of the present application. The same reference numerals are used in these drawings to denote the same or similar parts. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application.

[0050] Figure 1 This is a flowchart of a method in an example of the present invention;

[0051] Figure 2 This is a schematic diagram of the encapsulation substructure prepared in step S1” of the first preferred example of the present invention;

[0052] Figure 3 This is a schematic diagram of the encapsulation substructure prepared in step S2” of the first preferred example of the present invention;

[0053] Figure 4 This is a schematic diagram of the encapsulation substructure prepared in step S3” of the first preferred example of the present invention;

[0054] Figure 5 This is a schematic diagram of the encapsulation substructure prepared in step S4” of the first preferred example of the present invention;

[0055] Figure 6 This is a schematic diagram of the encapsulation substructure prepared in step S5” of the first preferred example of the present invention;

[0056] Figure 7 This is a top view of the encapsulation substructure prepared in step S5” of the first preferred example of the present invention;

[0057] Figure 8 This is a schematic diagram of the encapsulation substructure prepared in step S6” of the first preferred example of the present invention;

[0058] Figure 9 This is a schematic diagram of the encapsulation substructure prepared in step S7” of the first preferred example of the present invention;

[0059] Figure 10 This is a schematic diagram of the encapsulation substructure prepared in step S8” of the first preferred example of the present invention;

[0060] Figure 11 This is a schematic diagram of the encapsulation substructure prepared in step S9” of the first preferred example of the present invention;

[0061] Figure 12 This is a schematic diagram of the encapsulation substructure prepared in step S10” of the first preferred example of the present invention;

[0062] Figure 13 A method flowchart from another example of the present invention;

[0063] Figure 14 This is a schematic diagram of the encapsulation substructure prepared in step S1”' of the second preferred example of the present invention;

[0064] Figure 15 This is a schematic diagram of the encapsulation substructure prepared in step S2”' of the second preferred example of the present invention;

[0065] Figure 16 This is a schematic diagram of the encapsulation substructure prepared in step S3”' of the second preferred example of the present invention;

[0066] Figure 17 This is a schematic diagram of the encapsulation substructure prepared in step S4”' of the second preferred example of the present invention;

[0067] Figure 18 This is a schematic diagram of the encapsulation substructure prepared in step S5”' of the second preferred example of the present invention;

[0068] Figure 19 This is a schematic diagram of the encapsulation substructure prepared in step S6”' of the second preferred example of the present invention;

[0069] Figure 20 This is a schematic diagram of the encapsulation substructure prepared in step S7”' of the second preferred example of the present invention;

[0070] Figure 21 This is a schematic diagram of the encapsulation substructure prepared in step S8”' of the second preferred example of the present invention;

[0071] Figure 22 This is a schematic diagram of the encapsulation substructure prepared in step S9”' of the second preferred example of the present invention;

[0072] Figure 23 This is a schematic diagram of the encapsulation substructure prepared in step S10”' of the second preferred example of the present invention;

[0073] Figure 24 This is a schematic diagram of the encapsulation substructure prepared in step S11”', which is a second preferred example of the present invention.

[0074] In the diagram: 1-First chip; 2-Second chip; 3-Carrier board; 4a-First molding compound layer; 4b-Second molding compound layer; 4c-Third molding compound layer; 4d-Fourth molding compound layer; 5-First wiring layer; 6-Second wiring layer; 7a-First dielectric layer; 7b-Second dielectric layer; 8a-Third inner redistribution layer; 8b-Third outer redistribution layer; 9-Fourth wiring layer; 10a-Fifth inner redistribution layer; 10b-Fifth outer redistribution layer; 11-Pad; 12- 13 - Lead metal; 14 - Front electrode; 15 - First inner blind via; 16 - First outer through-hole; 17 - Second inner through-hole; 18 - First wiring metal layer; 19 - Second wiring metal layer; 20 - Third wiring metal layer; 21 - Fourth wiring metal layer; 22 - Fifth wiring metal layer; 23a - Fourth dielectric layer; 23b - Fifth dielectric layer; 24 - Fourth blind via; 25 - Fifth through-hole; 26 - Seventh through-hole; 27 - Eighth through-hole. Detailed Implementation

[0075] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0076] In the description of this invention, it should be noted that the directions or positional relationships indicated by terms such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" are based on the directions or positional relationships shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention. Furthermore, the use of ordinal numbers (e.g., "first and second," "first to fourth," etc.) is for distinguishing objects and is not limited to this order, and should not be construed as indicating or implying relative importance.

[0077] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0078] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0079] In one example, the method for fabricating a chip packaging structure according to the present invention specifically includes the following steps:

[0080] The first chip is packaged to obtain the first molding layer;

[0081] Fabricate the first wiring component, and connect the first wiring component to the first surface electrode of the first chip;

[0082] A second chip is packaged to obtain a second molding layer stacked on the first molding layer. The first side electrode of the second chip is connected to the first side electrode of the first chip via a first rewiring component. The first side electrode of the first chip and the first side electrode of the second chip are the same electrode, that is, both represent the front electrode or the back electrode of the chip. In some embodiments of the present invention, the first side electrode is the back electrode and the second side electrode is the front electrode.

[0083] A second rewiring component is fabricated, wherein the second side electrode of the first chip or the second side electrode of the second chip is connected to the pad via the second rewiring component; when the second side electrode of the first chip is connected to the pad via the second rewiring component, the second side electrode of the second chip is connected to the pad; when the second side electrode of the second chip is connected to the pad via the second rewiring component, the second side electrode of the first chip is connected to the pad.

[0084] A third wiring component is fabricated, and the first electrode of the first chip and the first electrode of the second chip are connected to the pads through the first wiring component and the third wiring component.

[0085] It should be noted that in this example, the steps do not need to be performed in the order described above. To ensure preparation efficiency and reduce the difficulty of the process, some steps can be performed simultaneously (e.g., some redistribution layers in the first redistribution component and some redistribution layers in the second redistribution component can be fabricated at the same time), or the steps can be reversed (e.g., some redistribution layers in the second redistribution component can be fabricated first, and then the second chip can be packaged).

[0086] Specifically, the molding compound material is preferably epoxy resin, which has the characteristics of being lightweight, high-strength, corrosion-resistant, having excellent electrical properties, and shock absorption, and can well meet the chip packaging requirements.

[0087] Furthermore, the redistribution component is a single redistribution layer (RDL) or formed by interconnecting multiple redistribution layers. The redistribution layer is used to change the position of the original chip circuit contact through wafer-level metal wiring and bumping processes, thereby enabling the chip to be suitable for different packaging forms.

[0088] Furthermore, when the first chip and the second chip are oriented in the same direction, i.e., the first chip and the second chip face upwards, in this example, the first chip and the second chip both face upwards. At this time, the first rewiring component includes a horizontal rewiring layer connected to the back electrode of the first chip and the back electrode of the second chip, and a vertical rewiring layer connecting the two horizontal rewiring layers and penetrating the first molding compound. As an option, the vertical rewiring layer can be a "U"-shaped rewiring component with a certain thickness (equal to the thickness of the first molding compound), including horizontal wiring components and vertical wiring components. After the horizontal rewiring layer connected to the back electrode of the second chip extends vertically, it connects with the horizontal wiring component, thereby realizing the interconnection of the back electrodes of the first chip and the second chip. More preferably, in order to improve manufacturing efficiency, the horizontal wiring component in the "U"-shaped rewiring component can reserve a gap according to the width of the horizontal rewiring layer connected to the back electrode of the second chip.

[0089] Furthermore, when the first chip and the second chip are arranged in the same direction, the second rewiring component includes a horizontal wiring layer connected to the front electrode of the first chip and a vertical wiring layer connected to the horizontal wiring layer; the third rewiring component is preferably a single-layer vertical rewiring layer, which can be connected to any wiring layer in the first rewiring component.

[0090] Furthermore, when the first chip and the second chip are reversed, i.e., one chip faces upwards and the other faces downwards, the first rewiring component is preferably a single-layer rewiring layer, directly interconnecting the back electrodes of the first and second chips. Alternatively, it can be a multi-layered rewiring layer, interconnecting the back electrodes of the first and second chips through multiple layers. The second rewiring component preferably includes a horizontal rewiring layer and a vertical rewiring layer. The horizontal rewiring layer is connected to the front electrode of the second chip, and the vertical rewiring layer leads out the front electrode of the second chip. Optionally, the vertical rewiring layer can be a multi-layered vertical rewiring sublayer. The third rewiring component is a vertical rewiring layer that penetrates the first molding layer and is connected to the first rewiring component.

[0091] In one example, when the first chip and the second chip are configured in the same direction, such as... Figure 1 As shown, the method for fabricating the encapsulation structure includes the following steps:

[0092] S1: The second side of the first chip is attached to a carrier board, and the first chip is encapsulated to obtain a first encapsulation layer; wherein, the carrier board 1 includes, but is not limited to, a steel plate, a glass plate, etc.; optionally, the first chip can be attached to the carrier board using temporary bonding adhesive. Preferably, the first encapsulation layer is ground smooth to expose the chip electrodes before the first wiring layer is fabricated.

[0093] S2: A first wiring layer is fabricated on the first molding compound layer. The first wiring layer is interconnected with the back side of the first chip. After removing the carrier board, a second wiring layer is fabricated, and a first dielectric layer is deposited. In this step, the carrier board is removed directly by removing the temporary bonding adhesive, such as by heating. Preferably, after the first wiring layer is fabricated, a third molding compound layer is fabricated on the first wiring layer, and the first wiring layer is embedded inside the molding compound layer.

[0094] S3: Fabricate a third inner wiring layer within the first dielectric layer, connect the third inner wiring layer to the second wiring layer, and fabricate a third outer wiring layer that penetrates the first molding layer and the first dielectric layer.

[0095] S4: A fourth wiring layer is fabricated on the first dielectric layer. The fourth wiring layer is connected to the third outer wiring layer. The first wiring layer, the third outer wiring layer, and the fourth wiring layer constitute the first rewiring component.

[0096] S5: Attach the second chip to the fourth wiring layer, connect the first electrode of the second chip to the fourth wiring layer, and encapsulate the second chip to obtain the second encapsulation layer;

[0097] S6: Fabricate a fifth inner wiring layer and a fifth outer wiring layer that penetrate the second molding layer. The fifth inner wiring layer is connected to the third inner wiring layer. The second wiring layer, the third inner rewiring layer, and the fifth inner wiring layer form a second rewiring component. The fifth outer wiring layer is a third rewiring component and is connected to the third outer wiring layer.

[0098] S7: Pads are fabricated on the second molding layer, and the fifth inner wiring layer, the fifth outer wiring layer, and the second side electrode of the second chip are connected to the pads.

[0099] In this example, the thicknesses of the third inner rewiring layer, the third outer rewiring layer, the fifth inner rewiring layer, and the fifth outer rewiring layer are all less than or equal to the thickness of the molding layer and less than the total height of the two chips, which reduces the difficulty of fabricating the through-hole metal wiring process.

[0100] As an option, when the first chip and the second chip are arranged in the same direction, the method for fabricating the package structure may further include the following steps:

[0101] S1': The first side of the first chip is attached to the carrier board, and the first chip is encapsulated to obtain the first encapsulation layer;

[0102] S2': Deposition of the first dielectric layer;

[0103] S3': Fabricate the third outer wiring layer that runs through the first molding layer and the first dielectric layer;

[0104] S4': A fourth routing layer is fabricated on the first dielectric layer, and the fourth routing layer is connected to the third outer routing layer.

[0105] S5': Remove the carrier board, flip the current packaging structure, prepare the first wiring layer on the first molding layer, connect the first wiring layer with the third outer wiring layer, and the first wiring layer, the third outer wiring layer and the fourth wiring layer constitute the first rewiring component;

[0106] S6': Attach the second chip to the fourth wiring layer, connect the first electrode of the second chip to the fourth wiring layer, and encapsulate the second chip to obtain a second encapsulation layer, wherein the second encapsulation layer is smaller than the first encapsulation layer to expose the outside of the second dielectric layer;

[0107] S7': A second wiring layer is fabricated within the first dielectric layer. At this time, the second chip is not aligned with the first chip, and the positions corresponding to the front electrodes of the first dielectric layer and the first chip are not blocked by the second molding layer.

[0108] S8': A third inner wiring layer is fabricated within the first dielectric layer (in a position not obscured by the second molding layer), so that the third inner wiring layer is connected to the second wiring layer;

[0109] S9': Fabricate a fifth inner wiring layer that penetrates the second molding layer. The fifth inner wiring layer is connected to the third inner wiring layer. The second wiring layer, the third inner rewiring layer, and the fifth inner wiring layer form a second rewiring component.

[0110] S10': Fabricate the fifth outer wiring layer that penetrates the second molding layer. The fifth outer wiring layer is a third wiring component and is connected to the third outer wiring layer.

[0111] S11': Pads are fabricated on the second molding layer, and the fifth inner wiring layer, the fifth outer wiring layer, and the second side electrode of the second chip are connected to the pads.

[0112] In one example, creating the third inner redistribution layer includes the following sub-steps:

[0113] S31: Make an opening in the first dielectric layer until the second wiring layer is exposed to obtain the first inner blind via; in this invention, the opening can be achieved by laser process, or by etching.

[0114] S32: A third inner redistribution layer is fabricated within the first inner blind via, that is, a metal layer is filled within the first inner blind via as the third inner redistribution layer, so that the third inner redistribution layer is connected to the second redistribution layer.

[0115] In one example, creating the third outer redistribution layer includes:

[0116] S33: Create a first outer via through the first molding layer and the first dielectric layer to expose the first wiring layer;

[0117] S34: A third outer redistribution layer is fabricated within the first outer through-hole, that is, a metal layer is filled within the first outer through-hole as the third outer redistribution layer, so that the third outer redistribution layer is connected to the first wiring layer.

[0118] In one example, creating the fifth inner redistribution layer includes:

[0119] S61: Make an opening in the second molding layer until the third inner redistribution layer is exposed to obtain the second inner through-hole;

[0120] S62: A fifth inner redistribution layer is fabricated within the second inner through-hole, that is, a metal layer is filled within the second inner through-hole as the fifth inner redistribution layer, so that the fifth inner redistribution layer is connected to the third inner redistribution layer.

[0121] In one example, creating the fifth outer redistribution layer includes:

[0122] S63: Make an opening in the second molding layer until the third outer redistribution layer is exposed to obtain the second outer through-hole;

[0123] S64: A fifth outer redistribution layer is fabricated within the second outer via, that is, a metal layer is filled within the second outer via as the fifth outer redistribution layer, so that the fifth outer redistribution layer is connected to the third outer redistribution layer.

[0124] In one example, when fabricating a third inner redistribution layer within a first inner blind via or a third outer redistribution layer within a first outer via, the following sub-steps are included:

[0125] A first seed layer, preferably a Ti / Cu material, is sputtered onto the surface of the current packaging structure.

[0126] The first seed layer is masked using a first photoresist to expose the first seed layer corresponding to the location of the first inner blind hole or the first outer through hole;

[0127] Electroplating is performed on the first seed layer corresponding to the first inner blind hole or the first outer through hole, preferably Cu plating.

[0128] Remove the first photoresist and the excess first seed layer outside the location of the first inner blind hole or the first outer through hole to obtain a third inner redistribution layer connected to the second wiring layer, or obtain a third outer redistribution layer that penetrates the first molding layer and the first dielectric layer; wherein, preferably, wet etching is used to remove the first photoresist.

[0129] When fabricating a fifth inner redistribution layer within a second inner via or a fifth outer redistribution layer within a second outer via, the following sub-steps are included:

[0130] A second seed layer, preferably a Ti / Cu material, is sputtered onto the surface of the current packaging structure.

[0131] The second seed layer is masked using a second photoresist to expose the second seed layer corresponding to the location of the second inner or outer via.

[0132] Electroplating is performed on the second seed layer corresponding to the location of the second inner through hole or the second outer through hole, preferably Cu plating.

[0133] Remove the second photoresist and the excess second seed layer outside the location of the second inner via or the second outer via to obtain a fifth inner redistribution layer or a fifth outer redistribution layer that penetrates the second molding layer; wherein, preferably, wet etching is used to remove the second photoresist.

[0134] In one example, the second encapsulation layer obtained by molding the second chip is replaced by:

[0135] The fourth wiring layer and the second chip are encapsulated to obtain the second encapsulation layer, thereby reducing the volume of the entire package structure and improving the reliability of the package structure.

[0136] In one example, a second dielectric layer is fabricated on the second molding compound, that is, the second dielectric layer is located between the second molding compound and the pads, and the pads are fabricated on the second dielectric layer. The second dielectric layer can be any one of epoxy resin, PBO, Al2O3, SiO2, or SiNx.

[0137] Furthermore, before fabricating the solder pads on the second molding layer, the following steps are also included:

[0138] Make openings in the second dielectric layer until the fifth inner wiring layer, the fifth outer wiring layer, and the second surface electrode of the second chip are exposed.

[0139] The third through hole is filled with lead metal, which is a (alloy) metal block formed by any one or more of the following materials: Au, Ti, Al, Ni, and Cu.

[0140] Pads are fabricated on the second dielectric layer, and the fifth inner wiring layer, the fifth outer wiring layer, and the second surface electrode of the second chip are connected to the pads via lead metal.

[0141] Combining the above examples, a first preferred example of the method for fabricating the package (sub) structure when the first chip and the second chip are arranged in the same direction is obtained, including the following steps:

[0142] S1”: such as Figure 2 As shown, the front side of the first chip 1 is pasted onto the carrier board 3, and the first chip 1 is encapsulated to obtain a first encapsulation layer 4a. Then, a first wiring layer 5 is fabricated on the first encapsulation layer 4a, and a third encapsulation layer 4c is fabricated on the first wiring layer 5. The front side of the chip is the side with the circuit pattern etched on it, and the other side is the back side of the chip. Furthermore, the first chip 1 can be pasted onto the carrier board 3 using temporary bonding adhesive.

[0143] S2”: such as Figure 3 As shown, after removing the carrier board 3, a second wiring layer 6 is fabricated, and a first dielectric layer 7a is deposited; in this step, the carrier board 3 is removed directly by removing the temporary bonding adhesive.

[0144] S3”: such as Figure 4 As shown, a hole is made in the first dielectric layer 7a (corresponding to the second wiring layer 6) until the second wiring layer 6 is exposed, thus obtaining the first inner blind hole 14; at the same time, holes are made in the first molding layer 4a and the first dielectric layer 7a to expose the first wiring layer 5, thus obtaining the first outer through hole 15 that penetrates the first molding layer 4a and the first dielectric layer 7a.

[0145] S4”: such as Figure 5As shown, a third inner redistribution layer 8a is fabricated in the first inner blind hole 14 so that the third inner redistribution layer is connected to the second redistribution layer 6; at the same time, a third outer redistribution layer 8b is fabricated in the first outer through hole 15 so that the third outer redistribution layer 8b is connected to the first redistribution layer 5.

[0146] S5”: such as Figure 6 As shown, a fourth wiring layer 9 is fabricated on the first dielectric layer 7a, and the fourth wiring layer 9 is interconnected with the "U"-shaped third outer redistribution layer 8b, as shown. Figure 7 As shown;

[0147] S6”: such as Figure 8 As shown, the second chip 2 is attached to the fourth wiring layer 9, so that the back electrode of the second chip 2 is connected to the fourth wiring layer 9, and the second chip 2 and the fourth wiring layer 9 are encapsulated to obtain the second encapsulation layer 4b.

[0148] S7”: such as Figure 9 As shown, an opening is made in the second molding layer 4b (corresponding to the third inner wiring layer and the third outer wiring layer) until the third inner wiring layer and the third outer wiring layer are exposed, resulting in a second inner through hole 16 corresponding to the third inner wiring layer and a second outer through hole 17 corresponding to the third outer wiring layer.

[0149] S8”: such as Figure 10 As shown, a fifth inner redistribution layer 10a is fabricated in the second inner via 16 to connect the fifth inner redistribution layer with the third inner redistribution layer. At this time, the fifth inner redistribution layer is connected to the front electrode 13 (top electrode) of the first chip. At the same time, a fifth outer redistribution layer 10b is fabricated in the second outer via 17 to connect the fifth outer redistribution layer 10b with the third outer redistribution layer 8b. At this time, the fifth outer redistribution layer 10b is connected to the back electrode of the first chip 1 and the back electrode of the second chip 2.

[0150] S9”: such as Figure 11 As shown, a second dielectric layer 7b is deposited on the surface of the second molding layer 4b, and an opening is made in the second dielectric layer 7b to expose the fifth inner redistribution layer 10a, the fifth outer redistribution layer 10b, and the front electrode 13 of the second chip to form lead metal 12. Lead metal 12 is deposited in the through-hole of the second dielectric layer 7b so that the lead metal 12 is connected to the fifth inner redistribution layer 10a, the fifth outer redistribution layer 10b, and the front electrode 13 of the second chip.

[0151] S10”: such as Figure 12As shown, pads 11 are fabricated on the second dielectric layer 7b, and the pads 11 are connected to the fifth inner redistribution layer 10a, the fifth outer redistribution layer 10b, and the front electrode 13 of the second chip, thereby realizing the lead-out of the front electrode 13 and the back electrode of the first chip 1 and the second chip, thus completing the fabrication of the package substructure.

[0152] In one example, when the first chip and the second chip are reversed, such as Figure 13 As shown, the preparation method includes the following steps:

[0153] s1: The second side of the first chip is attached to the carrier board, and the first chip is encapsulated to obtain a first encapsulation layer. A groove is made in the first encapsulation layer to expose the first electrode of the first chip. Preferably, when the first encapsulation layer is grooved, the size of the groove is larger than the size of the first chip.

[0154] s2: A first wiring metal layer is formed in the groove, the first wiring metal layer being a first rewiring component; preferably, the surface of the first wiring metal layer is flush with the surface of the first molding layer;

[0155] s3: Fabricate a second chip on the first wiring metal layer, and connect the first wiring metal layer to the first surface electrode of the second chip; preferably, the first surface of the second chip is soldered on the first wiring metal layer by a soldering method, thereby connecting the first surface electrode of the first chip to the first surface electrode of the second chip.

[0156] s4: The second chip is encapsulated to obtain a second encapsulation layer, and a second wiring metal layer is fabricated on the second encapsulation layer so that the first electrode of the second chip is connected to the second wiring metal layer. Then, a fourth encapsulation layer is fabricated and the carrier board is removed.

[0157] s5: Flip the current package structure (the package structure obtained in steps s1-s4), and make a third wiring metal layer that penetrates the first molding layer and the second molding layer, so that the third wiring metal layer is connected to the second wiring metal layer, and the second wiring metal layer and the third wiring metal layer form a second rewiring component;

[0158] s6: A fourth wiring metal layer is fabricated within the first molding layer, and the fourth wiring metal layer is connected to the first wiring metal layer. The fourth wiring metal layer is a third wiring component.

[0159] s7: A third dielectric layer is fabricated on the first molding layer, and pads are fabricated on the third dielectric layer. The third wiring metal layer, the fourth wiring metal layer, and the second side electrode of the first chip are connected to the pads.

[0160] In one example, when the first chip and the second chip are reversed, the fabrication method may include the following steps:

[0161] s1': The first chip is attached to the carrier board, and the first chip is encapsulated to obtain the first encapsulation layer. A groove is made in the first encapsulation layer to expose the first surface electrode of the first chip. Preferably, when the first encapsulation layer is grooved, the size of the groove is larger than the size of the first chip.

[0162] s2': A first wiring metal layer is formed in the groove, the first wiring metal layer being a first rewiring component; preferably, the surface of the first wiring metal layer is flush with the surface of the first molding layer;

[0163] s3': A second chip is fabricated on the first wiring metal layer, and the first wiring metal layer is connected to the first surface electrode of the second chip; preferably, the first surface of the second chip is soldered on the first wiring metal layer by a soldering method, thereby connecting the first surface electrode of the first chip to the first surface electrode of the second chip.

[0164] s4': The second chip is encapsulated to obtain a second encapsulation layer, and a second wiring metal layer is fabricated on the second encapsulation layer so that the first electrode of the second chip is connected to the second wiring metal layer. Then, a fourth encapsulation layer is fabricated and the carrier board is removed.

[0165] s5': Flip the current package structure (the package structure obtained in steps s1-s4), and make a fourth wiring metal layer inside the first molding layer, so that the fourth wiring metal layer is connected to the first wiring metal layer. The fourth wiring metal layer is the third wiring component.

[0166] s6': Fabricate a third wiring metal layer that penetrates the first molding layer and the second molding layer, and connect the third wiring metal layer with the second wiring metal layer. The second wiring metal layer and the third wiring metal layer form a second rewiring component.

[0167] s7': A third dielectric layer is fabricated on the first molding layer, and pads are fabricated on the third dielectric layer. The third wiring metal layer, the fourth wiring metal layer, and the second side electrode of the first chip are connected to the pads.

[0168] In one example, fabricating a fourth wiring metal layer within a first molding compound includes the following steps:

[0169] s51': Make an opening in the first molding layer until the first wiring metal layer is exposed to obtain the fourth blind via;

[0170] s52': A fourth wiring metal layer is fabricated inside the fourth blind via, that is, a metal layer is filled inside the fourth blind via as the fourth wiring metal layer, so that the fourth wiring metal layer is connected to the first wiring metal layer.

[0171] In one example, fabricating a third wiring metal layer that penetrates the first molding layer and the second molding layer includes the following steps:

[0172] s61': Make openings in the second molding layer and the first molding layer until the second wiring metal layer is exposed, to obtain a fifth through hole that penetrates the second molding layer and the first molding layer;

[0173] s62': Create a third wiring metal layer inside the fifth through hole, that is, fill the fifth through hole with a metal layer as the third wiring metal layer, so that the third wiring metal layer is connected to the second wiring metal layer.

[0174] In one example, when fabricating a fourth wiring metal layer within a fourth blind via or a third wiring metal layer within a fifth through via, the following sub-steps are included:

[0175] A third seed layer, preferably a Ti / Cu material, is sputtered onto the surface of the current packaging structure.

[0176] The third seed layer is masked using a third photoresist to expose the third seed layer corresponding to the location of the fourth blind hole or the fifth through hole;

[0177] Electroplating is performed on the third seed layer corresponding to the fourth blind hole or the fifth through hole, preferably Cu plating;

[0178] Remove the excess third seed layer outside the third photoresist and the fourth blind hole or fifth through hole locations to obtain a fourth wiring metal layer that penetrates the second molding compound layer, or a third wiring metal layer that penetrates the second molding compound layer and the first molding compound layer; wherein, wet etching is preferably used to remove the third photoresist.

[0179] In one example, the third wiring metal layer includes interconnected third wiring metal sublayer A and third wiring metal sublayer B. Third wiring metal sublayer A penetrates the second molding layer, and third wiring metal sublayer B penetrates the first molding layer. This splits the third wiring metal layer into two fabrication layers, greatly reducing the process complexity. Correspondingly, the fabrication method includes the following steps:

[0180] s1”: The first chip is attached to the carrier board, and the first chip is encapsulated to obtain the first encapsulation layer. A groove is made in the first encapsulation layer to expose the first electrode of the first chip. Preferably, when the first encapsulation layer is grooved, the size of the groove is larger than the size of the first chip.

[0181] s2”: A first wiring metal layer is formed in the groove, the first wiring metal layer being a first rewiring component; preferably, the surface of the first wiring metal layer is flush with the surface of the first molding layer;

[0182] s3”: A second chip is fabricated on the first wiring metal layer, and the first wiring metal layer is connected to the first side electrode of the second chip; preferably, the first side of the second chip is soldered on the first wiring metal layer by a soldering method, thereby connecting the first side electrode of the first chip to the first side electrode of the second chip.

[0183] S4”: Fabricate the third wiring metal sublayer B that runs through the first molding layer;

[0184] S5”: The second chip is encapsulated to obtain a second encapsulation layer, and a second wiring metal layer is fabricated on the second encapsulation layer so that the first electrode of the second chip is connected to the second wiring metal layer. Then, a fourth encapsulation layer is fabricated and the carrier board is removed.

[0185] S6”: Flip the current package structure (the package structure obtained in steps s1-s4), and make a fourth wiring metal layer in the first molding layer, so that the fourth wiring metal layer is connected to the first wiring metal layer. The fourth wiring metal layer is the third wiring component.

[0186] s6”: A third wiring metal sublayer A is fabricated at the corresponding position of the third wiring metal sublayer B, penetrating the second molding layer, and then the third wiring metal sublayer A is connected to the third wiring metal sublayer B to obtain a third wiring metal layer. The third wiring metal layer is then connected to the second wiring metal layer, and the second wiring metal layer and the third wiring metal layer form a second rewiring component.

[0187] s7”: A third dielectric layer is fabricated on the first molding layer, and pads are fabricated on the third dielectric layer. The third wiring metal layer, the fourth wiring metal layer, and the second side electrode of the first chip are connected to the pads.

[0188] In one example, the second encapsulation layer obtained by molding the second chip is replaced by:

[0189] The second chip and the first wiring metal layer are encapsulated to obtain a second encapsulation layer, which reduces the volume of the package structure and prevents the first wiring metal layer from being exposed to the air, thereby improving the package reliability.

[0190] In one example, the process includes fabricating a third dielectric layer on the first molding layer and fabricating pads on the third dielectric layer, followed by:

[0191] A third dielectric layer is fabricated on the first molding layer;

[0192] A hole is made in the third dielectric layer until the third wiring metal layer, the fourth wiring metal layer, and the second surface electrode of the first chip are exposed, thus obtaining several sixth through holes;

[0193] Fill the sixth through hole with lead metal;

[0194] Pads are fabricated on the third dielectric layer, and the third wiring metal layer, the fourth wiring metal layer, and the second-side electrode of the first chip are connected to the pads via lead metal. In this example, lead metal is introduced through the third dielectric layer, and the connection between the third wiring metal layer, the fourth wiring metal layer, the second-side electrode of the first chip, and the pads is achieved through the lead metal, thereby improving the connection stability and reliability.

[0195] In this example, the third dielectric layer can be replaced with interconnected fourth and fifth dielectric layers. In this case, the following steps are required before creating the pads:

[0196] A fourth dielectric layer is fabricated on the first molding layer;

[0197] A hole is made in the fourth dielectric layer until the third wiring metal layer, the fourth wiring metal layer, and the second surface electrode of the first chip are exposed, thus obtaining several seventh vias;

[0198] The seventh through-hole is filled with the fifth wiring metal layer;

[0199] Fabricate a fifth dielectric layer on the fourth dielectric layer;

[0200] A hole is made in the fifth dielectric layer until the fifth wiring metal layer is exposed, thereby obtaining several eighth vias (located in the fifth dielectric layer).

[0201] Fill the eighth through hole with lead metal;

[0202] Pads are fabricated on the fifth dielectric layer, and the third wiring metal layer, the fourth wiring metal layer, and the second side electrode of the first chip are sequentially connected to the pads via the fifth wiring metal layer and the lead metal.

[0203] Combining the above examples, a second preferred example of the method for fabricating the package (sub) structure when the first chip and the second chip are reversed is obtained, including the following steps:

[0204] s1”': For example Figure 14 As shown, the front side of the first chip 1 is pasted onto the carrier board 3, and the first chip 1 is encapsulated to obtain the first encapsulation layer 4a; then a groove is made in the first encapsulation layer 4a to expose the back electrode of the first chip 1.

[0205] s2”': For example Figure 15 As shown, a first wiring metal layer 18 (interconnect metal block) is fabricated in the groove. The first wiring metal layer 18 is preferably fabricated by electroplating Cu. The first wiring metal layer 18 is the first rewiring component. At this time, the surface of the first wiring metal layer 18 is flush with the surface of the first molding layer 4a. This is generally achieved by grinding the first wiring metal layer 18 that protrudes from the surface of the first molding layer 4a.

[0206] s3”': For example Figure 16 As shown, a second chip 2 is fabricated on the first wiring metal layer 18. Preferably, the first wiring metal layer 18 and the back electrode of the second chip 2 are connected by soldering methods such as silver paste, eutectic bonding, and adhesive coating, thereby realizing the interconnection between the back electrode of the first chip 1 and the back electrode of the second chip 2.

[0207] s4”': For example Figure 17As shown, the second chip 2 is encapsulated to obtain a second encapsulation layer 4b, and a second wiring metal layer 19 is fabricated on the second encapsulation layer 4b so that the front electrode 13 of the second chip is connected to the second wiring metal layer 19. The second wiring metal layer 19 is then encapsulated to obtain a fourth encapsulation layer 4d, and the carrier board 3 is removed.

[0208] s5”': For example Figure 18 As shown, the current packaging structure (the packaging structure obtained in steps s1-s4) is flipped over. At this time, the front electrode 13 of the first chip faces upward and the front electrode 13 of the second chip faces downward. An opening is made in the first molding layer 4a until the first wiring metal layer 18 is exposed, thus obtaining the fourth blind hole 24.

[0209] s6”': For example Figure 19 As shown, a metal layer is filled in the fourth blind hole 24 as the fourth wiring metal layer 21. The fourth wiring metal layer 21 is essentially a third wiring component, so that the fourth wiring metal layer 21 is connected to the first wiring metal layer 18 to bring out the first wiring metal layer 18.

[0210] s7”': For example Figure 20 As shown, holes are made in the second molding layer 4b and the first molding layer 4a until the second wiring metal layer 19 is exposed, resulting in a fifth through hole 25 that penetrates the second molding layer 4b and the first molding layer 4a.

[0211] s8”': For example Figure 21 As shown, a metal layer is filled in the fifth through hole 25 as the third wiring metal layer 20, so that the third wiring metal layer 20 is connected to the second wiring metal layer 19, and the second wiring metal layer 19 and the third wiring metal layer 20 form a second rewiring component.

[0212] s9”': For example Figure 22 As shown, a fourth dielectric layer 23a is fabricated on the first molding layer 4a, and holes are made in the fourth dielectric layer 23a until the third wiring metal layer 20, the fourth wiring metal layer 21, and the second surface electrode of the first chip 1 are exposed, thus obtaining a number of seventh through holes 26.

[0213] s10”': For example Figure 23 As shown, the fifth wiring metal layer 22 is filled in the seventh through hole 26, and then the fifth dielectric layer 23b is fabricated on the fourth dielectric layer 23a. Holes are made in the fifth dielectric layer 23b until the fifth wiring metal layer 22 is exposed, thereby obtaining a number of eighth through holes 27 (located in the fifth dielectric layer 23b).

[0214] s11”': For example Figure 24As shown, pin metal 12 is filled in the eighth through-hole 27, and pads 11 are fabricated on the fifth dielectric layer 23b, such that the third wiring metal layer 20, the fourth wiring metal layer 21, and the second surface electrodes of the first chip 1 are connected to the pads 11 through the fifth wiring metal layer 22 and the pin metal 12 in sequence.

[0215] The present invention further includes a chip packaging structure, including a packaging sub-structure obtained according to the preparation method described in any of the above examples, which includes a first plastic package layer and a second plastic package layer arranged in a stacked manner. The first chip is encapsulated in the first plastic package layer, and the second chip is encapsulated in the second plastic package layer.

[0216] The second surface electrodes of the first chip or the second chip are connected to the pads through a second re-wiring component. When the second surface electrodes of the first chip are connected to the pads through the second re-wiring component, the second surface electrodes of the second chip are connected to the pads. When the second surface electrodes of the second chip are connected to the pads through the second re-wiring component, the second surface electrodes of the first chip are connected to the pads.

[0217] The first surface electrodes of the first chip and the first surface electrodes of the second chip are connected to the pads through a first re-wiring component and a third re-wiring component.

[0218] Preferably, when the first chip and the second chip are arranged in the same direction, the packaging sub-structure is as Figure 12 shown. The packaging sub-structure sequentially includes a third plastic package layer, a first wiring layer, a first plastic package layer, a first dielectric layer, a second plastic package layer, a second dielectric layer, and pads from bottom to top.

[0219] The first chip is encapsulated in the first plastic package layer. A third outer wiring layer is formed through the first plastic package layer and the first dielectric layer, and the third outer wiring layer is in a "return" shape.

[0220] A second wiring layer is formed in the first dielectric layer, and a third inner wiring layer is formed on the second wiring layer and within the first dielectric layer.

[0221] The second chip is encapsulated in the second plastic package. The first chip and the second chip are arranged in the same direction. A fourth wiring layer is further provided in the second plastic package layer, and the fourth wiring layer is disposed at the bottom of the second chip, that is, the fourth wiring layer is connected to the back electrodes of the second chip. A fifth inner wiring layer and a fifth outer wiring layer are further provided in the second plastic package layer, and the fifth inner wiring layer and the fifth outer wiring layer penetrate through the second plastic package layer.

[0222] Pin metal is formed in the second dielectric layer.

[0223] The front electrodes of the first chip are sequentially connected to the pads through the second wiring layer, the third inner wiring layer, the fifth inner wiring layer, and the pin metal. The front electrodes of the second chip are connected to the pads through the pin metal.

[0224] The back electrode of the first chip is connected to the pad via the first wiring layer, the third outer wiring layer, the fifth outer wiring layer, the lead metal, and the pad in sequence; the back electrode of the second chip is connected to the pad via the fourth wiring layer, the third outer wiring layer, the fifth outer wiring layer, the lead metal, and the pad.

[0225] Preferably, when the first chip and the second chip are reversed, the package substructure is as follows: Figure 24 As shown, the package substructure includes, from bottom to top, a fourth molding layer, a second molding layer, a first molding layer, a fourth dielectric layer, a fifth dielectric layer, and pads;

[0226] A second wiring metal layer is formed within the fourth molding layer, and the second wiring metal layer is connected to the front electrode of the second chip.

[0227] A third wiring metal layer is formed through the first molding layer and the second molding layer. The third wiring metal layer is connected to the second wiring metal layer. The second wiring metal layer and the third wiring metal layer form a second rewiring component.

[0228] The first molding compound encapsulates a first chip, which is positioned in reverse order of the second chip. The first molding compound also contains a first wiring metal layer (first rewiring component), which is located at the bottom of the first chip and is connected to the back electrode of the first chip. The second molding compound also contains a fourth wiring metal layer, which is connected to the first wiring metal layer. The first and fourth wiring metal layers form a third rewiring component.

[0229] A fifth wiring metal layer is formed within the fourth dielectric layer;

[0230] Lead metal is formed within the fifth dielectric layer;

[0231] The back electrode of the first chip and the back electrode of the second chip are connected to the pads sequentially through the first wiring metal layer, the fourth wiring metal layer, the fifth wiring metal layer, the lead metal layer, and the pad.

[0232] The front electrode of the first chip is connected to the pad via the fifth wiring metal layer, the lead metal layer, and the solder pad in sequence; the front electrode of the second chip is connected to the pad via the second wiring metal layer, the third wiring metal layer, the fifth wiring metal layer, the lead metal layer, and the solder pad in sequence.

[0233] In one example, the packaging substructures prepared in the above example are horizontally spliced ​​together to obtain a multi-chip packaging structure. In this example, the packaging structure can be obtained by horizontally splicing together the packaging substructure formed by two chips, or it can be obtained during the preparation of the packaging substructure. In this case, the two chips are a group of each other. Multiple first chips are packaged in the first molding compound layer, and multiple second chips are packaged in the second molding compound layer. Other steps are performed by interconnecting the two chips as a group through redistribution components. Redistribution components with the same function can be fabricated in the same process. This process simplifies the manufacturing process, saves packaging time, and greatly improves packaging efficiency.

[0234] The above detailed embodiments are a description of the present invention. It should not be considered that the specific embodiments of the present invention are limited to these descriptions. For those skilled in the art, several simple deductions and substitutions can be made without departing from the concept of the present invention, and all of these should be considered to fall within the protection scope of the present invention.

Claims

1. A method of fabricating a chip package structure, the method comprising: It comprises: ​ Packaging the first chip to obtain a first plastic package layer; Making a first rewiring part, which is connected with the first surface electrode of the first chip; Packaging the second chip to obtain a second plastic package layer stacked on the first plastic package layer, and the first surface electrode of the second chip is connected with the first surface electrode of the first chip through the first rewiring part; the first surface electrode of the first chip and the first surface electrode of the second chip are the same electrode; Making a second rewiring part, the second surface electrode of the first chip or the second surface electrode of the second chip is connected with the pad through the second rewiring part; when the second surface electrode of the first chip is connected with the pad through the second rewiring part, the second surface electrode of the second chip is connected with the pad; when the second surface electrode of the second chip is connected with the pad through the second rewiring part, the second surface electrode of the first chip is connected with the pad; Making a third rewiring part, the first surface electrode of the first chip and the first surface electrode of the second chip are connected with the pad through the first rewiring part and the third rewiring part; When the first chip and the second chip are arranged in the same direction, the method comprises the following steps: Pasting the first chip on the carrier board, packaging the first chip to obtain a first plastic package layer, making a first wiring layer on the first plastic package layer, and making a third plastic package layer on the first wiring layer; After removing the carrier board, making a second wiring layer and depositing a first dielectric layer; Making a third inner wiring layer in the first dielectric layer, connecting the third inner wiring layer with the second wiring layer, and making a third outer wiring layer penetrating through the first plastic package layer and the first dielectric layer; Making a fourth wiring layer on the first dielectric layer, connecting the fourth wiring layer with the third outer wiring layer, and the first wiring layer, the third outer wiring layer and the fourth wiring layer constitute a first rewiring part; Pasting the second chip on the fourth wiring layer, connecting the first surface electrode of the second chip with the fourth wiring layer, and packaging the second chip to obtain a second plastic package layer; Making a fifth inner wiring layer and a fifth outer wiring layer penetrating through the second plastic package layer, connecting the fifth inner wiring layer with the third inner wiring layer, and the second wiring layer, the third inner wiring layer and the fifth inner wiring layer form a second rewiring part; the fifth outer wiring layer is a third rewiring part, which is connected with the third outer wiring layer; Making a pad on the second plastic package layer, and connecting the fifth inner wiring layer, the fifth outer wiring layer and the second surface electrode of the second chip with the pad; When the first chip and the second chip are arranged in opposite directions, the method comprises the following steps: Pasting the first chip on the carrier board, packaging the first chip to obtain a first plastic package layer, and slotting the first plastic package layer to expose the first surface electrode of the first chip; Making a first wiring metal layer in the groove, which is a first rewiring part; Making the second chip on the first wiring metal layer, and connecting the first wiring metal layer with the first surface electrode of the second chip; Packaging the second chip to obtain a second plastic package layer, making a second wiring metal layer on the second plastic package layer, connecting the second surface electrode of the second chip with the second wiring metal layer, and then making a fourth plastic package layer and removing the carrier board; Turn over the current packaging structure, manufacture the third wiring metal layer penetrating the first plastic sealing layer and the second plastic sealing layer, make the third wiring metal layer connect with the second wiring metal layer, and the second wiring metal layer and the third wiring metal layer form the second re-wiring part; Manufacture the fourth wiring metal layer in the first plastic sealing layer, make the fourth wiring metal layer connect with the first wiring metal layer, and the fourth wiring metal layer is the third re-wiring part; Manufacture the third dielectric layer on the first plastic sealing layer, and manufacture the pad on the third dielectric layer, and the third wiring metal layer, the fourth wiring metal layer and the second surface electrode of the first chip connect with the pad.

2. The method of claim 1, wherein: When the first chip and the second chip are set in the same direction, the second plastic sealing layer obtained by plastic sealing the second chip is replaced by: Plastic seal the fourth wiring layer and the second chip to obtain the second plastic sealing layer.

3. The method of claim 1, wherein: When the first chip and the second chip are set in the same direction, before manufacturing the pad on the second plastic sealing layer, it further includes: Manufacture the second dielectric layer on the second plastic sealing layer; Hole the second dielectric layer until the fifth inner wiring layer, the fifth outer wiring layer and the second surface electrode of the second chip are exposed to obtain a plurality of through holes; Fill the pin metal in the through hole; Manufacture the pad on the second dielectric layer, and the fifth inner wiring layer, the fifth outer wiring layer and the second surface electrode of the second chip connect with the pad through the pin metal.

4. The method of claim 1, wherein: When the first chip and the second chip are set in reverse, the third wiring metal layer includes interconnected third wiring metal sublayer A and third wiring metal sublayer B, the third wiring metal sublayer A penetrates the second plastic sealing layer, and the third wiring metal sublayer B penetrates the first plastic sealing layer.

5. The method of claim 1, wherein: When the first chip and the second chip are set in reverse, the second plastic sealing layer obtained by plastic sealing the second chip is replaced by: Plastic seal the second chip and the first wiring metal layer to obtain the second plastic sealing layer.

6. The method of claim 1, wherein: When the first chip and the second chip are set in reverse, the manufacturing of the pad on the third dielectric layer includes: Manufacture the third dielectric layer on the first plastic sealing layer; Hole the third dielectric layer until the third wiring metal layer, the fourth wiring metal layer and the second surface electrode of the first chip are exposed to obtain a plurality of through holes; Fill the pin metal in the through hole; Manufacture the pad on the third dielectric layer, and the third wiring metal layer, the fourth wiring metal layer and the second surface electrode of the first chip connect with the pad through the pin metal.

7. A chip package structure, characterized by: The package substructure is obtained by the preparation method according to any one of claims 1-6, and the package substructure includes the first plastic sealing layer and the second plastic sealing layer arranged in a stack, the first chip is encapsulated in the first plastic sealing layer, and the second chip is encapsulated in the second plastic sealing layer; The second surface electrode of the first chip or the second surface electrode of the second chip connects with the pad through the second re-wiring part; when the second surface electrode of the first chip connects with the pad through the second re-wiring part, the second surface electrode of the second chip connects with the pad; when the second surface electrode of the second chip connects with the pad through the second re-wiring part, the second surface electrode of the first chip connects with the pad; The first surface electrode of the first chip and the first surface electrode of the second chip connect with the pad through the first re-wiring part and the third re-wiring part.

8. The chip package structure of claim 7, wherein: The package substructure includes a plurality of package substructures, and each package substructure is horizontally spliced to obtain a multi-chip package structure.

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