Semiconductor structure and method of forming the same

Abstract

The embodiments of the present disclosure provide a semiconductor structure and a forming method thereof, wherein the forming method of the semiconductor structure comprises: providing a substrate; the substrate comprises a first PMOS region and a peripheral signal region; sequentially forming a first epitaxial layer and a second epitaxial layer on at least the first PMOS region; in the process of forming a first gate oxide layer on the peripheral signal region, the second epitaxial layer is consumed.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and a method for forming the same. Background Technology

[0002] Silicon germanium (SiGe) is used in high-k metal gate (HKMG) technology to improve the performance of PMOS devices because of its narrower bandgap and the fact that strained SiGe can improve carrier mobility.

[0003] In the HKMG process, the growth of a thick gate oxide layer will cause SiGe to be consumed, which will lead to an increase in the threshold voltage. Therefore, a cap layer needs to be added after SiGe is formed to protect the single-crystal SiGe structure from being damaged or even oxidized and consumed. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and a method for forming the same.

[0005] In a first aspect, embodiments of this disclosure provide a method for forming a semiconductor structure, comprising: providing a substrate; the substrate comprising a first PMOS region and a peripheral signal region; sequentially forming a first epitaxial layer and a second epitaxial layer on at least the first PMOS region; and consuming the second epitaxial layer during the formation of a first gate oxide layer on the peripheral signal region.

[0006] In some embodiments, the substrate further includes: a first NMOS region; at least a first epitaxial layer and a second epitaxial layer are sequentially formed on the first PMOS region, including: forming a barrier layer on the first NMOS region and the peripheral signal region; and sequentially forming the first epitaxial layer and the second epitaxial layer on the barrier layer and the first PMOS region.

[0007] In some embodiments, before forming the first gate oxide layer, the method further includes: removing the first epitaxial layer and the second epitaxial layer on the barrier layer to expose the barrier layer; consuming the second epitaxial layer during the formation of the first gate oxide layer on the peripheral signal region, including: consuming the second epitaxial layer on the first PMOS region during the formation of the first gate oxide layer on the surface of the barrier layer on the peripheral signal region.

[0008] In some embodiments, the method further includes: forming a second gate oxide layer on a first epitaxial layer on the first PMOS region, a first gate oxide layer, and a barrier layer on the first NMOS region; wherein the thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer.

[0009] In some embodiments, the first epitaxial layer and the second epitaxial layer on the first PMOS region respectively include a single-crystal SiGe layer and a single-crystal Ge layer; the first epitaxial layer and the second epitaxial layer on the first NMOS region and the peripheral signal region respectively include a polycrystalline SiGe layer and a polycrystalline Ge layer.

[0010] In some embodiments, the formation of the first gate oxide layer includes: forming an initial oxide layer on a barrier layer on the first NMOS region and the peripheral signal region; removing the initial oxide layer on the barrier layer on the first NMOS region; and forming the first gate oxide layer on the peripheral signal region.

[0011] In some embodiments, the process parameters for forming the first epitaxial layer include: a temperature range of 600 to 730°C, a gas pressure range of 5 to 20 Torr, a time range of 50 to 300 s, a SiH4 gas flow rate range of 40 to 270 sccm, a DCS gas flow rate range of 50 to 300 sccm, a GeH4 gas flow rate range of 20 to 80 sccm, and an HCl gas flow rate range of 0 to 90 sccm.

[0012] In some embodiments, the process parameters for forming the second epitaxial layer include: a temperature range of 450 to 620°C, a gas pressure range of 5 to 20 Torr, a time range of 30 to 200 s, a GeH4 gas flow rate range of 20 to 270 sccm, and an HCl gas flow rate range of 0 to 50 sccm.

[0013] In some embodiments, the process parameters for removing the first and second epitaxial layers on the barrier layer include: a temperature range of 450 to 700°C, a gas pressure range of 5 to 20 Torr, a time range of 60 to 800 s, a GeH4 gas flow rate range of 0 to 40 sccm, and an HCl gas flow rate range of 50 to 120 sccm.

[0014] In some embodiments, an in-situ water vapor oxidation process is used to form the initial oxide layer; wherein the process parameters of the in-situ water vapor oxidation process include: a temperature range of 900 to 1100°C, a gas pressure range of 5 to 30 Torr, a time range of 30 to 60 s, an O2 gas flow rate range of 20 to 30 slm, and an H2 gas flow rate range of 1 to 2 slm.

[0015] In some embodiments, the thickness of the first epitaxial layer ranges from 8 to 15 nm; the thickness of the second epitaxial layer ranges from 1 to 4 nm.

[0016] In some embodiments, the method further includes forming transistors on the second gate oxide layer of the first NMOS region, the first PMOS region, and the peripheral signal region.

[0017] In a second aspect, embodiments of this disclosure provide a semiconductor structure formed according to the formation method described in any of the above embodiments; wherein the semiconductor structure includes: a substrate, the substrate including a first PMOS region and a peripheral signal region; a first epitaxial layer located on the first PMOS region; and a first gate oxide layer located on the peripheral signal region.

[0018] In some embodiments, the substrate further includes a first NMOS region; the semiconductor structure further includes a barrier layer located on the peripheral signal region and the first NMOS region; correspondingly, the first gate oxide layer is located on the barrier layer on the peripheral signal region.

[0019] In some embodiments, the semiconductor structure further includes a second gate oxide layer located on the first gate oxide layer, the first NMOS region, and the first epitaxial layer; wherein the thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer.

[0020] In this embodiment, firstly, a substrate is provided; the substrate includes a first PMOS region and a peripheral signal region; secondly, a first epitaxial layer and a second epitaxial layer are sequentially formed on at least the first PMOS region; finally, the second epitaxial layer is consumed during the formation of the first gate oxide layer on the peripheral signal region. Since the first epitaxial layer can serve as the channel material for the first PMOS region, improving carrier mobility, it enhances the performance of the subsequently formed device; the second epitaxial layer can serve as a sacrificial layer and a protective layer, not only protecting the first epitaxial layer from oxidation damage during the subsequent formation of the first gate oxide layer, but also being completely consumed during the formation of the first gate oxide layer. This reduces or even avoids defects in the first epitaxial layer, thereby achieving a lower threshold voltage and higher carrier mobility to improve device performance. Attached Figure Description

[0021] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0022] Figure 1 A schematic diagram illustrating the implementation flow of a method for forming a semiconductor structure according to an embodiment of this disclosure;

[0023] Figures 2 to 11 This is a schematic diagram illustrating the formation process of a semiconductor structure according to an embodiment of the present disclosure. Detailed Implementation

[0024] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0025] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0026] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0027] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0029] Before introducing the embodiments of this disclosure, the SiGe channel and the steps of forming a cap layer on the SiGe channel in the related art will be introduced first.

[0030] Dynamic Random Access Memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data, and is widely used in data storage devices. A DRAM device may include a substrate with peripheral regions and multiple array regions. The peripheral regions include peripheral functional regions and peripheral signal regions. Typically, each array region is a memory array tile (MAT) area, containing memory cells. Each memory cell typically includes a capacitor and a transistor. The transistor's gate is connected to the word line (WL), its drain to the bit line, and its source to the capacitor. The peripheral regions contain driver circuits, clock circuits, etc., used to control the read and write operations of the memory cells in the array regions. The peripheral regions may include P-type transistors and N-type transistors.

[0031] The P-type metal-oxide-semiconductor (PMOS) in the peripheral functional region is hole-conducting, and the hole mobility is relatively low. Meanwhile, the gate oxide layer is a thin gate oxide layer; to prevent breakdown of the thin gate oxide layer, a threshold voltage (V) is required. t The threshold voltage (threshold voltage) cannot be too large. Therefore, materials that can improve carrier mobility need to be embedded in the channel region of the PMOS in the peripheral functional region to improve the performance of the DRAM device. The N-type metal-oxide-semiconductor (NMOS) region of the peripheral functional region is electronically conductive, and the gate oxide layers of the PMOS and NMOS regions in the peripheral signal region are thick gate oxide layers, which can increase the threshold voltage. Therefore, neither the NMOS region of the peripheral functional region nor the peripheral signal region needs to improve the carrier mobility.

[0032] In related technologies, silicon (Si) layers are generally used as cap layers. Cap layers include trench-filled cap layers and silane (SiH4) or dichlorosilane (DCS) as the silicon source epitaxial silicon layer. However, trench-filled cap layer growth processes have sidewalls, which differ from SiGe channels in semiconductor fabrication; silanes have poor selectivity and low decomposition efficiency at low temperatures in DCS, while high temperatures can cause changes in the SiGe profile.

[0033] The process of forming the SiGe channel and Si cap layer in related technologies is as follows: First, a 10-nanometer (nm) thick single-crystal SiGe layer is formed on the PMOS in the peripheral functional region, and a barrier layer, such as an oxide layer, is formed on the single-crystal SiGe layer, the NMOS region in the peripheral functional region, the peripheral signal region, and the array region. Second, the barrier layer on the NMOS region and the peripheral signal region in the peripheral functional region is removed. Third, a thick gate oxide layer is formed on the peripheral functional region and the peripheral signal region. Next, photoresist is formed on the peripheral signal region and the array region to remove the thick gate oxide layer on the peripheral functional region, retaining the thick gate oxide layer on the peripheral signal region. Finally, a thin gate oxide layer is formed on the peripheral functional region. Because the barrier layer has a weak barrier capability during the formation of the thick gate oxide layer, oxygen can pass through the barrier layer and oxidize the SiGe layer, thus consuming the 4nm single-crystal SiGe layer.

[0034] In view of this, embodiments of this disclosure provide a method for forming a semiconductor structure, with reference to... Figure 1 The method includes steps S101 to S103, wherein:

[0035] Step S101: Provide a substrate; the substrate includes a first PMOS region and a peripheral signal region;

[0036] refer to Figure 2 A substrate 10 is provided, which includes a first PMOS region 12 and a peripheral signal region 13. The peripheral signal region 13 may include a second NMOS region 131 and a second PMOS region 132.

[0037] Here, the substrate may include a silicon substrate, a germanium substrate, a silicon germanide substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.; the substrate may also include other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc. In other embodiments, the substrate may also be an ion-doped substrate, such as a p-type doped substrate or an n-type doped substrate.

[0038] In some embodiments, the substrate may further include an array region, which may include a shallow trench isolation (STI) structure for forming an isolation structure between devices.

[0039] Step S102: At least a first epitaxial layer and a second epitaxial layer are sequentially formed on the first PMOS region;

[0040] refer to Figure 3 A first epitaxial layer 21 and a second epitaxial layer 22 are sequentially formed on the first PMOS region 12.

[0041] Here, the first epitaxial layer serves as the channel material for the first PMOS region, thereby improving the performance of the device formed subsequently. The second epitaxial layer (i.e., the cap layer) can serve as a sacrificial layer and a protective layer. It can not only protect the first epitaxial layer from oxidation when the first gate oxide layer is formed, but also be completely consumed during the formation of the first gate oxide layer.

[0042] The first and second epitaxial layers are made of the same material or have similar structures to the substrate. For example, the first epitaxial layer may be a single-crystal SiGe layer, and the second epitaxial layer may be a single-crystal Ge layer. In some embodiments, the first or second epitaxial layer may include at least one of a single-layer structure or a multilayer structure.

[0043] In practice, apart from the crystal orientation needing to be consistent with the substrate, other characteristics of the epitaxial layer, such as material doping type and resistivity, can be selected according to the specific circumstances. Understandably, when the material of the epitaxial layer is consistent with the substrate material, the semiconductor structure can achieve better performance.

[0044] For every 1 angstrom increase in SiGe thickness The threshold voltage of a PMOS decreases by 1 millivolt (mV), and for every 1% increase in Ge concentration, the threshold voltage decreases by 12 mV. Simultaneously, with increasing thickness and Ge concentration, the thin film tends towards a relaxation state, resulting in increased leakage current and decreased mobility; therefore, the SiGe thickness represents an equilibrium state. In implementation, the thickness and Ge concentration of the single-crystal SiGe layer can be selected as needed.

[0045] The first and second epitaxial layers can be formed by epitaxial growth, wherein the epitaxial growth methods include, but are not limited to, Gas Source Molecular Beam Epitaxy (GSMBE), Solid Source Molecular Beam Epitaxy (SSMBE), and Ultra-High Vacuum Chemical Vapor Deposition (UHV / CVD). GSMBE and UHV / CVD methods are similar, both using gas as the growth source; the main difference lies in the gas pressure in the growth chamber during epitaxy. UHV / CVD uses a higher gas pressure, while GSMBE uses a lower pressure. UHV / CVD and GSMBE have significant advantages over SSMBE in growing SiGe materials, such as not requiring a high-temperature evaporation furnace and not needing to break the vacuum in the growth chamber when changing the source, thus maintaining the purity of the growth chamber for a long time, which is beneficial for growing high-quality materials. Those skilled in the art can choose the appropriate epitaxial growth method as needed, and the embodiments disclosed herein are not limited in this regard.

[0046] In some embodiments, the thickness of the first epitaxial layer can range from 8 to 15 nm, for example, the thickness of the first epitaxial layer is 10 nm, which can better improve carrier mobility. The thickness of the second epitaxial layer can range from 1 to 4 nm, for example, the thickness of the second epitaxial layer is 3 nm; this allows the second epitaxial layer to be consumed precisely during the process of forming the first gate oxide layer, thereby better protecting the first epitaxial layer while simplifying the process flow; if the thickness of the second epitaxial layer is too large, it cannot be completely removed in subsequent steps; if the thickness of the second epitaxial layer is too small, it cannot provide protection in subsequent steps.

[0047] In step S103, the second epitaxial layer is consumed during the formation of the first gate oxide layer on the peripheral signal region.

[0048] refer to Figure 4 During the formation of the first gate oxide layer 23 on the peripheral signal region 13, the second epitaxial layer 22 is consumed (see reference). Figure 3 ), exposing the first epitaxial layer 21.

[0049] Here, the first gate oxide layer can be formed using suitable processes such as thermal oxidation (Thermo Oxide) or in-situ steam generation (ISSG). Thermal oxidation is characterized by the ability to form a thicker oxide layer in a short time, resulting in high production efficiency and low production costs. ISSG, also known as internal steam oxidation, can be considered a low-pressure rapid oxidation thermal annealing technique. It performs compensating oxidation growth simultaneously with thermal annealing, which helps to form a denser and more uniform gate oxide film, thus resulting in a first gate oxide layer with fewer defects and a higher breakdown voltage.

[0050] During the formation of the first gate oxide layer (e.g., using the ISSG process), the second epitaxial layer, such as a single-crystal Ge layer, is oxidized to form germanium monoxide or germanium dioxide. The ISSG process typically operates at a temperature of 1000°C, at which the germanium compound is vaporized (e.g., germanium monoxide is vaporized at 710°C), thereby gradually consuming the single-crystal Ge layer.

[0051] In practice, the thickness of the second epitaxial layer (e.g., a single-crystal germanium layer) needs to be matched with the process of the first gate oxide layer (i.e., thick gate oxide) so that it is completely consumed in the thick gate oxide process, leaving no residue and achieving the function of protecting the SiGe layer. Therefore, the thickness of the second epitaxial layer and the process parameters for forming the first gate oxide layer can be adjusted so that the second epitaxial layer is completely consumed after the process of forming the first gate oxide layer is completed, thereby better protecting the first epitaxial layer.

[0052] In this embodiment, firstly, a substrate is provided; the substrate includes a first PMOS region and a peripheral signal region; secondly, a first epitaxial layer and a second epitaxial layer are sequentially formed on at least the first PMOS region; finally, the second epitaxial layer is consumed during the formation of the first gate oxide layer on the peripheral signal region. Since the first epitaxial layer can serve as the channel material for the first PMOS region, improving carrier mobility, it enhances the performance of the subsequently formed device; the second epitaxial layer can serve as a sacrificial layer and a protective layer, not only protecting the first epitaxial layer from oxidation damage during the subsequent formation of the first gate oxide layer, but also being completely consumed during the formation of the first gate oxide layer. This reduces or even avoids defects in the first epitaxial layer, thereby achieving a lower threshold voltage and higher carrier mobility to improve device performance.

[0053] In some embodiments, the substrate further includes a first NMOS region. The implementation of step S102 may include:

[0054] Step S1021: A barrier layer is formed on the first NMOS region and the peripheral signal region;

[0055] refer to Figure 5 The substrate 10 includes a first NMOS region 11, a first PMOS region 12, and a peripheral signal region 13; the first NMOS region 11 and the first PMOS region 12 can constitute a peripheral functional region. In some embodiments, the substrate 10 further includes an array region 14, which includes an isolation structure 141, a gate structure 142, and an insulating structure 143 located on the isolation structure 141 and the gate structure 142. Here, the insulating structure may include an oxide layer and a nitride layer.

[0056] refer to Figure 6 A barrier layer 24 is formed on the first NMOS region 11 and the peripheral signal region 13. Figure 6 As can be seen, no barrier layer is formed on the insulating structure 143 of the array region 14.

[0057] Here, the barrier layer serves to allow the formation of a single-crystal SiGe layer on the first PMOS region and a polycrystalline SiGe layer on other regions in subsequent processes. The barrier layer can be made of oxides, such as silicon oxide or silicon oxynitride. The barrier layer can be formed using any of the following processes: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), spin coating, or coating. In this embodiment, an Atomic Layer Deposition process can be used to form an initial barrier layer on the first NMOS region, the first PMOS region, and the peripheral signal region to improve the quality of the barrier layer. Subsequently, the first NMOS region and the peripheral signal region are masked, and the initial barrier layer on the first PMOS region is etched away to form a barrier layer on the first NMOS region and the peripheral signal region.

[0058] Step S1022: A first epitaxial layer and a second epitaxial layer are sequentially formed on the barrier layer and the first PMOS region.

[0059] Here, a full epitaxial process can be used to form the first and second epitaxial layers. The full epitaxial process refers to forming a single-crystal layer, such as single-crystal SiGe, on the surface of a single-crystal silicon wafer, and forming polycrystalline layers on other insulating layers (including barrier layers) of the silicon wafer.

[0060] In some embodiments, the first epitaxial layer and the second epitaxial layer on the first PMOS region respectively include a single-crystal SiGe layer and a single-crystal Ge layer; the first epitaxial layer and the second epitaxial layer on the first NMOS region and the peripheral signal region respectively include a polycrystalline SiGe layer and a polycrystalline Ge layer.

[0061] refer to Figure 7A first epitaxial layer 21 is formed on the barrier layer 24 and the first PMOS region 12. The first epitaxial layer 21 may include a first sub-epitaxial layer 211 located on the first PMOS region 12 and a second sub-epitaxial layer 212 located on the barrier layer 24. Since there is no barrier layer on the first PMOS region 12, the first sub-epitaxial layer 211 may be a single-crystal SiGe layer; the second sub-epitaxial layer 212 on the barrier layer 24 may be a polycrystalline SiGe layer.

[0062] refer to Figure 8 A second epitaxial layer 22 is formed on the first epitaxial layer 21. The second epitaxial layer 22 may include a third sub-epitaxy layer 221 located on the first PMOS region 12 and a fourth sub-epitaxy layer 222 located on the first NMOS region 11 and the peripheral signal region 13. The third sub-epitaxy layer 221 may be a single-crystal Ge layer, and the fourth sub-epitaxy layer 222 may be a polycrystalline Ge layer.

[0063] Since the array region 14 includes an insulating structure 143, a second sub-epitaxial layer 212, such as a polycrystalline SiGe layer, is also formed on the array region 14. During the formation of the second epitaxial layer, a fourth sub-epitaxial layer 222, such as a polycrystalline Ge layer, is formed on the second sub-epitaxial layer 212 on the array region 14.

[0064] In some embodiments, the formation process parameters of the first epitaxial layer may include: a temperature range of 600 to 730 degrees Celsius (°C), a gas pressure range of 5 to 20 Torr, a time range of 50 to 300 seconds (s), a SiH4 gas flow rate range of 40 to 270 standard condition milliliters per minute (sccm), a DCS gas flow rate range of 50 to 300 sccm, a germanium hydride (GeH4) gas flow rate range of 20 to 80 sccm, and a hydrogen chloride (HCl) gas flow rate range of 0 to 90 sccm.

[0065] During implementation, the temperature can be selected as 600℃, 650℃, or 730℃; the gas pressure can be selected as 5 Torr, 8 Torr, 10 Torr, or 20 Torr; the time can be selected as 50s, 100s, 200s, or 300s; the SiH4 gas flow rate can be selected as 40ccm, 100sccm, 200sccm, or 270sccm; the DCS gas flow rate can be selected as 50sccm, 100sccm, 200sccm, or 300sccm; the GeH4 gas flow rate can be selected as 20sccm, 40sccm, 60sccm, or 80sccm; and the HCl gas flow rate can be selected as 0sccm, 10sccm, 20sccm, 30sccm, 50sccm, 80sccm, or 90sccm.

[0066] For example, the formation process parameters of the first epitaxial layer are: temperature of 600℃, gas pressure of 20 Torr, time of 300s, SiH4 gas flow rate of 270sccm, DCS gas flow rate of 300sccm, GeH4 gas flow rate of 80sccm and HCl gas flow rate of 90sccm.

[0067] In some embodiments, the formation process parameters of the second epitaxial layer may include: a temperature range of 450 to 620°C, a gas pressure range of 5 to 20 Torr, a time range of 30 to 200 s, a GeH4 gas flow rate range of 20 to 270 sccm, and an HCl gas flow rate range of 0 to 50 sccm.

[0068] In some embodiments, the method for forming a semiconductor structure prior to forming the first gate oxide layer further includes:

[0069] Step S11: Remove the first epitaxial layer and the second epitaxial layer on the barrier layer to expose the barrier layer;

[0070] Correspondingly, the implementation of step S103, "consuming the second epitaxial layer during the formation of the first gate oxide layer on the peripheral signal region", may include: consuming the second epitaxial layer on the first PMOS region during the formation of the first gate oxide layer on the surface of the barrier layer on the peripheral signal region.

[0071] refer to Figure 8 and Figure 9 The first epitaxial layer 21 (i.e., the second sub-epitaxy layer 212) and the second epitaxial layer (i.e., the fourth sub-epitaxy layer 222) on the barrier layer 24 are removed, exposing the barrier layer 24. Figure 9 As can be seen, the first PMOS region 12 has a first epitaxial layer 21 and a second epitaxial layer 22.

[0072] In some embodiments, reference Figure 8 and Figure 9 During the process of removing the first epitaxial layer and the second epitaxial layer, the first epitaxial layer 21 and the second epitaxial layer 22 on the insulating structure 143 will also be removed, thereby exposing the insulating structure 143.

[0073] refer to Figure 10 During the process of forming the first gate oxide layer 23 on the surface of the barrier layer 24 on the peripheral signal region 13, the second epitaxial layer 22 on the first PMOS region 12 is consumed, thereby exposing the first epitaxial layer 21.

[0074] In some embodiments, the formation of the first gate oxide layer may include the following steps: forming an initial oxide layer on the blocking layer on the first NMOS region and the peripheral signal region; then, using a photomask to cover the first PMOS region 12 and the peripheral signal region 13, removing the initial oxide layer on the blocking layer on the first NMOS region 11, and forming the first gate oxide layer on the peripheral signal region 13.

[0075] In some embodiments, an in-situ water vapor oxidation process is used to form the initial oxide layer. The process parameters for this in-situ water vapor oxidation process include: a temperature range of 900 to 1100°C, a gas pressure range of 5 to 30 Torr, a time range of 30 to 60 seconds, an oxygen (O2) flow rate range of 20 to 30 slm / min (standard conditions), and a hydrogen (H2) flow rate range of 1 to 2 slm. This improves the quality of the formed first gate oxide layer. Furthermore, since germanium oxidation products are germanium monoxide and germanium dioxide, which have different crystal forms, germanium monoxide vaporizes at around 710°C. In the in-situ water vapor oxidation process, when the process temperature is around 1000°C, the germanium oxide will completely vaporize. In other words, only a temperature within the specific parameter range of 900 to 1000°C can completely consume germanium.

[0076] Here, hydrogen and oxygen are the reaction gases in the in-situ water vapor oxidation process. In other embodiments, the reaction gases also include a mixture of nitric oxide and hydrogen or a mixture of nitrogen dioxide and hydrogen.

[0077] During implementation, the temperature can be selected as 900℃, 1000℃ or 1100℃, and the pressure can be selected as 5 Torr, 8 Torr, 10 Torr, 20 Torr or 30 Torr.

[0078] In some embodiments, the process parameters for removing the first and second epitaxial layers on the barrier layer include: a temperature range of 450 to 700°C, a gas pressure range of 5 to 20 Torr, a time range of 60 to 800 s, a GeH4 gas flow rate range of 0 to 40 sccm, and an HCl gas flow rate range of 50 to 120 sccm.

[0079] Here, the first epitaxial layer on the barrier layer can be a polycrystalline SiGe layer, and the second epitaxial layer on the barrier layer can be a polycrystalline Si layer; the first epitaxial layer and the second epitaxial layer on the first PMOS region are a single-crystal SiGe layer and a single-crystal Si layer, respectively. In practice, different first epitaxial layers have the same thickness, and different second epitaxial layers also have the same thickness; that is, the polycrystalline SiGe layer and the polycrystalline Si layer have the same thickness, and the single-crystal SiGe layer and the single-crystal Si layer also have the same thickness.

[0080] HCl exhibits different etching rates for single-crystal SiGe and single-crystal Ge, and for polycrystalline SiGe and polycrystalline Ge. The etching selectivity of the etchant for polycrystalline SiGe and single-crystal Ge is 30-150, while the selectivity for polycrystalline Ge and single-crystal Ge is also 30-150. This allows for the complete removal of polycrystalline SiGe and polycrystalline Ge layers while minimizing the consumption of the single-crystal Ge layer, thus better protecting the single-crystal SiGe layer. In other words, HCl can completely remove the first and second epitaxial layers on the barrier layer, reduce the consumption of the second epitaxial layer on the first PMOS region, and does not consume the first epitaxial layer (i.e., the single-crystal SiGe layer) on the first PMOS region.

[0081] It should be noted that the role of GeH4 is to accelerate the etching rate of the first and second epitaxial layers, thereby saving time.

[0082] In this embodiment of the disclosure, the etching rates of the first epitaxial layer and the second epitaxial layer on different regions are different using HCl, which can remove the first epitaxial layer and the second epitaxial layer on the barrier layer.

[0083] In some embodiments, after step S103, the method for forming a semiconductor structure further includes: forming a second gate oxide layer on the first epitaxial layer, the first gate oxide layer, and the barrier layer on the first NMOS region; wherein the thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer.

[0084] refer to Figure 11 A second gate oxide layer 26 is formed on the first epitaxial layer 21, the first gate oxide layer 23 on the first PMOS region 12 and the barrier layer 24 on the first NMOS region.

[0085] Here, the first gate oxide layer can be a thick gate oxide layer, and the second gate oxide layer can be a thin gate oxide layer. In this way, the first gate oxide layer can reduce gate leakage current, and the second gate oxide layer can be made easier to turn on or conduct, so that the two can be used in different MOSFETs with different functions.

[0086] In some embodiments, the method for forming a semiconductor structure further includes forming transistors on the second gate oxide layer of the first NMOS region, the first PMOS region, and the peripheral signal region.

[0087] Here, a first NMOS transistor is formed on a first NMOS region, and a first PMOS transistor is formed on a first PMOS region; a second NMOS transistor is formed on a second NMOS region in the peripheral signal region, and a second PMOS transistor is formed on a second PMOS region in the peripheral signal region. The gate of the transistor may include a metal gate layer, the material of which may include titanium, cobalt, aluminum, or tungsten. In this way, the metal gate layer can reduce the threshold voltage drift, polysilicon depletion effect, excessively high gate resistance, and Fermi level pinning of the polysilicon gate, thereby improving the stability of the semiconductor structure and enhancing the performance of the transistors formed in the semiconductor structure.

[0088] In some embodiments, an HK layer may be formed before forming the metal gate layer. The material of the HK layer may include one or more of hafnium oxide, doped hafnium oxide, zirconium oxide, aluminum oxide, and lanthanum oxide.

[0089] In some embodiments, during the formation of the first gate oxide layer and the second gate oxide layer, a shielding layer is used to cover the array region, so that the first gate oxide layer and the second gate oxide layer are not formed on the array region 14.

[0090] This disclosure provides a method for forming a semiconductor structure, including:

[0091] A single-crystal SiGe layer or a polycrystalline SiGe layer (i.e., the first epitaxial layer) is epitaxially grown on a wafer; wherein, the wafer includes an array region, a peripheral functional region (including PMOS Peri Core and NMOS Peri Core, i.e., the first PMOS region and the first NMOS region) and a peripheral signal region (including PMOS Peri I / O and NMOS Peri I / O, i.e., the second PMOS region and the second NMOS region); the single-crystal SiGe layer or the polycrystalline SiGe layer is grown epitaxially and covers the entire wafer; the array region (which may have a silicon nitride layer), the peripheral signal region (which may have a silicon dioxide layer), and the NMOS Peri Core are epitaxially grown with polycrystalline SiGe layers, and the PMOS Peri Core is epitaxially grown with a single-crystal SiGe layer;

[0092] A second epitaxial layer (i.e., a single-crystal Ge layer or a polycrystalline Ge layer) is grown on a single-crystal SiGe layer or a polycrystalline SiGe layer. In other words, a single-crystal Ge layer is epitaxially grown on a single-crystal SiGe layer, and a polycrystalline Ge layer is epitaxially grown on a polycrystalline SiGe layer.

[0093] By utilizing the different etching rates of HCl on polycrystalline and monocrystalline layers, polycrystalline Ge and polycrystalline SiGe are etched with HCl, leaving only the required monocrystalline layer.

[0094] Taking advantage of the characteristic that single-crystal Ge layers are easily oxidized into gas, in the thick gate oxide process, the single-crystal Ge layer reacts with excess oxygen free radicals to generate gas, and by controlling the thickness, all single-crystal Ge is consumed in the reaction, thereby achieving the purpose of protecting the SiGe layer.

[0095] This disclosure provides a semiconductor structure, with reference to... Figure 4 The semiconductor structure is formed using the formation method in any of the above embodiments, including:

[0096] Substrate 10, which includes a first PMOS region 12 and a peripheral signal region 13;

[0097] The first epitaxial layer 21 is located on the first PMOS region 12;

[0098] The first gate oxide layer 23 is located on the outer signal region.

[0099] The semiconductor structure in this embodiment is formed using the above-described semiconductor structure formation method. Therefore, the first epitaxial layer is not oxidized, damaged, or even consumed, which can improve the carrier mobility and thus improve the performance of the semiconductor structure.

[0100] In some embodiments, the semiconductor structure further includes a second gate oxide layer located on the first epitaxial layer 21 and the first gate oxide layer 23.

[0101] In some embodiments, reference Figure 10 The substrate also includes a first NMOS region 11; the semiconductor structure also includes:

[0102] A barrier layer 24 is located on the peripheral signal region 13 and the first NMOS region 11;

[0103] Correspondingly, the first gate oxide layer 23 is located on the blocking layer 24 on the peripheral signal region 13.

[0104] In some embodiments, the substrate further includes an array region 14, which includes an isolation structure 141, a gate structure 142, and an insulating structure 143 located on the isolation structure 141 and the gate structure 142. Here, the insulating structure may include an oxide layer and a nitride layer.

[0105] In some embodiments, reference Figure 11 The semiconductor structure also includes:

[0106] A second gate oxide layer 26 is located on the first gate oxide layer 23, the first NMOS region 11, and the first epitaxial layer 21. The thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.

[0107] In some embodiments, the semiconductor structure further includes a transistor located on a second gate oxide layer in the first NMOS region, the first PMOS region, and the peripheral signal region.

[0108] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-target manner. The structural embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the various components shown or discussed are coupled or directly coupled to each other.

[0109] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0110] The features disclosed in the several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or structural embodiments.

[0111] The above descriptions are merely some embodiments of this disclosure, but the protection scope of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this disclosure should be included within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a first PMOS region and a peripheral signal region; sequentially forming a first epitaxial layer and a second epitaxial layer on at least the first PMOS region; consuming the second epitaxial layer in a process of forming a first gate oxide layer on the peripheral signal region; wherein the substrate further comprises a first NMOS region, and sequentially forming the first epitaxial layer and the second epitaxial layer on at least the first PMOS region comprises: forming a barrier layer on the first NMOS region and the peripheral signal region; sequentially forming the first epitaxial layer and the second epitaxial layer on the barrier layer and the first PMOS region; wherein the first epitaxial layer and the second epitaxial layer on the first PMOS region comprise a single-crystal SiGe layer and a single-crystal Ge layer respectively, and the first epitaxial layer and the second epitaxial layer on the first NMOS region and the peripheral signal region comprise a polycrystal SiGe layer and a polycrystal Ge layer respectively. 2.The method of claim 1, wherein before forming the first gate oxide layer, the method further comprises: removing the first epitaxial layer and the second epitaxial layer on the barrier layer to expose the barrier layer; and wherein consuming the second epitaxial layer in the process of forming the first gate oxide layer on the peripheral signal region comprises: consuming the second epitaxial layer on the first PMOS region in the process of forming the first gate oxide layer on the surface of the barrier layer on the peripheral signal region. 3.The method of claim 1, wherein the method further comprises: forming a second gate oxide layer on the first epitaxial layer on the first PMOS region, the first gate oxide layer, and the barrier layer on the first NMOS region, wherein the second gate oxide layer has a thickness smaller than that of the first gate oxide layer. 4.The method of claim 1, wherein forming the first gate oxide layer comprises: forming an initial oxide layer on the barrier layer on the first NMOS region and the peripheral signal region; and removing the initial oxide layer on the barrier layer on the first NMOS region to form the first gate oxide layer on the peripheral signal region. 5.The method of any one of claims 1 to 4, wherein a process parameter for forming the first epitaxial layer comprises: a temperature range of 600 to 730 ℃, a pressure range of 5 to 20 Torr, a time range of 50 to 300 s, a gas flow rate range of SiH4 of 40 to 270 sccm, a gas flow rate range of DCS of 50 to 300 sccm, a gas flow rate range of GeH4 of 20 to 80 sccm, and a gas flow rate range of HCl of 0 to 90 sccm. 6.The method of any one of claims 1 to 4, wherein a process parameter for forming the second epitaxial layer comprises: a temperature range of 450 to 620 ℃, a pressure range of 5 to 20 Torr, a time range of 30 to 200 s, a gas flow rate range of GeH4 of 20 to 270 sccm, and a gas flow rate range of HCl of 0 to 50 sccm. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 7. The forming method of any one of claims 2-4, wherein: the process parameters for removing the first and second epitaxial layers on the barrier layer include a temperature range of 450-700 °C, a pressure range of 5-20 Torr, a time range of 60-800 s, a gas flow rate of GeH4 ranging from 0 to 40 seem, and a gas flow rate of HCl ranging from 50 to 120 seem.

8. The forming method of claim 4, wherein: the initial oxide layer is formed using an in-situ water vapor oxidation process having process parameters including a temperature range of 900-1100 °C, a pressure range of 5-30 Torr, a time range of 30-60 s, a gas flow rate of O2 ranging from 20 to 30 slm, and a gas flow rate of H2 ranging from 1 to 2 slm.

9. The forming method of any one of claims 1-4, wherein: the first epitaxial layer has a thickness ranging from 8 to 15 nm, and the second epitaxial layer has a thickness ranging from 1 to 4 nm.

10. The forming method of claim 3, wherein: the method further comprises: forming a transistor on the second gate oxide layer of the first NMOS region, the first PMOS region, and the peripheral signal region.

11. A semiconductor structure, characterized by ， formed according to any one of claims 1-10, wherein the semiconductor structure comprises: a substrate comprising a first PMOS region and a peripheral signal region; a first epitaxial layer on the first PMOS region; a first gate oxide layer on the peripheral signal region.

12. The semiconductor structure of claim 11, wherein: the substrate further comprises a first NMOS region, and the semiconductor structure further comprises: a barrier layer on the peripheral signal region and the first NMOS region; correspondingly, the first gate oxide layer is on the barrier layer on the peripheral signal region.

13. The semiconductor structure of claim 12, wherein: the semiconductor structure further comprises: a second gate oxide layer on the first gate oxide layer, the first NMOS region, and the first epitaxial layer, wherein the second gate oxide layer has a thickness less than a thickness of the first gate oxide layer.

Images