A manufacturing method of a semiconductor large-capacitance capacitor structure

Abstract

The application discloses a manufacturing method of a semiconductor high-capacitance capacitor structure, which comprises the following steps: manufacturing a substrate, and sequentially manufacturing an epitaxial channel layer and an epitaxial barrier layer on the substrate, and forming a two-dimensional electron gas at the interface of the epitaxial channel layer and the epitaxial barrier layer; manufacturing an ohmic contact of a positive electrode on the epitaxial channel layer; manufacturing an isolation region, and making the isolation region penetrate through the epitaxial channel layer and extend into the substrate; depositing a first dielectric layer on the epitaxial barrier layer, etching the first dielectric layer, manufacturing a Schottky contact, forming a negative electrode; depositing a second dielectric layer on the first dielectric layer, etching a window at a position corresponding to the ohmic contact of the positive electrode, and depositing a metal at the window to lead out the positive electrode, and the deposited metal extends and covers on the second dielectric layer. The two-dimensional electron gas is used as an internal electrode of the capacitor to realize the lateral leading-out of the electrode, the thin-layer epitaxial barrier layer in the reverse type is selected as a capacitor dielectric layer, a large-capacitance on-chip capacitor is realized, and the process is simple and easy to integrate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a manufacturing method of semiconductor large-capacitance capacitor structure. BACKGROUND

[0002] When the radio frequency chip works, multiple large-capacitance bypass capacitors are needed as power filter or radio frequency bypass. In practical application, it is generally realized by externally connecting single-layer ceramic capacitors. The requirements for the device are often that it needs to withstand high DC voltage, the radio frequency equivalent series parasitic resistance and inductance are small, the heat dissipation performance is good, and the volume is small. Limited by materials and processes, it is difficult for the single-layer ceramic capacitor to compromise on the above requirements and give a satisfactory solution. In recent years, there are also examples of using multi-layer ceramic capacitors, which reduce the volume to a certain extent. However, in general, under the condition of fixed withstand voltage, the volume is large, the series parasitic resistance is not ideal, the parasitic inductance caused by off-chip interconnection is large, and the withstand voltage and process problems caused by multi-component installation are prominent. Therefore, developing a new capacitor manufacturing process to adapt to the on-chip integration of large-capacitance bypass has become the key. SUMMARY

[0003] The present application aims to overcome the problem of on-chip integration of large-capacitance bypass capacitor in the prior art, and provides a manufacturing method of semiconductor large-capacitance capacitor structure.

[0004] The purpose of the present application is achieved by the following technical solutions:

[0005] The present application mainly provides a manufacturing method of semiconductor large-capacitance capacitor structure, which comprises:

[0006] S1, making a substrate, and sequentially making an epitaxial channel layer and an epitaxial barrier layer on the substrate, and forming a two-dimensional electron gas at the interface of the epitaxial channel layer and the epitaxial barrier layer;

[0007] S2, making an ohmic contact of a positive electrode on the epitaxial channel layer;

[0008] S3, making an isolation region, so that the isolation region penetrates through the epitaxial channel layer and extends into the substrate;

[0009] S4, depositing a first dielectric layer on the epitaxial barrier layer, etching in the first dielectric layer, making a Schottky contact, and forming a negative electrode;

[0010] S5, depositing a second dielectric layer on the first dielectric layer, etching a window at a position corresponding to the ohmic contact of the positive electrode, and depositing a metal at the window to lead out the positive electrode, and the deposited metal extends and covers on the second dielectric layer.

[0011] In the present application, the two-dimensional electron gas is used as the internal electrode of the capacitor to realize the lateral lead-out of the electrode, and the thin-layer epitaxial barrier layer in reverse type is selected as the capacitor dielectric layer.

[0012] As a preferred option, a manufacturing method of a semiconductor high-capacitance capacitor structure, the negative electrode is a long strip structure.

[0013] As a preferred option, a manufacturing method of a semiconductor high-capacitance capacitor structure, the substrate is a silicon carbide substrate.

[0014] As a preferred option, a manufacturing method of a semiconductor high-capacitance capacitor structure, the epitaxial channel layer is a GaN epitaxial channel layer.

[0015] As a preferred option, a manufacturing method of a semiconductor high-capacitance capacitor structure, the epitaxial barrier layer is an Al X Ga 1-X N epitaxial barrier layer.

[0016] As a preferred option, a manufacturing method of a semiconductor high-capacitance capacitor structure, the thickness of the epitaxial barrier layer is 10nm-100nm.

[0017] As a preferred option, a manufacturing method of a semiconductor high-capacitance capacitor structure, the first dielectric layer is a SiN X dielectric layer.

[0018] As a preferred option, a manufacturing method of a semiconductor high-capacitance capacitor structure, the second dielectric layer is a SiN X dielectric layer.

[0019] As a preferred option, a manufacturing method of a semiconductor high-capacitance capacitor structure, a back metallization hole is made below the epitaxial channel layer corresponding to the negative electrode.

[0020] As a preferred option, a manufacturing method of a semiconductor high-capacitance capacitor structure, the isolation region is a square ring.

[0021] It should be further explained that the technical features corresponding to the above options can be combined or replaced with each other to form new technical solutions without conflict.

[0022] Compared with the prior art, the present application has the following advantages:

[0023] (1) The present application realizes the lead-out of integrated capacitors by taking the two-dimensional electron gas of the semiconductor epitaxial layer as the internal electrode of the capacitor, and realizes the large specific capacitance on-chip capacitor by taking the extremely thin semiconductor inversion layer as the dielectric; the two-dimensional electron gas realizes the lateral lead-out of the capacitor electrode, maintains the lattice order and ideality of the inversion layer dielectric, has high breakdown strength and high voltage resistance; at the same time, the parasitic inductance is small without off-chip interconnection; and since the capacitor upper electrode (negative electrode) and the inversion layer are in Schottky contact, it has polarity.

[0024] (2) The manufacturing method of the present application is compatible with most compound semiconductor processes, easy to integrate, especially suitable for GaN process, without increasing masks, increasing processes or adjusting process sequence, low cost.

[0025] (3) The capacitor structure manufactured by the present application realizes 1500pF / mm 2 The specific capacitance value above.

[0026] (4) In one example, the capacitor structure of the present application can further improve the specific capacitance in combination with other ways, for example, a back metallization hole is made below the epitaxial layer corresponding to the negative electrode, to realize a bypass capacitor with larger specific capacitance, which has higher practical application value. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 A flow chart of a manufacturing method of a semiconductor large-capacitance capacitor structure is shown for an embodiment of the present application;

[0028] Figure 2 A schematic diagram of manufacturing an ohmic contact of a positive electrode is shown for an embodiment of the present application;

[0029] Figure 3 A schematic diagram of manufacturing an isolation region is shown for an embodiment of the present application;

[0030] Figure 4 A schematic diagram of depositing a first dielectric layer and etching to manufacture a Schottky contact is shown for an embodiment of the present application;

[0031] Figure 5 A schematic diagram of depositing a second dielectric layer and etching a window is shown for an embodiment of the present application;

[0032] Figure 6 A schematic diagram of a semiconductor large-capacitance capacitor structure is shown for an embodiment of the present application;

[0033] Figure 7 A schematic diagram of an effective capacitor composition is shown for an embodiment of the present application;

[0034] Figure 8 A schematic diagram of the width of a negative electrode is shown for an embodiment of the present application;

[0035] Figure 9 A schematic diagram of a capacitor structure combined with a back metallization hole is shown for an embodiment of the present application.

[0036] In the figure: 1, substrate; 2, epitaxial channel layer; 3, epitaxial barrier layer; 4, two-dimensional electron gas; 5, isolation region; 6, ohmic contact of positive electrode; 7, first dielectric layer; 8, negative electrode; 9, second dielectric layer; 10, deposited metal; 11, back metallization hole. DETAILED DESCRIPTION

[0037] The technical solutions of the present application will be described clearly and completely below in conjunction with the drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0038] In the description of the present application, it should be noted that the directions or positional relationships indicated by "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like are described based on the directions or positional relationships described in the drawings, which are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In addition, "first", "second" are only for the purpose of description and cannot be understood as indicating or implying relative importance.

[0039] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, "mounting", "connection" and "connection" should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above-mentioned terms in the present application can be understood according to the specific circumstances.

[0040] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0041] In an exemplary embodiment, a manufacturing method of a semiconductor large-capacitance capacitor structure is provided, as shown in the accompanying drawings, the method comprises: Figure 1 As shown in the accompanying drawings, the method comprises:

[0042] S1, a substrate 1 is made, and an epitaxial channel layer 2 and an epitaxial barrier layer 3 are sequentially made on the substrate 1, and a two-dimensional electron gas 4 is formed at the interface of the epitaxial channel layer 2 and the epitaxial barrier layer 3;

[0043] S2, as shown in the accompanying drawings, an ohmic contact 6 of the positive electrode is made on the epitaxial channel layer 2; Figure 2 S3, as shown in the accompanying drawings, an isolation region 5 is made, and the isolation region 5 penetrates through the epitaxial channel layer 2 and extends into the substrate 1;

[0044] Figure 3 S4, as shown in the accompanying drawings, a negative electrode is made on the isolation region 5;

[0045] S5, as shown in the accompanying drawings, a dielectric layer 7 is made on the negative electrode, and a via hole 8 is made in the dielectric layer 7, and the via hole 8 is filled with a conductive material to form a conductive via 9; and Figure 4 ​As shown, a first dielectric layer 7 is deposited on the epitaxial barrier layer 3, and a Schottky contact is etched in the first dielectric layer 7 to form a negative electrode 8;

[0046] S5、as Figure 5 As shown, a second dielectric layer 9 is deposited on the first dielectric layer 7, a window is etched at a position corresponding to the ohmic contact 6 of the positive electrode, and a metal 10 is deposited at the window to lead out the positive electrode, the deposited metal 10 extends to cover the second dielectric layer 9, and a capacitor structure as shown in Figure 6 is obtained.

[0047] In the capacitor structure, the two-dimensional electron gas 4 is used as an internal electrode of the capacitor to realize lateral leading-out of the electrode, and the thin-layer epitaxial barrier layer 3 in the reverse type is selected as a dielectric layer of the capacitor.

[0048] Specifically, according to common sense, two plates constituting a capacitor are generally metal. According to a single-layer capacitor formula, in the case of limited area and selected material, only the thickness of the dielectric can be reduced to realize a large capacitance value.

[0049] C = εS / d

[0050] In the formula, C represents a capacitance value, ε represents a dielectric constant of the dielectric, S represents an area of a single-layer capacitor, and d represents a thickness of the dielectric.

[0051] However, thinning of the dielectric thickness means a decrease in breakdown strength. There are two traditional methods for semiconductor process to make a capacitor: MIM capacitor with single-layer dielectric and semiconductor capacitor with metal-semiconductor contact. Deposition of the dielectric on the metal cannot form a single-crystal structure, but only a polycrystalline dielectric layer full of grain boundaries. Therefore, the MIM capacitor can only increase the thickness of the polycrystalline dielectric layer to improve the voltage resistance, but cannot maintain both thinness and voltage resistance, which means a limited specific capacitance; the semiconductor capacitor is realized by using a very thin reverse layer at the metal-semiconductor interface. Since the reverse layer can be very thin, the specific capacitance is relatively large. However, in order to lead out the capacitor, the electrode on the semiconductor side of the capacitor is led out from the vertical direction by semiconductor doping. Due to impurity diffusion, the reverse layer has low voltage resistance.

[0052] The application uses the two-dimensional electron gas 4 as an internal electrode of the capacitor to realize lateral leading-out of the integrated capacitor, maintains lattice order and ideality (without doping) of the reverse layer, and thus has high breakdown strength. The very thin reverse layer (epitaxial barrier layer 3) is beneficial to realization of a single-layer capacitor with large specific capacitance. Since there is a Schottky contact between the upper electrode (negative electrode 8) of the capacitor and the reverse layer, the capacitor has polarity. The ohmic contact 6 and the Schottky contact of the positive electrode are both metal.

[0053] Further, as shown in Figure 7As shown, the effective capacitance of this capacitor structure consists of three parts: C1, formed by the projected area of ​​the negative electrode and the two-dimensional electron gas 4; C2, formed by the projected area of ​​the negative electrode and the positive electrode; and C3, formed by the ohmic contact 6 between the negative electrode and the positive electrode. That is, C = C1 + C2 + C3, where C1 is the main component of C.

[0054] In one example, such as Figure 8 As shown, the negative electrode 8 has a long strip structure. Specifically, the negative electrode 8 should preferably have a long strip structure, that is, the width W should not be too large. The capacitance value should be increased by increasing the length as much as possible, otherwise the capacitance Q value will be severely reduced.

[0055] In one example, the substrate 1 is preferably a silicon carbide substrate, the epitaxial channel layer 2 is a GaN epitaxial channel layer, and the epitaxial barrier layer 3 is preferably Al. X Ga 1-X N-eptaxial barrier layer, wherein the first dielectric layer 7 is preferably SiN. X The dielectric layer, wherein the second dielectric layer 9 is preferably SiN X Dielectric layer. It should be noted that the selection of each layer structure is only a preferred option and is not interpreted as a limitation on the structure of each layer. In practice, any material can be selected according to specific needs.

[0056] The thickness of the epitaxial barrier layer 3 should meet the voltage withstand requirements of the capacitor design, and is generally determined based on the compatible GaN process. Specifically, the thickness of the epitaxial barrier layer 3 is 10nm to 100nm, and Al... X The content is between 15% and 35%. The fabrication method of this invention is compatible with most compound semiconductor processes, is easy to integrate, and is especially suitable for GaN processes. It does not require additional masks, additional steps, or adjustments to the process sequence, and is low in cost.

[0057] In one example, the capacitor structure of the present invention can be combined with other methods to further improve the specific capacitance, such as... Figure 9 As shown, a back-side metallized via 11 is formed below the epitaxial channel layer 2 corresponding to the negative electrode 8. This is used to achieve a bypass capacitor with a larger specific capacitance, and has high practical application value.

[0058] In one example, the isolation region 5 is a square ring shape. The specific shape and size of the isolation region 5 are designed according to actual needs. The isolation region design should isolate the ohmic region and Schottky contact region of the electrode from the outside to prevent accidental interconnection (unless it is intentional), while not isolating these regions of the capacitor into different areas. The width of the isolation region 5 should meet the voltage withstand requirements of the capacitor design.

[0059] The above detailed description of the application is not intended to limit the application to the specific embodiments described, but is intended to cover all alternatives that fall within the scope of the application.

Claims

1. A method of manufacturing a semiconductor high-capacitance capacitor structure, characterized by, The method comprises: S1, making a substrate (1), and sequentially making an epitaxial channel layer (2) and an epitaxial barrier layer (3) on the substrate (1), and forming a two-dimensional electron gas (4) at the interface of the epitaxial channel layer (2) and the epitaxial barrier layer (3); S2, making an ohmic contact (6) of a positive electrode on the epitaxial channel layer (2); S3, making an isolation region (5) which penetrates through the epitaxial channel layer (2) and extends into the substrate (1); S4, depositing a first dielectric layer (7) on the epitaxial barrier layer (3), etching in the first dielectric layer (7), making a Schottky contact, and forming a negative electrode (8); S5, depositing a second dielectric layer (9) on the first dielectric layer (7), etching a window at a position corresponding to the ohmic contact (6) of the positive electrode, and depositing a metal (10) at the window to lead out the positive electrode, the deposited metal (10) extending and covering on the second dielectric layer (9); Wherein, the two-dimensional electron gas (4) is used as an internal electrode of a capacitor to realize lateral leading-out of the electrode, and a thin-layer epitaxial barrier layer (3) in a reverse type is selected as a capacitor dielectric layer.

2. The method for manufacturing a semiconductor large-capacitance capacitor structure according to claim 1, characterized in that, The negative electrode (8) is in a long strip structure.

3. The method for manufacturing a semiconductor large-capacitance capacitor structure according to claim 1, characterized in that, The substrate (1) is a silicon carbide substrate.

4. The method for manufacturing a semiconductor large-capacitance capacitor structure according to claim 1, characterized in that, The epitaxial channel layer (2) is a GaN epitaxial channel layer.

5. The method for manufacturing a semiconductor large-capacitance capacitor structure according to claim 1, characterized in that, The epitaxial barrier layer (3) is Al X Ga 1-X N epitaxial barrier layer.

6. The method for manufacturing a semiconductor large-capacitance capacitor structure according to claim 5, characterized in that, The thickness of the epitaxial barrier layer (3) is 10-100 nm.

7. The method for manufacturing a semiconductor large-capacitance capacitor structure according to claim 5, characterized in that, The first dielectric layer (7) is SiN X Dielectric layer.

8. The method for manufacturing a semiconductor large-capacitance capacitor structure according to claim 7, characterized in that, The second dielectric layer (9) is SiN X Dielectric layer.

9. The method for manufacturing a semiconductor large-capacitance capacitor structure according to claim 1, characterized in that, A back metallization hole (11) is made below the epitaxial layer (2) corresponding to the negative electrode (8).

10. The method for manufacturing a semiconductor large-capacitance capacitor structure according to claim 1, characterized in that, The isolation region (5) is in a square ring shape.

Images