A heterojunction bipolar transistor and its fabrication method

Abstract

This invention discloses a heterojunction bipolar transistor and its fabrication method. The heterojunction bipolar transistor includes, from bottom to top, a substrate, a sub-collector region, a tunneling structure, a collector region, a base region, an emitter region, an emitter capping layer, and an ohmic contact layer. The tunneling structure comprises alternating layers of first and second conductivity types of ion doped layers. According to the heterojunction bipolar transistor and its fabrication method provided by this invention, by forming a tunneling structure composed of alternating layers of first and second conductivity types of ion doped layers between the sub-collector region and the collector region, an etch stop layer is no longer formed. The tunneling junction capacitance (Ctj) is connected in series with the collector junction capacitance (Cbc), reducing the equivalent capacitance and improving device performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a heterojunction bipolar transistor and its fabrication method. Background Technology

[0002] Heterojunction bipolar transistors (HBTs) have advantages such as high power density, high gain, low phase noise, good linearity, small chip area, and low manufacturing cost, and are widely used in radio frequency devices in mobile phones, optical communication systems, and radar systems.

[0003] Existing heterojunction bipolar transistors (HBTs) consist of a sub-collector region, an etch stop layer, a collector region, a base region, an emitter region, an emitter capping layer, and an ohmic contact layer deposited sequentially from bottom to top on a semi-insulating substrate. Typically, a gradient-doped collector region is used. Increasing the doping concentration of the sub-collector region reduces the sheet resistance of the sub-collector region and the ohmic contact resistance of the collector, thereby reducing the knee voltage. Furthermore, since the etch stop layer is typically made of InGaP, unlike the GaAs used in the sub-collector and collector regions, the InGaP / GaAs interface has a potential barrier, which increases parasitic resistance and degrades device characteristics.

[0004] Therefore, it is necessary to propose a new heterojunction bipolar transistor and its fabrication method to solve the above problems. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] This invention provides a heterojunction bipolar transistor, which includes, from bottom to top, a substrate, a sub-collector region, a tunneling structure, a collector region, a base region, an emitter region, an emitter capping layer, and an ohmic contact layer;

[0007] The tunneling structure includes alternating layers of first and second conductivity-type ion doped layers.

[0008] Furthermore, the first conductivity type ion doped layer is an N-type ion doped layer, and the dopant ion of the N-type ion doped layer is a tellurium ion.

[0009] Furthermore, the doped ions in the sub-current collector region are tellurium ions.

[0010] Furthermore, the tunneling structure comprises, from bottom to top, an N-type ion-doped layer and a P-type ion-doped layer.

[0011] Furthermore, the current collector region is doped with N-type ions, and the tunneling structure includes, from bottom to top, an N-type ion doped layer, a P-type ion doped layer, and an N-type ion doped layer.

[0012] Furthermore, the sub-collector region, the tunneling structure, and the collector region are made of the same material.

[0013] Furthermore, the doping concentration range of tellurium ions in the first conductivity type ion-doped layer is: the doping concentration range of tellurium ions in the sub-current collector region is: 5e18cm -3 ~1e20cm -3 .

[0014] This invention also provides a method for fabricating a heterojunction bipolar transistor, comprising the following steps:

[0015] Provide substrate;

[0016] A sub-current collector region is formed on the substrate;

[0017] A tunneling structure is formed on the sub-current collector region, the tunneling structure comprising alternating layers of first conductivity type ion doping and second conductivity type ion doping;

[0018] A current collector region, a base region, a transmitter region, a transmitter region capping layer, and an ohmic contact layer are sequentially formed on the tunnel structure.

[0019] Furthermore, after forming the sub-current collector region on the substrate, the method further includes a step of doping the sub-current collector region with tellurium ions.

[0020] Furthermore, forming the tunnel structure includes the following steps:

[0021] An N-type ion doped layer and a P-type ion doped layer are formed sequentially from bottom to top;

[0022] or,

[0023] From bottom to top, N-type ion doping layer, P-type ion doping layer and N-type ion doping layer are formed sequentially.

[0024] According to the heterojunction bipolar transistor and its fabrication method provided by the present invention, a tunneling structure consisting of alternating first conductivity type ion doped layers and second conductivity type ion doped layers is formed between the sub-collector region and the collector region, and an etch stop layer is no longer formed. The tunneling junction capacitance (Ctj) is connected in series with the collector junction capacitance (Cbc), the equivalent capacitance is reduced, and the performance of the device is improved. Attached Figure Description

[0025] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0026] In the attached image:

[0027] Figure 1A A schematic diagram of a heterojunction bipolar transistor according to an embodiment of the present invention is shown;

[0028] Figure 1B A schematic diagram of a heterojunction bipolar transistor according to another embodiment of the present invention is shown;

[0029] Figure 2 A schematic diagram of the equivalent circuit structure of a heterojunction bipolar transistor according to an embodiment of the present invention is shown;

[0030] Figure 3 A schematic flowchart illustrating a method for fabricating a heterojunction bipolar transistor according to an embodiment of the present invention is shown. Detailed Implementation

[0031] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0032] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0033] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0034] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0035] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0036] To fully understand this invention, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0037] Existing heterojunction bipolar transistors (HBTs) consist of a sub-collector region, an etch stop layer, a collector region, a base region, an emitter region, an emitter capping layer, and an ohmic contact layer deposited sequentially from bottom to top on a semi-insulating substrate. Typically, a gradient-doped collector region is used. Increasing the doping concentration of the sub-collector region reduces the sheet resistance of the sub-collector region and the ohmic contact resistance of the collector, thereby reducing the knee voltage. Furthermore, since the etch stop layer is typically made of InGaP, unlike the GaAs used in the sub-collector and collector regions, the InGaP / GaAs interface has a potential barrier, which increases parasitic resistance and degrades device characteristics.

[0038] To address the above problems, this invention provides a heterojunction bipolar transistor, such as... Figure 1A As shown in 1B, the heterojunction bipolar transistor includes, from bottom to top, a substrate 100, a sub-collector region 110, a tunneling structure 120, a collector region 130, a base region 140, an emitter region 150, an emitter capping layer 160, and an ohmic contact layer 170; wherein, the tunneling structure 120 includes alternating first conductivity type ion doped layers 121 and second conductivity type ion doped layers 122.

[0039] In one embodiment, the first conductivity type ion doped layer 121 is an N-type ion doped layer, and the second conductivity type ion doped layer 122 is a P-type ion doped layer.

[0040] Reference Figure 2 According to the equivalent circuit of the heterojunction bipolar transistor provided by the present invention, the collector junction capacitance (Cbc) 210 and the tunnel junction capacitance (Ctj) 220 are connected in series, the equivalent capacitance is reduced, which is beneficial to high frequency characteristics and improves the performance of the device.

[0041] For example, the sub-collector region 110, the tunnel structure 120, and the collector region 130 are made of the same material.

[0042] By using the same material for the sub-collector region 110, tunnel structure 120, and collector region 130, the potential barrier at the GaAs / InGaP interface caused by using different materials (e.g., using InGaP for the etch stop layer and GaAs for the sub-collector region 110 and / or collector region 130) is avoided, thus preventing the increase of parasitic resistance and optimizing device characteristics. At the same time, the inconvenience caused by the similar etch selectivity ratios of GaAs and InGaP in controlling the process window and device consistency is avoided.

[0043] The substrate 100 can be any suitable semiconductor material known to those skilled in the art, such as germanium, silicon, GaAs, or combinations thereof. The substrate 100 is semi-insulating in conductivity, specifically selected according to the type of device to be fabricated. In one embodiment, the substrate 100 can be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). As an example, in this embodiment, the substrate 100 is constructed from GaAs or InP.

[0044] In one embodiment, the sub-collector region 110 is a GaAs layer. Further, the dopant ions in the sub-collector region 110 are tellurium (Te) ions, and the doping concentration of the Te ions is 5e18cm⁻¹. -3 ~1e20cm -3 The thickness of the sub-collector region 110 ranges from 300 nm to 1000 nm.

[0045] In one embodiment, the first conductivity type ion-doped layer 121 of the tunneling structure 120 is a GaAs layer. Further, the dopant ions in the first conductivity type ion-doped layer 121 are Te ions, and the doping concentration of the Te ions is 5e18cm⁻¹. -3 ~1e20cm -3 The thickness of the first conductive ion-doped layer 121 ranges from 10 nm to 30 nm.

[0046] In one embodiment, the second conductivity type ion-doped layer 122 of the tunneling structure 120 is a GaAs layer. Further, the doping ions of the second conductivity type ion-doped layer 122 include, but are not limited to, C or Mg ions, wherein the C ion doping concentration is 5e19cm⁻¹. -3 ~1e20 cm -3 The thickness of the second conductive type ion-doped layer 122 ranges from 5 nm to 20 nm.

[0047] In one embodiment, the collector region 130 is a GaAs layer. Further, the doped ions in the collector region 130 include, but are not limited to, silicon ions, wherein the silicon ion doping concentration is 5e15cm⁻¹. -3 ~3e16cm -3 The thickness of the current collector region 130 ranges from 500 nm to 1000 nm.

[0048] By using Te ions as dopants in the first conductivity type ion-doped layer 121, the n-type carrier concentration reaches 1e⁻¹. 19 / cm 3The above measures effectively reduce the parasitic resistance and contact resistance of the collector, thereby improving the device characteristics. At the same time, Te ions have low diffusion and low deactivation rate, which can maintain a high concentration of activated carriers even under high temperature conditions, thereby improving the reliability of the device.

[0049] By using Te ions as dopants in the sub-collector region 110, dry etching ends with Te ions, which facilitates the definition of etching depth. At the same time, the Te ion doping in the sub-collector region 110 increases the carrier concentration and effectively reduces the collector contact resistance.

[0050] like Figure 1A As shown, the tunneling structure 120 includes an N-type ion doped layer and a P-type ion doped layer from bottom to top.

[0051] Since the sub-catch region 110 is doped with N-type ions, placing the N-type ion doped layer in the tunneling structure 120 adjacent to the sub-catch region 110 can further reduce the interface barrier between the tunneling structure 120 and the sub-catch region 110, reduce parasitic resistance, and improve device performance.

[0052] like Figure 1B As shown, the tunneling structure 120 includes, from bottom to top, an N-type ion doped layer, a P-type ion doped layer, and an N-type ion doped layer.

[0053] Since both the sub-collector region 110 and the collector region 130 are N-type ion doped, two N-type ion doped layers are provided in the tunneling structure 120, and the two N-type ion doped layers are respectively arranged adjacent to the sub-collector region 110 and the collector region 130, which further reduces the interface barrier between the tunneling structure 120 and the sub-collector region 110 and the collector region 130, reduces parasitic resistance, and improves device performance.

[0054] For example, the heterojunction bipolar transistor further includes a base region 140, an emitter region 150, an emitter capping layer 160, and an ohmic contact layer 170.

[0055] In one embodiment, the base region 140 is a GaAs layer doped with p-type ions. In one embodiment, the dopant ions in the base region 140 include, but are not limited to, C ions, wherein the doping concentration of the C ions is 2e19cm⁻¹. -3 ~5e19cm -3 The thickness of the base region 140 ranges from 40 nm to 100 nm;

[0056] In one embodiment, the emitter region 150 is an InGaP layer doped with N-type ions. In one embodiment, the dopant ions in the emitter region 150 include, but are not limited to, silicon ions, wherein the silicon ion doping concentration is 2e17cm⁻¹. -3 ~1e18cm -3 The thickness of the emission region 150 ranges from 40 nm to 100 nm;

[0057] In one embodiment, the emitter capping layer 160 is a GaAs layer doped with N-type ions. In one embodiment, the dopant ions of the emitter capping layer 160 include, but are not limited to, silicon ions, wherein the doping concentration of the silicon ions is 1e18cm⁻¹. -3 ~5e18cm -3 The thickness of the emission region capping layer 160 ranges from 80 nm to 200 nm.

[0058] In one embodiment, the ohmic contact layer 170 is an InGaAs layer. In one embodiment, the doping ions of the ohmic contact layer 170 include, but are not limited to, silicon ions, wherein the doping concentration of the silicon ions is 1e19cm⁻¹. -3 ~1e20cm -3 The thickness of the ohmic contact layer 170 ranges from 50 nm to 150 nm.

[0059] This invention also provides a method for fabricating a heterojunction bipolar transistor, such as... Figure 3 As shown, the steps include:

[0060] Step S310: Provide a substrate;

[0061] Step S320: Form a sub-collector region on the substrate;

[0062] Step S330: A tunneling structure is formed on the sub-collector region, the tunneling structure comprising alternating layers of first conductivity type ion doping and second conductivity type ion doping;

[0063] Step S340: A current collector region, a base region, a transmitter region, a transmitter region capping layer, and an ohmic contact layer are sequentially formed on the tunneling structure.

[0064] First, execute step S310, referring to... Figure 1A As shown in 1B, a substrate 100 is provided.

[0065] The substrate 100 can be any suitable semiconductor material known to those skilled in the art, such as germanium or silicon, or combinations thereof. The conductivity type of the substrate 100, such as N-type or P-type, is selected appropriately based on the type of device to be fabricated. In one embodiment, the substrate 100 can be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). As an example, in this embodiment, the substrate 100 is constructed from GaAs or InP.

[0066] Next, proceed to step S320, referring to... Figure 1A As shown in 1B, a sub-collector region 120 is formed on the substrate 100.

[0067] In one embodiment, the sub-collector region 110 is a GaAs layer, and the thickness of the sub-collector region 110 ranges from 50 nm to 200 nm. The sub-collector region 110 can be formed using any existing technology familiar to those skilled in the art, preferably chemical vapor deposition (CVD), such as low-temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), thermally rapid chemical vapor deposition (RTCVD), and plasma-enhanced chemical vapor deposition (PECVD). Taking the GaAs layer as an example, metal-organic chemical vapor deposition (MOCVD) is preferably used as the growth process, with TMGa, TMIn, AsH3, and PH3 as the growth source, a growth temperature of 600°C to 800°C, and a reaction chamber pressure of 50 mbar to 800 mbar.

[0068] Furthermore, the doping source for the sub-collector region 110 is diethyltellurium, and the doping concentration of the Te ions is 5e18cm. -3 ~1e20cm -3 .

[0069] By using Te ions as dopants in the sub-collector region 110, dry etching ends with Te ions, which facilitates the definition of etching depth. At the same time, the Te ion doping in the sub-collector region 110 increases the carrier concentration and effectively reduces the collector contact resistance.

[0070] Next, proceed to step S330, referring to... Figure 1A As shown in 1B, a tunneling structure 120 is formed on the sub-collector region 110, the tunneling structure 120 including alternating first conductivity type ion doped layers 121 and second conductivity type ion doped layers 122.

[0071] In one embodiment, the first conductivity type ion-doped layer 121 of the tunneling structure 120 is a GaAs layer, and the thickness of the first conductivity type ion-doped layer 121 ranges from 10 nm to 30 nm. The method for forming the first conductivity type ion-doped layer 121 can employ any existing technology familiar to those skilled in the art, and will not be elaborated here.

[0072] Furthermore, the dopant ions of the first conductivity type ion-doped layer 121 are Te ions, and the doping concentration of the Te ions is 5e18cm. -3 ~1e20cm -3 In one embodiment, the ions implanted into the first conductivity type ion-doped layer 121 include Te ions, and the doping source is diethyltellurium.

[0073] By using Te ions as dopants in the first conductivity type ion-doped layer 121, the n-type carrier concentration reaches 1e⁻¹. 19 / cm 3 The above measures effectively reduce the parasitic resistance and contact resistance of the collector, thereby improving the device characteristics. At the same time, Te ions have low diffusion and low deactivation rate, which can maintain a high concentration of activated carriers even under high temperature conditions, thereby improving the reliability of the device.

[0074] In one embodiment, the second conductivity type ion-doped layer 122 of the tunneling structure 120 is a GaAs layer, and the thickness of the second conductivity type ion-doped layer 122 ranges from 5 nm to 20 nm. The method for forming the second conductivity type ion-doped layer 122 can employ any existing technology familiar to those skilled in the art, and will not be elaborated here.

[0075] Furthermore, the doping ions of the second conductivity type ion-doped layer 122 include, but are not limited to, C or Mg ions, wherein the doping concentration of the C ions is 2e19cm⁻¹. -3 ~5e19cm -3 In one embodiment, the ions doped into the second conductivity type ion-doped layer 122 include C ions, and the doping source is CBr4 or CCl4.

[0076] Next, proceed to step S340, referring to... Figure 1A As shown in 1B, a collector region 130, a base region 140, a transmitter region 150, a transmitter region capping layer 160, and an ohmic contact layer 170 are sequentially formed on the tunneling structure 120.

[0077] In one embodiment, the collector region 130 is a GaAs layer. The base region 140 is a GaAs layer doped with p-type ions. The emitter region 150 is an InGaP layer doped with n-type ions. The emitter capping layer 160 is a GaAs layer doped with n-type ions. The ohmic contact layer 170 is an InGaAs layer. The methods for forming the collector region 130, base region 140, emitter region 150, emitter capping layer 160, and ohmic contact layer 170 can employ any existing technology familiar to those skilled in the art, and will not be elaborated upon here.

[0078] For example, the sub-collector region 110, the tunnel structure 120, and the collector region 130 are made of the same material.

[0079] By using the same material for the sub-collector region 110, tunnel structure 120, and collector region 130, the potential barrier at the GaAs / InGaP interface caused by using different materials (e.g., using InGaP for the etch stop layer and GaAs for the sub-collector region 110 and / or collector region 130) is avoided, thus preventing the increase of parasitic resistance and optimizing device characteristics. At the same time, the inconvenience caused by the similar etch selectivity ratios of GaAs and InGaP in controlling the process window and device consistency is avoided.

[0080] like Figure 1A As shown, the tunneling structure 120 includes an N-type ion doped layer and a P-type ion doped layer from bottom to top.

[0081] Since the sub-catch region 110 is doped with N-type ions, placing the N-type ion doped layer in the tunneling structure 120 adjacent to the sub-catch region 110 can further reduce the interface barrier between the tunneling structure 120 and the sub-catch region 110, reduce parasitic resistance, and improve device performance.

[0082] like Figure 1B As shown, the tunneling structure 120 includes, from bottom to top, an N-type ion doped layer, a P-type ion doped layer, and an N-type ion doped layer.

[0083] Since both the sub-collector region 110 and the collector region 130 are N-type ion doped, two N-type ion doped layers are provided in the tunneling structure 120, and the two N-type ion doped layers are respectively arranged adjacent to the sub-collector region 110 and the collector region 130, which further reduces the interface barrier between the tunneling structure 120 and the sub-collector region 110 and the collector region 130, reduces parasitic resistance, and improves device performance.

[0084] This concludes the introduction of the key steps in the fabrication method of the heterojunction bipolar transistor of the present invention. Further processes may be required for the complete device fabrication, which will not be elaborated here.

[0085] According to the heterojunction bipolar transistor and its fabrication method provided by the present invention, a tunneling structure consisting of alternating first conductivity type ion doped layers and second conductivity type ion doped layers is formed between the sub-collector region and the collector region, and an etch stop layer is no longer formed. The tunneling junction capacitance (Ctj) is connected in series with the collector junction capacitance (Cbc), the equivalent capacitance is reduced, and the performance of the device is improved.

[0086] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the present invention is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of the present invention, all of which fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A heterojunction bipolar transistor, characterized in that, It includes, from bottom to top, a substrate, a sub-collector region, a tunneling structure, a collector region, a base region, an emitter region, an emitter capping layer, and an ohmic contact layer; The tunneling structure includes alternating layers of a first type of conductive ion doping and a second type of conductive ion doping. The first type of conductive ion doping layer is an N-type ion doping layer, and the dopant ion in the N-type ion doping layer is a tellurium ion.

2. The heterojunction bipolar transistor as described in claim 1, characterized in that, The doped ions in the sub-current collector region are tellurium ions.

3. The heterojunction bipolar transistor as described in claim 2, characterized in that, The tunneling structure comprises, from bottom to top, an N-type ion-doped layer and a P-type ion-doped layer.

4. The heterojunction bipolar transistor as described in claim 2, characterized in that, The current collector region is doped with N-type ions, and the tunneling structure includes, from bottom to top, an N-type ion doped layer, a P-type ion doped layer, and an N-type ion doped layer.

5. The heterojunction bipolar transistor as described in claim 1, characterized in that, The sub-collector region, the tunnel structure, and the collector region are made of the same material.

6. The heterojunction bipolar transistor as described in claim 2, characterized in that, The doping concentration of tellurium ions in the first conductive type ion-doped layer ranges from 5e18cm -3 1e20cm -3 ; The doping concentration of tellurium ions in the sub-collector region ranges from 5e18cm. -3 ~ 1e20cm -3 .

7. A method for fabricating a heterojunction bipolar transistor, characterized in that, Including the following steps: Provide substrate; A sub-current collector region is formed on the substrate; A tunneling structure is formed on the sub-current collector region, the tunneling structure comprising alternating layers of first conductivity type ion doping and second conductivity type ion doping; A current collector region, a base region, a transmitter region, a transmitter region capping layer, and an ohmic contact layer are sequentially formed on the tunneling structure. Wherein, the first conductivity type ion doped layer is an N-type ion doped layer, and the dopant ion of the N-type ion doped layer is a tellurium ion.

8. The manufacturing method as described in claim 7, characterized in that, After forming the sub-current collector region on the substrate, the method further includes a step of doping the sub-current collector region with tellurium ions.

9. The manufacturing method as described in claim 8, characterized in that, The steps for forming the tunnel structure are as follows: An N-type ion doped layer and a P-type ion doped layer are formed sequentially from bottom to top; or, From bottom to top, N-type ion doping layer, P-type ion doping layer and N-type ion doping layer are formed sequentially.

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