Sram with advanced burst mode address comparator

Abstract

A memory is provided that is configured to implement normal read operations and also to implement burst mode read operations. A burst mode address comparator compares a current row address with a previous row address from a previous read operation to determine whether a read operation is a normal read operation or a burst mode read operation. The burst mode address comparator invokes burst mode even in the presence of intervening write operations to row addresses that are not equal to the previous row address.

Description

[0001] Priority requirements

[0002] This patent application claims priority to non-provisional application number 17 / 008433, filed on August 31, 2020, entitled “SRAM WITH ADVANCED BURSTMODE ADDRESS COMPARATOR”, which has been assigned to the assignee of this application and is expressly incorporated herein by reference. Technical Field

[0003] This application relates to memory, and more specifically to low-power memory with a burst-mode address comparator. Background Technology

[0004] In conventional static random access memory (SRAM), the bit line voltage difference during a read operation is not the full rail, but rather a fraction of the supply voltage. For example, if the supply voltage is 1 volt, the voltage difference might be only 100 millivolts or less. To respond to this relatively small voltage difference and make a bit decision about the contents stored in the bit cell, typical sense amplifiers require relatively large gain, and are therefore unsuitable within the column spacing, causing each sense amplifier to be multiplexed across a set of multiplexed columns. Therefore, burst-mode read operations are not suitable for SRAMs with sense amplifier multiplexing.

[0005] Therefore, there is a need in the art for SRAM with burst mode read operations. Summary of the Invention

[0006] According to a first aspect of this disclosure, a burst-mode address comparator for a memory is provided, the burst-mode address comparator comprising: a latch configured to set a latch output signal in response to a second row address for a write operation being equal to a first row address, the write operation following a first read operation; a first plurality of logic gates configured to assert a bit comparison word in response to a current row address for the memory being equal to the first row address; a first transistor configured to be turned off during each write operation and turned on during each read operation; a second transistor having a first terminal coupled to a burst-mode node for a burst-mode signal and having a second terminal coupled to ground through the first transistor; and a second plurality of logic gates configured to turn on the second transistor to ground the burst-mode node in response to the bit comparison word assertion when the latch output signal is asserted, and to de-turn on the second transistor in response to the bit comparison word assertion when the latch output signal is reset.

[0007] According to a second aspect of this disclosure, a burst-mode method for a memory is provided, comprising: pre-charging a pair of sense nodes for a sense amplifier during a first read operation for a first row in the memory; latching a first signal in the sense amplifier after pre-charging; writing to a second row in the memory during a write operation following the first read operation; and passing the first signal latched in the sense amplifier to a data output latch during a second read operation for the first row following the write operation, without pre-charging the pair of sense nodes during the second read operation and without asserting a word line for the first row during the second read operation.

[0008] According to a third aspect of this disclosure, a memory is disclosed, comprising: word lines; a plurality of columns, each column including: a bit line pair, a bit cell at the intersection of the column and the word line, and a sense amplifier coupled to the bit line pair via a sense node pair; a burst-mode blocking latch configured to set a latch output signal in response to a write operation to the first row address after an initial read operation to the first row address; a burst-mode address comparator configured to determine, in response to the row address of each subsequent read cycle and in response to the latch output signal, whether each subsequent read operation is a burst-mode read operation or a random read operation for a series of subsequent read operations following the initial read operation; and a sense node precharge circuit configured to precharge the sense node pair of each column in each random read operation, and not to precharge the sense node pair of each column in each burst-mode read operation.

[0009] These and additional advantages can be better understood through the following detailed description. Attached Figure Description

[0010] Figure 1 The illustration shows an SRAM including a burst-mode address comparator according to one aspect of the present disclosure, the burst-mode address comparator being used for a burst-mode call operation, even though there are intermediate write operations.

[0011] Figure 2 The illustration shows one aspect of this disclosure. Figure 1 The SRAM was modified so that the column multiplexing is 4:1 multiplexing.

[0012] Figure 3 This is a circuit diagram of an example burst-mode address comparator according to one aspect of this disclosure.

[0013] Figure 4 This is a timing diagram of various random mode reads and burst mode reads with intermediate write operations, according to one aspect of this disclosure.

[0014] Figure 5 This is a flowchart of a burst mode address comparison method according to one aspect of this disclosure, wherein a burst mode still occurs despite the presence of intermediate write operations.

[0015] Figure 6 The illustrations show some example electronic systems according to one aspect of this disclosure, each example electronic system comprising SRAM with burst-mode address comparison.

[0016] The embodiments and advantages of this disclosure can be best understood by referring to the following detailed description. It should be understood that the same reference numerals are used to identify the same elements illustrated in one or more of the figures. Detailed Implementation

[0017] Memory such as SRAM is provided with multiple bit cells arranged according to rows and columns. Each column has a corresponding pair of bit lines. Each row has a corresponding word line. At the intersection of each row and column, there is a corresponding bit cell in the bit cell. Each column includes its own sense amplifier, which latches a bit decision into one bit cell in its bit cell during a random read operation. In a random read operation, the word line of the accessed row is asserted such that the sense amplifier of each column latches a bit decision from the bit cell shared by the column and the accessed row.

[0018] The address comparator controls whether each read operation occurs as a random read or a burst mode read. In either type of read operation, the accessed row is identified by a unique row address. Burst mode follows a random read operation on the row with the first row address. As long as no intermediate write operation points to the same row address, the address comparator invokes burst mode in subsequent read operations pointing to the same row address. Therefore, even if an intermediate write operation occurs targeting other rows, the address comparator will still invoke burst mode.

[0019] The resulting burst mode is also referred to as an advanced burst mode read operation in this paper because the bit decisions latched in the sense amplifier are not discarded even if there are intermediate write operations for other(multiple) rows(s). This is highly advantageous in terms of power saving, as the word line of the accessed row is not asserted during the burst mode read operation. Similarly, the sense amplifier is not pre-charged during the burst mode read operation to further save power.

[0020] The following discussion focuses on a favorable charge-transfer implementation that simplifies the implementation of the sense amplifier. However, it should be understood that any conventional latch sense amplifier can be used, provided each column has its own sense amplifier. As previously mentioned, during read operations (random mode or burst mode), the bit-line voltage difference between the bit-line pairs of a column is not the entire rail, but rather a portion of the supply voltage. Therefore, conventional SRAM sense amplifiers require gain to amplify this portion of the bit-line voltage difference to a “full rail” bit decision equal to the supply voltage or ground. Conventional SRAM sense amplifiers are therefore relatively bulky, necessitating a correspondingly large column pitch to accommodate each column with its own conventional SRAM sense amplifier. The charge transfer disclosed herein allows each column to have a compact sense amplifier, such as a reset-set flip-flop implemented by a pair of cross-coupled logic gates (e.g., a pair of cross-coupled NAND gates).

[0021] Prior to a random read operation, the bit lines for the column are precharged to the memory supply voltage. Then, a clock signal triggers a self-timed clock circuit to assert the word lines for the addressed row. The asserted word lines turn on the access transistors in the bit cells of that row, allowing the bit cells in the addressed row to affect the precharge state of the corresponding bit line pairs. Depending on the binary content of the addressed bit cells, one bit line in each bit line pair is slightly discharged below the memory supply voltage, while the second bit line in each pair remains charged to the memory supply voltage.

[0022] Each column has its own sense amplifier, which latches a bit decision based on the voltage difference formed by the bit line pairs across the column when the word line voltage is asserted. Bit decisions from the sense amplifiers / columns can be arranged into groups of multiplexed columns. Bit cells at the intersection of a word line and a group of multiplexed columns are referred to herein as bit cell groups, such that only the column address differs across bit cell groups. Each group of multiplexed columns includes a column multiplexer that selects from the group's sense amplifiers to drive the corresponding data output latch. The selection by the column multiplexer depends on the column address. Each sense amplifier includes a pair of sense amplifier nodes for coupling to the bit lines of the column during the sense enable period of a random read operation. The sense amplifier nodes are precharged before the random read operation, although this precharge can be a discharge to ground compared to precharging the bit lines to the supply voltage. The random read operation ends with the bit decision from the addressed column latched in the data output latch.

[0023] Whether a sequential read operation is another random read operation or a burst-mode read operation depends in part on whether the address used for the sequential read operation points to the same row. Note that during a random read operation, each sense amplifier in the set of multiplexed columns addressed latches a bit decision for the group of bit cells. If the same row as the row addressed in a previous read operation is addressed, the burst-mode address comparator disclosed herein advantageously invokes burst mode for the sequential read operation, provided that no intermediate write operation to the same row has occurred. In this way, latched bit decisions from the previous random read operation are utilized in the burst-mode read operation without needing to re-assert word lines and even if write operations to other rows exist. Similarly, during a burst-mode read operation, bit lines are not precharged, and sense amplifier nodes are not precharged to reduce power consumption.

[0024] Before the burst mode address comparator invokes burst mode, random read operations should occur so that the sense amplifiers latch their bit decisions. Once a random read operation occurs, burst mode can be invoked repeatedly, as long as the same row as addressed in a previous random read operation is addressed (assuming no intermediate writes to that row). For example, suppose four columns are multiplexed, and the initial random read operation occurs for the first column of the four columns. If successive read operations point to the same row without any intermediate writes to that row, the address comparator activates burst mode. For example, the second column of the four columns can be read in the first burst mode read operation. Then, the third column of the four columns can be read in the second burst mode read operation, and so on. Word lines, bit lines, and sense amplifier nodes are not precharged during burst mode read operations, which significantly reduces power consumption.

[0025] Typically, column addresses are smaller than row addresses because column multiplexing is usually less than the number of rows. For example, in an embodiment with 4:1 column multiplexing, only two address bits are needed to identify the addressed column. In contrast, in an embodiment with 128 rows, the row address would be seven bits to identify the addressed row. Therefore, the following discussion will assume that the row address bits are the most significant bits in the read address, and the column address bits are the least significant bits. In this embodiment, the burst mode address comparator is thus used to determine whether the most significant bit of the read address of the current read operation is equal to the most significant bit of the read address in a previous random read operation. More generally, the burst mode address comparator is used to determine whether the row address portion of the current read address is equal to the row address portion of the previous random read address. If the row addresses are equal, the burst mode address comparator invokes burst mode for the current read cycle. If the row addresses are not equal, the burst mode address comparator does not invoke burst mode for the current read cycle.

[0026] The following discussion will focus on an advantageous charge-transfer embodiment of a burst-mode memory controlled by the burst-mode address comparison disclosed herein. However, it should be understood that the burst-mode address comparison disclosed herein is applicable to any SRAM including a latch sense amplifier per column. In a charge-transfer memory implementation, density is not hampered by the lack of a single sense amplifier multiplexed across multiple columns due to the charge-transfer operation implemented via the control of charge-transfer transistors. Each bit line for a column is coupled to the sense amplifier node of the column's sense amplifier via a corresponding charge-transfer transistor. The source of each charge-transfer transistor is coupled to its bit line, and the drain of each charge-transfer transistor is coupled to its sense amplifier node. Therefore, the gate-to-source voltage for each charge-transfer transistor is determined by its gate voltage and its bit line voltage. The following discussion will assume that each charge-transfer transistor is a p-type metal-oxide-semiconductor (PMOS) transistor; however, it should be understood that charge transfer can also be accomplished using n-type metal-oxide-semiconductor (NMOS) transistors.

[0027] Before word line assertion for the initial random read operation, the bit lines are precharged to the supply voltage, while the sense amplifier nodes are fully discharged. The word lines are then asserted during a word line assertion period, during which a bit line voltage difference is formed for each bit line pair, depending on the bit stored in each bit cell at the intersection of the word line and the bit line pairs used for a set of multiplexed columns. Depending on this bit, the true bit line or complementary bit line in each bit line pair is slightly discharged from the precharged state (supply voltage). The resulting bit line voltage difference is not the full rail, but a portion of the supply voltage (e.g., approximately 100 mV). Traditionally, a high-gain sense amplifier is required to form a bit decision from this relatively small bit line difference. Such a high-gain sense amplifier requires a large amount of die space, and therefore it is typically multiplexed across a set of columns. However, the charge transfer technique discussed in this paper results in an amplification of the bit line voltage difference across sense node pairs of bit line pairs. Because of this amplification, the resulting sense amplifier does not require high gain and can instead be implemented using relatively dense reset-set (RS) latches with relatively low power consumption. Therefore, each column can have its own sense amplifier.

[0028] Charge transfer occurs during a charge transfer period that begins near the end of the word line assertion period. Prior to the charge transfer period, the gate voltage of each charge transfer transistor is maintained at the supply voltage, causing each charge transfer transistor to be off. The charge transfer period is delayed relative to the word line assertion, allowing a bit line voltage difference to be formed for each bit line pair. During the charge transfer period, the gate voltage of the charge transfer transistor decreases from the supply voltage toward ground at a certain switching rate. For example, a relatively small inverter or dummy bit line voltage can be used to control the gate voltage of the charge transfer transistor. Depending on the bit value being read, the true bit line or complementary bit line in each bit line pair will decrease slightly from its pre-charge state (supply voltage). This bit line is referred to as a partially charged bit line in the following discussion. However, the remaining bit lines in each bit line pair will remain charged to the supply voltage. This bit line is referred to as a fully charged bit line in the following discussion.

[0029] During the charge transfer period, the gate voltage of each charge transfer transistor in a set of multiplexed columns decreases such that the gate-to-source voltage (gate-to-bit voltage) of the charge transfer transistor for a fully charged bit line meets its threshold voltage. However, the decrease in voltage of a partially charged bit line causes this same gate voltage to no longer meet the threshold voltage of the charge transfer transistor for that bit line. Therefore, only the charge transfer transistor for the fully charged bit line in the bit line pair will initially conduct charge to its sensing node. The capacitance of the sensing node can be relatively small compared to the capacitance of the bit line, so the resulting charge transfer brings the sensing node close to being charged to the supply voltage. In contrast, the sensing node for the partially discharged bit line remains in its discharged default state, such that the voltage difference between the sensing nodes for the accessed bit line pair is close to full rail (the voltage difference is close to equal to the supply voltage). Therefore, the charge transfer causes the relatively small bit line voltage difference to be amplified to a near full rail voltage difference on the sensing node, allowing the sensing amplifier to be a relatively compact and low-power RS ​​latch, such as one formed by a pair of cross-coupled NAND gates. Sensing by the sensing amplifier occurs during the sensing enable period.

[0030] Figure 1An example charge-transfer SRAM 100 is shown, which includes a burst-mode address comparator 101 that advantageously invokes burst mode even when there are intermediate read operations for different rows. Bit line pairs bl and blb cross the first column. Bit cell 105 is located at the intersection of the first column and the word line wl. Bit cell 105 is formed by a pair of cross-coupled inverters. The output node of the first inverter in the inverters is the true (Q) output of bit cell 105. This output node is coupled to bit line bl via NMOS access transistor M4. Similarly, the output nodes of the remaining second inverters in the inverters are the complementary (QB) outputs of bit cell 105, which are coupled to the complementary bit line blb via NMOS access transistor M3. The word line wl is coupled to the gate of the access transistor, such that the Q node and QB node drive their respective bit lines during the word line assertion period.

[0031] SRAM 100 includes a second column, which has bit cells at its intersection with the word line wl. Since the second column is a repetition of the structure in the first column, it is not shown in the diagram for clarity. Figure 1 Details of the second column are shown below. The two columns are multiplexed by column multiplexer 125. If a read operation (whether in random or burst mode) is pointed to bit cell 105, column multiplexer 125 selects the sense amplifier output from sense amplifier 110 for the first column. For example, column multiplexer 125 may include a tri-state buffer 130 for the first column and a tri-state buffer 135 for the second column. Tri-state buffers for unselected columns are tri-stateted to form the selection in column multiplexer 125. The output of column multiplexer 125 is latched in data output latch 140.

[0032] The bit cell 105 in the first column and the corresponding bit cell in the second column form a bit cell group that shares a common address that identifies the word line wl and a set of multiplexed columns. Within the bit cell group, only the column address changes. Regardless of whether the read operation occurs in burst mode, each read operation responds to a cycle of the memory clock signal 102. Assume that the first memory clock cycle corresponds to a read operation involving different word lines and / or columns, and assume that the first memory clock cycle is followed by a second memory clock cycle (in the second memory clock cycle, the read operation points to bit cell 105). For this second read operation, the burst mode address comparator 101 does not activate burst mode because the previously decoded address in the first memory clock cycle identifies different word lines and / or different sets of multiplexed columns.

[0033] During random read operations, bit lines bl and blb are precharged to the supply voltage by bit line precharge circuitry 150 before word line assertion. This precharge of the bit lines is routine and therefore not performed during... Figure 1 The diagram illustrates details of the bit line precharge circuit 150. The timing of various actions (such as bit line precharge, pulse width for word line assertion, and enable of sense amplifier 110 during read operations) is controlled by a self-timed clock circuit 155 (e.g., triggered by memory clock signal 102). During normal read operations, the timing of these actions is conventional. However, the self-timed clock circuit 155 is modified from this conventional function to accommodate burst mode. The self-timed clock circuit 155 therefore responds to burst mode signals such as the active low burst mode signal 145 (burst_n), such that during burst mode operation, word lines are not asserted, bit lines are not precharged, and charge transfer transistors are not turned on.

[0034] To control whether burst mode is activated, burst mode address comparator 101 asserts or de-asserts burst mode signal 145. As used herein, a signal is said to be "asserted" (or equivalently "set") when it has a logical true state (whether the logical true state is active high or active low). Conversely, a signal is considered to be "reset" herein when it has a logical false state (whether the logical true state is active high or active low). In an alternative embodiment, the burst mode signal may instead be an active high signal. If burst mode address comparator 101 does not assert burst mode signal 145, SRAM 100 performs a random read operation, wherein a second memory clock cycle triggers a self-timed clock circuit 155 to charge the voltage for word line w1l. Before this word line assertion, bit lines b1 and blb are pre-charged to the supply voltage by bit line pre-charge circuit 150. Following the bit line pre-charge, bit line pre-charge circuit 150 floats the bit lines. Bit line b1 is coupled to the corresponding sensing node sl of sense amplifier 110 via PMOS charge transfer transistor P1. Similarly, complementary bit line blb is coupled to the corresponding sensing node slb via PMOS charge transfer transistor P2. Before word line assertion, the gate voltage rm of the charge transfer transistor is charged to the supply voltage by self-timer clock circuit 155 to prevent any charge transfer to the sensing node. Since burst mode is not activated, the self-timer clock circuit 155 charges the sensing node precharge signal (cts_pre_n) to the supply voltage before word line assertion. The charged sensing node precharge signal drives the gates of NMOS transistor M1 and NMOS transistor M2. The sources of transistors M1 and M2 are connected to ground, while their drains are connected to complementary sensing node slb and sensing node sl, respectively. Therefore, the assertion of the sensing node precharge signal will discharge both sensing nodes sl and slb of the first column, as transistors M1 and M2 are turned on to couple their respective bit lines to ground. As previously stated, the second column has the same structure as that shown for the first column.

[0035] Therefore, for normal read operations where burst mode is not activated, both columns will discharge their sense nodes and precharge their bit lines before the word line assertion. However, if a continuous read operation points to the second column, the burst mode address comparator 101 activates burst mode by asserting the burst mode signal 145. The self-timer clock circuit 155 responds to the assertion of the burst mode signal 145 by preventing the word line wl from being asserted. Similarly, during burst mode, the self-timer clock circuit 155 maintains the gate voltage signal rm at the supply voltage to prevent charge transfer transistors P1 and P2 from turning on. Furthermore, during burst mode read operations, the self-timer clock circuit 155 maintains the sense amplifier precharge signal cts_pre_n at ground to prevent the sense nodes sl and slb from being precharged.

[0036] During a random read operation, access transistors M4 and M3 are turned on by asserting the word line voltage, causing one of the bit lines, b1 or blb, to slightly discharge from its pre-charged state depending on the binary content stored in bit cell 105. This slight bit line discharge is amplified by a charge transfer period during which charge transfer transistors P1 and P2 are turned on as follows: The charge transfer period is triggered by the discharge of the gate voltage rm. This discharge of the gate voltage rm begins while the word line voltage is still asserted. The discharge of the gate voltage rm may end after the word line voltage has been discharged. The discharge of the gate voltage rm has a certain slope. Due to this less-than-instantaneous discharge of the gate voltage rm, the gate voltage rm will discharge to the threshold voltage of the charge transfer transistor whose source is tied to the fully charged bit line, but will still be higher than the threshold voltage of the charge transfer transistor whose source is tied to the partially discharged bit line. Therefore, the charge transfer transistor for the fully charged bit line will conduct charge to its sensing node before the other charge transfer transistors conduct charge from the partially discharged bit line. For example, suppose bit line bl is a fully charged bit line, causing charge transfer transistor P1 to turn on before charge transfer transistor P2. Therefore, the sensing node voltage sl will increase before the complementary sensing node voltage slb increases.

[0037] Sensing node sl is connected to the input of NAND gate 115 in sensing amplifier 110. Similarly, sensing node slb is connected to the input of NAND gate 120 in sensing amplifier 110. NAND gates 115 and 120 are cross-coupled to form an RS latch. The sensing node is pre-charged to zero volts, such that the outputs of both NAND gate 115 and NAND gate 120 are asserted as high as the supply voltage. The output of NAND gate 120 also forms the output terminal for the first column. The corresponding NAND gate in the second column (not shown) forms the output terminal for the second column. The capacitance of the sensing node, conceptually represented by capacitor Cs, is relatively small compared to the bit line capacitance, which is conceptually represented by capacitor Cbl. Therefore, the brief amount of time that charge transfer transistor P1 begins to conduct before charge transfer transistor P2 conducts, compared to sensing node slb, causes a significant increase in the voltage of sensing node sl. This voltage increase exceeds the threshold voltage of NAND gate 115, causing its output to discharge to zero. The zero output of NAND gate 115 amplifies the binary high output of NAND gate 120, causing the binary 1 value stored in bit cell 105 to be latched in sense amplifier 110.

[0038] If the read operation is for the first column, the column multiplexer 125 selects the output terminal of the sense amplifier 110 in the first column so that the binary content of the bit cell 105 is latched into the data output latch 140 in the first memory cycle. However, note that the sense amplifier for the second column has also latched bits stored in the remaining bit cells in the bit cell group. If a subsequent read operation points to these remaining bit cells, the bit sense is not discarded. The burst mode address comparator 101 detects that the address of the second read operation points to the same bit cell group and therefore triggers a burst mode for the second memory clock cycle by asserting the burst mode signal 145. In response to the assertion of the burst mode signal 145, the self-timed clock circuit 155 prevents the word line W1 voltage from charging during the second memory clock cycle. Similarly, the self-timed clock circuit 155 prevents the sense node precharge signal from being asserted during the second memory clock cycle. Furthermore, the self-timed clock circuit 155 also prevents the gate voltage rm from discharging during the second memory clock cycle due to burst mode operation. Then, the column multiplexer 125 selects the second column through the tri-state buffer 135 so that bits from the bit cells of the second column can be stored in the data output latch 140.

[0039] To assist latching within the sense amplifier 110, a sense node precharge signal drives the gate of PMOS transistor P5, connecting its source to the power node for the supply voltage. The drain of transistor P5 is connected to the sources of a pair of PMOS transistors P4 and P3. The drain of transistor P4 is connected to sense node sl, while the drain of transistor P3 is connected to the complementary sense node slb. The output of NAND gate 115 drives the gate of transistor P4. Similarly, the output of NAND gate 120 drives the gate of transistor P3. For example, suppose the output of NAND gate 115 is low. This low output turns on transistor P4 to reinforce the fully charged state of sense node sl, which in turn reinforces the zero output of NAND gate 115. Conversely, suppose the output of NAND gate 120 is low following the sense enable period. Then, transistor P3 will be turned on. The turn-on of transistor P3 reinforces the fully charged state of the complementary sense node slb, which in turn reinforces the zero output of NAND gate 120. In this way, the latching of the sense bit in the sense amplifier 110 is enhanced or strengthened.

[0040] It should be understood that the burst mode operations disclosed herein are not limited to any specific column multiplexing size. For example, Figure 2 The diagram illustrates SRAM 200, in which four columns, ranging from column 1 (CTS_Cell0) to column 4 (CTS_Cell3), are multiplexed by column multiplexer 125. Each column has a bit cell at the intersection of the column and word line wl. The structure within each column is as discussed with respect to SRAM 100. For clarity, only column 1 (CTS_Cell0) is shown in detail. Since there are four columns in the multiplexed column group, and these four columns share data output latch 140, there are four decoded bits bst_0, bst_1, bst_2, and bst_3, and their complements, which control which column is selected by column multiplexer 125. Column multiplexer 125 is implemented using tri-state buffers, including tri-state buffer 130 as discussed with respect to memory 100; however, it should be understood that other types of column multiplexers can be used in SRAM 200. Gate voltage rm controls the charge transfer transistors in each column. Similarly, the sensing node precharge signal (cts_pre_n) controls the precharge of the sensing node through transistors M1 and M2 in each column, and controls the latch enhancement through transistors P3, P4 and P5 in each column, as discussed with regard to SRAM 100.

[0041] Because there are four columns, only two bits (e.g., the two least significant bits) will differ for each bit cell address in the bit cell group. During the initial non-burst mode read operation, the discharge of the gate voltage rm can be performed by an inverter (not shown) in the self-timed clock circuit 155. The inverter is relatively small, causing the discharge of the gate voltage rm to have some slew, resulting in an amplification of the bit line voltage difference relative to the charge transfer to the corresponding sensing node. Depending on which column is addressed, the corresponding bit from the addressed bit cell is selected by the column multiplexer 125 and latched into the data output latch 140. However, the sensing amplifier 110 in each of the four columns latches its corresponding bit decision. If subsequent read operations point to the same bit cell group, the burst mode address comparator 101 activates burst mode.

[0042] Figure 3 The embodiment 300 of the burst mode address comparator 101 is shown in more detail below. The row address is n bits wide, ranging from the zeroth address bit Addr[0] to the (n-1)th address bit Addr[n-1]. Each address bit used for the current memory cycle (both read and write) is compared with the corresponding bit used for the previous read cycle by the corresponding bit comparator 305. Thus there is a bit comparator 305 for address bit Addr[0], a bit comparator 305 for address bit Addr[1], a bit comparator 305 for address bit Addr[2], and so on, until a last bit comparator 305 is provided for the last address bit Addr[n-1]. Each bit comparator 305 forms a one-bit output signal, which has a binary state depending on the corresponding bit comparison. Since there are n bit comparators 305 for the n-bit wide read address, their one-bit output signals form an n-bit wide bit comparison word 321.

[0043] Each bit comparator 305 includes memory for storing its row address bits during a read operation. For example, the memory may be formed by a master latch 310 and a slave latch 315, which sequentially latch the corresponding bit from the read address. As used herein, the term "latch" refers to any suitable storage element, which may be synchronous (e.g., a register or flip-flop) or asynchronous (e.g., a reset-set latch). Each master latch 310 is timed by a memory operating clock (aclk), which is asserted by a clock controller (such as a self-timer clock circuit 155) in response to an assertion of the memory clock signal 102. The memory clock signal 102 is asserted to initiate a read or write operation. Each slave latch 315 is timed by a read clock, which is asserted by the clock controller only in response to an assertion of the memory clock signal used for a read operation. The delay between the master latch and the slave latch is one memory clock cycle, such that the address bit stored by the slave latch 315 is the address bit from the previous read operation to the current cycle of the memory clock signal 102. Each bit comparator 305 also includes an XOR gate 320, which XORs the corresponding current address bit and the corresponding previous address bit from its slave latch 315. If the current address bit and the corresponding previous address bit are the same, then one bit of the output signal from each XOR gate 320 will be grounded. Note that this comparison is performed regardless of whether the current memory clock cycle is for a read operation or a write operation. If the current memory cycle points to the row addressed in the previous read operation, then the N-bit wide comparison word 321 will therefore be all zeros. Thus, the comparison word is active low, which is asserted when the current row address is equal to the row address in the previous read operation. Conversely, if the current memory cycle does not point to the same row address as the row address addressed in the previous read operation, then at least one bit of the N-bit wide comparison word will be charged to the memory power supply voltage. XOR gate 320 is an example of a first plurality of logic gates configured to assert a bit comparison word in response to the current row address for memory being equal to the previous row address for a read operation.

[0044] Multiple OR gates 330 arranged in parallel process the N-bit wide output signal formed by XOR gates 320. The XOR gates 320 are arranged as XOR gate groups such that the output bits from each group of XOR gates 320 drive the corresponding OR gate in the OR gate 330. The input width of each OR gate 330 is three bits, but in alternative embodiments, this input width can be increased or decreased. The final OR gate 330 also performs an OR operation on a delayed version of the memory clock signal 102 delayed by an even number of inverters 340 to produce a delayed clock signal (cd). The delay between the delayed clock signal cd and the memory clock signal 102 controls the pulse width of the burst mode enable signal en_bst for burst mode, as will be explained further herein. The final OR gate 330 also processes the output signal from the reset-set burst mode blocking latch 345. Generally, the goal is to enable burst mode if the current read operation points to the same row as the row that appeared in the previous read operation, provided that there is no intermediate write operation after the previous read operation and before the current read operation.

[0045] The burst-mode blocking latch 345 is set only in the event of an intermediate write operation to the same row, as will be explained further herein. Therefore, in the absence of an intermediate write operation to the same row, the output signal from the burst-mode latch 345 is reset. If the current row address equals the row address of the previous read operation, the output signal from the OR gate 330 will be all low during the delay period from the assertion of the memory clock signal 102 to the assertion of the delayed clock signal cd. If the stored row address matches the current row address, then the output signal from the OR gate 330 will therefore be all low during the delay period.

[0046] The output of OR gate 330 is processed by NOR gate 335 to form a burst mode enable signal en_bst. If the current row address is equal to the row address used for the previous read cycle, the burst mode enable signal en_bst will therefore be high during the delay period. In an alternative embodiment, OR gate 330 can be replaced by a single OR gate that processes the output from XOR gate 320, the delayed clock signal cd, and the output signal from burst mode latch 345. In this embodiment, NOR gate 335 can be replaced by an inverter to generate the burst mode enable signal en_bst. The length of the delay period is determined by the delay through inverter 340. The burst mode enable signal en_bst drives the gate of NMOS transistor M5, which has a source connected to the drain of NMOS transistor M7. The drain of transistor M7 is connected to ground. A low active write enable signal we_n drives the gate of transistor M7. The active-low write enable signal we_n is grounded during the memory clock cycle for write operations and asserted to the supply voltage during the memory clock cycle for read operations. Therefore, during the delay period of a read operation where the current row address matches the row address of a previous read operation, the drain of transistor M5 will be grounded. However, during a write operation where the current row address matches the row address of a previous read operation, transistor M7 will be turned off even if the burst mode enable signal en_bst is asserted, to prevent transistor M5 from grounding its drain in response to the assertion of the burst mode enable signal en_bst. Transistor M7 can also be represented as the first transistor, and transistor M5 can be represented as the second transistor.

[0047] The drain of transistor M5 is connected to the source of NMOS transistor M6, which can also be represented as a third transistor. Since the memory clock signal 102 drives the gate of transistor M6, in the event of two consecutive read operations where the current row address matches the previous row address and there are no intermediate write operations for the same row address, the drain of transistor M6 will be grounded in response to the rising edge of the memory clock signal 102. Once the delay period established by inverter 340 expires, the burst mode enable signal en_bst will go low to turn off transistor M5. The drain voltage of transistor M6 forms the burst mode node for the burst mode signal 145. The burst mode signal 145 will therefore be discharged to ground to indicate that burst mode is activated if the current row address for the read operation matches the row address of the previous read operation and there are no intermediate write operations for the same row address. The burst mode signal 145 is latched by a pulse latch 325 formed by the inverter pair. In one embodiment, OR gate 330 and NOR gate 335 are examples of a second plurality of logic gates configured to turn on a first transistor (M5) in response to an assertion of a bit comparison word to ground the burst mode node.

[0048] For each consecutive read operation, the burst mode signal 145 is re-evaluated. Therefore, before the next cycle of the memory clock signal 102, the burst mode signal 145 should be reset by being charged to the memory power supply voltage. For example, the burst mode signal 145 can be reset by a PMOS transistor P6, which has a drain connected to the drain of transistor M6. Transistor P6 can also be represented as a fourth transistor. The source of transistor P6 is connected to the power node for the memory power supply voltage. If transistor P6 is turned on, the drain of transistor M6, and therefore the burst mode signal 145, will be charged to the memory power supply. A self-timed active-low ready signal (ready_n), such as that generated by a self-timed clock circuit 155, drives the gate of transistor P6 to control whether the burst mode signal 145 is reset. The self-timed clock circuit 155 can use the falling edge of the ready_n signal to trigger the release of the word line during a normal read operation. Although the self-timed clock circuit 155 does not interrupt the word line during burst mode operation, the falling edge of the ready_n signal facilitates the control of the reset of the burst mode signal 145. In an alternative embodiment, other suitable signals, such as the falling edge of the memory clock signal 102, can be used to drive the gate of transistor P6 to control the reset of the burst mode signal 145.

[0049] When both the burst mode enable signal en_bst and the write enable signal (WE) are asserted, a first logic gate such as AND gate 355 sets the burst mode latch 345. The write enable signal is asserted in each write operation. However, the burst mode enable signal en_bst is asserted only if the row address used for an intermediate write operation is the same as the row address in a previous random read operation. In this case, AND gate 355 asserts its output signal to set the burst mode latch 345. Subsequent read operations are then forced as random read operations, even when bit comparison word 321 is asserted due to row address matching, because the output signal from end OR gate 330 is driven high by the set of burst mode latch 345. When the complement of the read signal (rd) and the active-low ready signal ready_n (ready) is asserted, a second logic gate such as AND gate 350 resets the burst mode latch 345. The read signal rd is asserted for each read operation. Similarly, the ready signal will be asserted after the word line assertion in the read operation. Therefore, AND gate 350 will be used to reset burst mode latch 345 in each read operation, regardless of whether the read operation is a random read operation or a burst mode read operation.

[0050] exist Figure 4The diagram illustrates a series of burst-mode read and write operations. Read and write operations respond to cycles of the memory clock signal (CLK). In the initial memory clock cycle, a random read (R) operation occurs for the first row. In the second memory clock cycle, the same first row is addressed in another read operation for the first row, invoking burst mode. Then, in the third memory clock cycle, a first write operation occurs for the second row. Since this is not an intermediate write operation for the first row, the read operation for the first row in the fourth memory clock cycle is again a burst-mode read operation. Then, in the fifth memory clock cycle, a second write operation occurs for the third row. Since this is again not an intermediate write operation for the first row, the read operation for the first row in the sixth memory clock cycle is again a burst-mode read operation.

[0051] Now about Figure 5 The flowchart discusses a method for burst-mode address comparison. The method includes action 500: during a first read operation targeting a first row in memory, pre-charging a pair of sense nodes used for a sense amplifier. Pre-charging sense nodes sl and slb in memory 100 or 200 is an example of action 500. The method also includes action 505: after the pre-charging in the first read operation, latching a first bit signal in the sense amplifier. Latching of RS flip-flop 110 is an example of action 505. Furthermore, the method includes action 510, which occurs during a write operation following the first read operation and includes writing to a second row of memory. Regarding... Figure 4 Any of the write operations discussed is an example of action 510. Finally, the method includes action 515, which occurs in a second read operation for the first row following the write operation, and includes passing the first bit signal latched in the sense amplifier to the data output latch without pre-charging the sense node pair during the second read operation. Passing the bit latched in RS flip-flop 110 to data output latch 140 during a burst-mode read operation is an example of action 515.

[0052] As disclosed herein, a burst-mode address comparison memory can be incorporated into a wide variety of electronic systems. For example, such as... Figure 6 As shown, according to this disclosure, a cellular phone 600, a laptop computer 605, and a tablet PC 610 can all include a memory with a burst-mode address comparator. Other exemplary electronic systems such as music players, video players, communication devices, and personal computers can also be configured with a burst-mode address comparator constructed according to this disclosure.

[0053] As those skilled in the art will now understand, and depending on the specific application at hand, many modifications, substitutions, and variations can be made to the materials, apparatus, configurations, and methods of using the devices of this disclosure without departing from the scope of this disclosure. Therefore, the scope of this disclosure should not be limited to the specific embodiments illustrated and described herein (as they are merely examples of this disclosure), but should be fully proportionate to the scope of the appended claims and their functional equivalents.

Claims

1. A memory including a burst mode address comparator, comprising: an address memory configured to store a first row address for a first read operation; a latch configured to set a latch output signal in response to a second row address for a write operation being equal to the first row address, the write operation following the first read operation; a first plurality of logic gates configured to assert a bit compare word in response to a current row address for the memory being equal to the first row address; a first transistor configured to be off during each write operation and on during each read operation; a second transistor having a first terminal coupled to a burst mode node for a burst mode signal and having a second terminal coupled to ground through the first transistor; and a second plurality of logic gates configured to turn on the second transistor to ground the burst mode node in response to assertion of the bit compare word when the latch output signal is asserted and not to turn on the second transistor in response to assertion of the bit compare word when the latch output signal is reset.

2. The memory of claim 1, further comprising: a third transistor coupled between the first terminal of the second transistor and the burst mode node, wherein the third transistor is configured to turn on in response to a memory clock signal for the memory.

3. The memory of claim 1, wherein the address memory includes a plurality of master-slave latches, and wherein each slave latch is responsive to a read clock signal.

4. The memory of claim 1, wherein the first plurality of logic gates includes a plurality of exclusive OR gates.

5. The memory of claim 4, wherein the second plurality of logic gates includes: a plurality of OR gates configured to process the bit compare word; and a NOR gate configured to process a plurality of output signals from the plurality of OR gates, wherein the NOR gate is further configured to drive a gate of the second transistor.

6. The memory of claim 5, wherein a last OR gate of the plurality of OR gates is further configured to process a delayed version of a memory clock signal for the memory and the latch output signal.

7. The memory of claim 2, further comprising: a self-timed clock circuit configured to assert a self-timed clock signal in response to the memory clock signal; and a fourth transistor coupled between a power node for a memory power supply voltage and the burst mode node, wherein the fourth transistor is configured to turn on in response to a falling edge of the self-timed clock signal.

8. The memory of claim 7, wherein the first transistor is an n-type metal oxide semiconductor (NMOS) transistor, the second transistor is an NMOS transistor, the third transistor is an NMOS transistor, and the fourth transistor is a p-type metal oxide (PMOS) transistor.

9. The memory of claim 1, further comprising: ​ ​ ​ a first column including a first sense amplifier configured to sense a first bit from a first bitcell through a first pair of sense nodes to output the first bit at a first output terminal for the first column, a second column including a second sense amplifier configured to sense a second bit from a second bitcell through a second pair of sense nodes and to output the second bit at a second output terminal for the second column; a data output latch; a column multiplexer configured to select between the first bit from the first output terminal and the second bit from the second output terminal to provide the selected bit to the data output latch; a sense node precharge circuit configured to precharge the first pair of sense nodes and the second pair of sense nodes in response to an assertion of a sense node precharge signal; and a self-timed clock circuit configured to assert the sense node precharge signal in a read cycle in which the burst mode signal is not asserted.

10. The memory of claim 9, wherein the first sense amplifier includes a first reset-set latch, and wherein the second sense amplifier includes a second reset-set latch.

11. The memory of claim 9, wherein the first column includes a bit line coupled to a first sense node of the first pair of sense nodes through a first charge transfer transistor and further includes a complementary bit line coupled to a second sense node of the first pair of sense nodes through a second charge transfer transistor, wherein the self-timed clock circuit is further configured to maintain the first charge transfer transistor and the second charge transfer transistor off in a read cycle in which the burst mode signal is asserted.

12. The memory of claim 11, wherein the first charge transfer transistor and the second charge transfer transistor each include a PMOS transistor.

13. The memory of claim 5, further comprising: a first logic gate configured to set the latch output signal in response to an assertion of an output signal from the NAND gate when a write enable signal is asserted; and a second logic gate configured to reset the output signal in response to an assertion of a read enable signal.

14. The memory of claim 13, wherein the first logic gate and the second logic gate each include an AND gate.

15. The memory of claim 1, wherein the memory is incorporated in a cellular telephone.

16. A burst mode method for a memory, comprising: precharging a pair of sense nodes for a sense amplifier during a first read operation for a first row in the memory; latching a first bit signal in the sense amplifier after the precharging; writing to a second row in the memory in a write operation after the first read operation; and ​ In a second read operation on the first row following the write operation, the first bit signal latched in the sense amplifier is passed to a data output latch without pre-charging the sense node pair during the second read operation.

17. The burst mode method of claim 16, further comprising: asserting a word line during the first read operation; and initiating a charge transfer period when the word line is asserted, a first charge transfer from a first pre-charge bit line to a first sense node of the sense node pair in the charge transfer period being dependent on a binary value of a first bit, wherein the latching of the first bit signal is responsive to the first charge transfer, and wherein the word line is not asserted during the second read operation.

18. The burst mode method of claim 17, further comprising: discharging the sense node pair prior to the charge transfer period.

19. The burst mode method of claim 16, wherein the sense node pair is not pre-charged during the second read operation in response to an assertion of a burst mode signal.

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