Thin film transistor, display panel, and display device

Abstract

A thin film transistor includes: a substrate; a semiconductor layer, a gate, and a source and a drain provided on the substrate; the semiconductor layer includes a first material layer and a second material layer which are stacked; a material of the first material layer is selected from one or more combinations of a first n-type metal oxide semiconductor material; a material of the second material layer is selected from one or more combinations of a second n-type metal oxide semiconductor material; a carrier mobility of the first n-type metal oxide semiconductor material is greater than or equal to 40 cm 2 Vs, the second n-type metal oxide semiconductor material is selected from being doped with Y selected from one or more combinations of rare earth elements; wherein the first material layer is closer to the gate relative to the second material layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a thin film transistor, a display panel and a display device. BACKGROUND

[0002] A thin film transistor (TFT) is a kind of semiconductor device commonly used in flat panel display. As a device for pixel control and driving in flat panel display, it affects the development of flat panel display. SUMMARY

[0003] In one aspect, a thin film transistor is provided, comprising: a substrate; a semiconductor layer, a gate electrode, and a source electrode and a drain electrode disposed on the substrate; the semiconductor layer comprises a first material layer and a second material layer stacked together; the material of the first material layer is selected from one or more combinations of a first n-type metal oxide semiconductor material, and the material of the second material layer is selected from one or more combinations of a second n-type metal oxide semiconductor material; the carrier mobility of the first n-type metal oxide semiconductor material is greater than or equal to 40 cm 2 / Vs, the second n-type metal oxide semiconductor material is doped with Y selected from one or more combinations of rare earth elements; wherein the first material layer is closer to the gate electrode than the second material layer.

[0004] In some embodiments, the doping proportion of the rare earth elements in the second n-type oxide semiconductor material is 0.01at%-0.30at%.

[0005] In some embodiments, the first n-type metal oxide semiconductor material is further doped with Z selected from one or more combinations of rare earth elements, and the type of the rare earth elements doped in the first n-type metal oxide semiconductor material is the same as or different from the type of the rare earth elements doped in the second n-type metal oxide semiconductor material.

[0006] In some embodiments, the first semiconductor layer contains the same types of elements as the second semiconductor layer, but the atomic number proportion of each element is different.

[0007] In some embodiments, the first n-type metal oxide semiconductor material is selected from a metal oxide doped with X or not doped with X; the metal oxide comprises one or more elements selected from indium, zinc, tin, gallium, and oxygen, and X is selected from one or more combinations of aluminum, tungsten, hafnium, zirconium, nitrogen and hydrogen.

[0008] In some embodiments, the thickness of the second material layer is greater than 10 nm.

[0009] In some embodiments, when the thickness of the second material layer is greater than 10 nm and less than or equal to 15 nm, the ratio of the thickness of the first material layer to the thickness of the second material layer is less than or equal to 1.

[0010] In some embodiments, as the ratio of the thickness of the first material layer to the thickness of the second material layer gradually increases, the carrier mobility of the thin film transistor increases.

[0011] In some embodiments, when the thickness of the second material layer is greater than 15 nm, the thickness of the first material layer is greater than or equal to 20 nm, and the ratio of the thickness of the first material layer to the thickness of the second material layer is less than or equal to 2.

[0012] In some embodiments, the thickness of the first material layer is greater than or equal to 10 nm.

[0013] In some embodiments, the thickness of the semiconductor layer is 30 nm to 70 nm.

[0014] In another aspect, a display panel is provided, comprising the thin film transistor as described above.

[0015] In yet another aspect, a display device is provided, comprising the display panel as described above. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only the drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0017] FIG. 1A A sectional view of a bottom-gate type thin film transistor according to some embodiments;

[0018] FIG. 1B A sectional view of a top-gate type thin film transistor according to some embodiments;

[0019] FIG. 2A A schematic diagram of the conversion of a depletion layer to an inversion layer of a thin film transistor according to some embodiments;

[0020] FIG. 2B A schematic diagram of the transition of a linear region to a saturation region of a thin film transistor according to some embodiments;

[0021] FIG. 2CFIG. 2 is a graph of output characteristics of a thin film transistor according to some embodiments at different gate voltages;

[0022] FIG. 2D FIG. 4 is a band structure diagram of NBIS based on the theory of photo-generated hole-electron pairs according to some embodiments;

[0023] FIG. 3A FIG. 5 is a cross-sectional view of another bottom gate type thin film transistor according to some embodiments;

[0024] FIG. 3B FIG. 6 is a cross-sectional view of another top gate type thin film transistor according to some embodiments;

[0025] FIG. 4A FIG. 7 is a comparison graph of transfer characteristics of thin film transistors in Comparative Example 1 and Comparative Example 2 and Experimental Example 3;

[0026] FIG. 4B FIG. 8 is a stability test graph of a thin film transistor in Comparative Example 1 under NBIS conditions;

[0027] FIG. 4C FIG. 9 is a stability test graph of a thin film transistor in Comparative Example 2 under NBIS conditions;

[0028] FIG. 4D FIG. 10 is a comparison graph of transfer characteristics of thin film transistors in Experimental Examples 1 to 4;

[0029] FIG. 4E FIG. 11 is a stability test graph of a thin film transistor in Experimental Example 1 under NBIS conditions;

[0030] FIG. 4F FIG. 12 is a stability test graph of a thin film transistor in Experimental Example 2 under NBIS conditions;

[0031] FIG. 4G FIG. 13 is a stability test graph of a thin film transistor in Experimental Example 3 under NBIS conditions;

[0032] FIG. 4H FIG. 14 is a stability test graph of a thin film transistor in Experimental Example 4 under NBIS conditions;

[0033] FIG. 4I FIG. 15 is a comparison graph of transfer characteristics of thin film transistors in Experimental Examples 4 to 6;

[0034] FIG. 4J FIG. 16 is a stability test graph of a thin film transistor in Experimental Example 5 under NBIS conditions;

[0035] FIG. 4K FIG. 17 is a stability test graph of a thin film transistor in Experimental Example 6 under NBIS conditions. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0037] Unless otherwise required by context, the term "comprise" and its other forms such as "comprises" and "comprising" are to be construed as open, inclusive, meaning that "comprising" means "including but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to mean that the specific feature, structure, material or characteristic associated with that embodiment or example is included in at least one embodiment or example of the present disclosure. The illustrative representation of the above terms does not necessarily mean the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0038] Hereinafter, the terms "first", "second" are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0039] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0040] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0041] The use of "adapted for" or "configured for" herein means open and inclusive language that does not exclude devices adapted for or configured for performing additional tasks or steps.

[0042] In addition, the use of "based on" means open and inclusive, as a process, step, calculation, or other action "based on" one or more recited conditions or values can in practice be based on additional conditions or values beyond those recited.

[0043] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the scale of the layers and regions can be shown in the drawings, which can distort the representation of the actual scale. Thus, embodiments can contemplate variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, and are therefore not limited to the specific shapes that are shown. It is therefore intended that an embodiment can include variations in the shapes and the like of parts illustrated in the drawings as a consequence of, for example, manufacturing. For example, an etched region illustrated as a rectangle will typically have curved distal and other features. The regions illustrated in the various figures are intended to show the generic positions of the various layers and / or regions in illustrative embodiments, and are not necessarily drawn to scale. Similarly, it is intended that an embodiment can include structures that are otherwise inconsistent with the shapes of the regions shown in the drawings, for example, where an shape is schematically represented by a rectangle but other shapes are contemplated.

[0044] Some embodiments of the present disclosure provide a display device including a display panel, and of course can also include other components, for example, can include a circuit for providing an electrical signal to the display panel to drive the display panel to display, which can be referred to as a control circuit, can include a circuit board and / or an IC (Integrate Circuit) electrically connected with the display panel.

[0045] The display panel example can be one of an LCD (Liquid Crystal Display), an OLED (Organic Light-Emitting Diode), and a QLED (Quantum Dot Light Emitting Diodes), a Micro LED (Micro Light Emitting Diodes), a mini LED (mini Light Emitting Diodes), and the like.

[0046] The display device can be specifically a mobile phone, a tablet computer, a notebook computer, a personal digital assistant (PDA), a vehicle-mounted computer, a laptop computer, a digital camera, and the like.

[0047] The display panel includes a substrate and a driving circuit, such as a pixel driving circuit, a gate driving circuit, etc., disposed on the substrate. The driving circuit can include a thin film transistor (TFT). The thin film transistor is an important component of the pixel driving circuit, the gate driving circuit, etc. During power-on, the thin film transistor is controlled to be turned on or off, so as to control the pixel driving circuit and the gate driving circuit to drive the display panel to display.

[0048] As shown in FIG. 1A and FIG. 1B , the thin film transistor 1 includes a substrate 11, a semiconductor layer 12, a gate 13, a gate insulating layer 14, a source 15 and a drain 16 disposed on the substrate 11. The substrate 11 can be part of the substrate described above. According to the display panel described above, the substrate 11 can be a flexible display panel or a rigid display panel. The substrate 11 can be a flexible substrate or a rigid substrate. The flexible substrate can be a plastic substrate, or a flexible substrate with a certain thickness made of glass or metal material. The rigid substrate can be a glass substrate or a semiconductor substrate (such as a silicon substrate, a corundum substrate), etc.

[0049] According to the relative positions of the gate 13 and the semiconductor layer 12 in the thin film transistor 1, the thin film transistor 1 can include a bottom-gate thin film transistor and a top-gate thin film transistor. As shown in FIG. 1A , for the bottom-gate thin film transistor, the gate 13 is disposed below the semiconductor layer 12, that is, the gate 13 is closer to the substrate 11 than the semiconductor layer 12. As shown in FIG. 1B , for the top-gate thin film transistor, the gate 13 is disposed above the semiconductor layer 12, that is, the semiconductor layer 12 is closer to the substrate 11 than the gate 13.

[0050] In some embodiments, as shown in FIG. 1A and FIG. 1B , the semiconductor layer 12 includes a channel region 121, a source region 122 and a drain region 123, the source region 122 and the drain region 123 are located on opposite sides of the channel region 121, and the source 15 and the drain 16 are disposed in the same layer. The source 15 and the drain 16 are disposed on the side of the semiconductor layer 12 close to the substrate 11, and the source 15 and the drain 16 are respectively in contact with the source region 122 and the drain region 123 of the semiconductor layer 12. Alternatively, as shown in FIG. 1A and FIG. 1B , the source 15 and the drain 16 are disposed on the side of the semiconductor layer 12 away from the substrate 11, and the source 15 and the drain 16 are respectively in contact with the source region 122 and the drain region 123 of the semiconductor layer 12.

[0051] Taking an n-type thin film transistor as an example, the working principle of the thin film transistor 1 is as follows:

[0052] As FIG. 2A shown, when a positive voltage is applied to the gate 13, an electric field is generated in the gate insulating layer 14, and an electric line of force is directed from the gate 13 toward the semiconductor surface, and an induced charge is generated at the surface. As the gate voltage increases, the semiconductor surface will change from a depletion layer to an electron accumulation layer, forming an inversion layer. When a strong inversion is reached (the required gate voltage is called the threshold voltage V th of the thin film transistor 1), the inversion layer forms a conductive channel between the source 15 and the drain 16, i.e., a so-called front channel, and when a voltage is applied between the source 15 and the drain 16, carriers pass through the channel. As FIG. 2B and FIG. 2C shown, when the source-drain voltage V ds is small, the conductive channel is approximately a constant resistance, and the drain current increases linearly with the source-drain voltage, corresponding to the linear region of the thin film transistor 1. When the source-drain voltage V ds is large, it has an effect on the gate voltage, causing the electric field in the gate insulating layer 14 to gradually weaken from the source to the drain, and the electron density in the inversion layer at the semiconductor surface to gradually decrease from the source to the drain, and the channel resistance increases with the source-drain voltage V ds . The drain current increases slowly, corresponding to the transition from the linear region to the saturation region. When the source-drain voltage V ds increases to a certain extent, the thickness of the inversion layer at the drain end decreases to zero, and as the source-drain voltage V ds continues to increase, the device enters the saturation region, and under the action of the source-drain positive voltage, electrons from the source 15 flow through the channel to form an electron current, which is the open state of the thin film transistor 1.

[0053] Thus, the working region of the turned-on thin film transistor 1 is divided into a non-saturation region and a saturation region. When V gs >V th , V ds <V gs -V th , the thin film transistor 1 works in the non-saturation region, and the corresponding non-saturation region current is shown in equation (1). When V ds >V gs -V th , V gs >V th , the thin film transistor works in the saturation region, and the corresponding saturation region current is shown in equation (2). Where μ is the electron mobility, C ox is the unit area capacitance of the MIS structure of the thin film transistor, and W / L represents the ratio of the width of the channel to the length of the channel of the thin film transistor. Of course, when no inversion channel is formed, the thin film transistor is in the cutoff region.

[0054]

[0055]

[0056] In a display panel (such as a liquid crystal display panel), the thin-film transistor 1 operates in the non-saturation region for most of the time. As shown in equation (1), to increase the on-state current I of the thin-film transistor... on (that is, I in equations (1) and (2) above) ds It can increase μ, Cox, W / L, and V. gs and V ds The value of V, or a decrease in V th The value of V gs and V ds Other parameters can be controlled through process design or structural design.

[0057] Furthermore, thin-film transistor 1 operates in the off state, i.e., under negative gate bias, for most of the time. Studies have shown that prolonged operation under negative gate bias leads to a negative threshold voltage drift and a significant increase in leakage current, thus degrading the device characteristics of thin-film transistor 1. This is especially true under illumination, such as... FIG. 2D As shown, photogenerated carriers, namely electron-hole pairs, are generated in the metal oxide semiconductor layer (i.e., semiconductor layer 12). Electrons move towards the drain 16 and holes move towards the source 15, thereby forming hole leakage current, which further aggravates the negative threshold voltage drift of the thin film transistor.

[0058] Therefore, in order to improve the performance of thin-film transistor 1, it is necessary not only to increase the on-state current of the thin-film transistor, but also to improve the light stability of the thin-film transistor.

[0059] Based on this, in some embodiments, such as FIG. 1A and FIG. 1B As shown, the semiconductor layer 12 includes a first material layer 12a and a second material layer 12b stacked together. The material of the first material layer 12a is selected from one or more combinations of first n-type metal-oxide-semiconductor materials, and the material of the second material layer 12b is selected from one or more combinations of second n-type metal-oxide-semiconductor materials. The carrier mobility of the first n-type metal-oxide-semiconductor material is greater than or equal to 40 cm⁻¹. 2 / Vs, the second n-type metal-oxide-semiconductor material is doped with Y, where Y is selected from one or more combinations of rare earth elements. The first material layer 12a is closer to the gate 13 than the second material layer 12b. For example... FIG. 1A As shown, the first material layer 12a is located below the second material layer 12b, as... FIG. 1B As shown, the first material layer 12a is located above the second material layer 12b.

[0060] The carrier mobility of the first material layer 12a can be determined by performing an I-test on the transfer characteristic curve.ds 1 / 2 ~V gs The curve is fitted to the straight line segments, and the electron mobility μ can be extracted from the extrapolated curve slope. The formula for calculating μ can be shown as formula (4) below.

[0061]

[0062]

[0063]

[0064] In some embodiments, the first n-type metal oxide semiconductor material is selected from a metal oxide doped with X or not doped with X; wherein the metal oxide comprises one or more of elements of indium, zinc, tin, gallium, and oxygen, and X is selected from one or more combinations of aluminum, tungsten, hafnium, tantalum, zirconium, nitrogen, and hydrogen.

[0065] The metal oxide comprising one or more of elements of indium, zinc, tin, gallium, and oxygen means that the metal oxide can be a monovalent metal oxide such as indium oxide, zinc oxide, tin oxide, gallium oxide, etc., a binary metal oxide such as indium zinc oxide (IZO), indium tin oxide (InSnO), etc., or a ternary metal oxide such as indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium gallium tin oxide (InGaSnO), etc. Of course, it can also be a combination of two or more of the above monovalent metal oxide, binary metal oxide, and ternary metal oxide. The metal oxide doped with X can be obtained by a target sputtering process. When X is a metal such as aluminum, the target can be an alloy containing X or a compound of X (such as aluminum oxide). When X is nitrogen, the sputtering process can be carried out in a nitrogen atmosphere.

[0066] In these embodiments, the carrier mobility of the material of the first material layer 12a can reach 40 cm 2 Vs or above, so as to ensure that the thin film transistor 1 has a high carrier mobility when in operation.

[0067] Rare earth elements are the collective name of 17 special elements. They are named because Swedish scientists used rare earth compounds when extracting rare earth elements.

[0068] The rare earth elements include lanthanide series elements, and elements yttrium (Y) and scandium (Sc) closely related to the lanthanide series elements. Among them, the lanthanide series elements refer to 15 elements of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) and lutetium (Lu).

[0069] The second n-type metal oxide semiconductor material doped with Y means that the second n-type metal oxide semiconductor material can be any metal oxide semiconductor material doped with Y, such as the second metal oxide semiconductor material can be any of the above-mentioned metal oxides (such as one or more combinations of indium zinc oxide, indium tin oxide, indium gallium zinc oxide, indium zinc tin oxide and indium gallium tin oxide) doped with one or more combinations of the above-mentioned 17 kinds of rare earth elements, and these metal oxides can also be doped or not doped with X.

[0070] The first material layer 12a can be sputtered by the above-mentioned selected material, and the second material layer 12b can be co-sputtered by the pure substance or compound corresponding to the doped rare earth element (such as praseodymium (Pr) in the case of praseodymium (Pr), the pure substance corresponding to the rare earth element is praseodymium (Pr), and the compound corresponding to the rare earth element is praseodymium (Pr)) and the metal oxide selected from the second n-type metal oxide semiconductor material in a certain gas atmosphere (such as an oxygen-containing atmosphere) to realize the doping of the rare earth element.

[0071] In the thin film transistor 1 provided by the present disclosure, by selecting the material of the first material layer 12a, using a metal oxide semiconductor material with a carrier mobility greater than 40 cm 2The material of Vs, as the carrier transport layer, can increase the conductive capacity of the semiconductor layer 12, thereby improving the carrier mobility of the thin film transistor 1. Meanwhile, by doping the first n-type metal oxide semiconductor material in the second material layer 12a with rare earth, on one hand, the photo-generated carrier relaxation path can be changed, and the activation energy required for the photo-generated electron-hole pair recombination process can be reduced. The recombination process is easier when the activation energy is reduced, and thus the holes and electrons are more likely to recombine, thereby improving the NBIS (Negative Gate-Bias Illumination Stress) stability of the thin film transistor 1. Compared with the related art in which only a material with a relatively high carrier mobility is used as the semiconductor layer 12, the NBIS stability of the thin film transistor can be improved while the carrier mobility is taken into account. Compared with the related art in which only a material doped with rare earth elements is used as the semiconductor layer 12, the carrier mobility of the entire semiconductor layer 12 can be prevented from being reduced due to the doping of rare earth elements, and the carrier mobility and the illumination stability of the semiconductor layer can be taken into account at the same time.

[0072] In some embodiments, the doping proportion of Y in the second n-type oxide semiconductor material is 0.01 at% to 0.30 at%. at% represents the atomic percentage, and the doping proportion of Y in the second n-type oxide semiconductor material refers to the percentage of the number of atoms of the rare earth element represented by Y in the total number of atoms in the second n-type oxide semiconductor material.

[0073] Here, it should be noted that when Y is selected from one rare earth element, the doping proportion of Y in the second n-type oxide semiconductor material refers to the percentage of the number of atoms of the rare earth element in the total number of atoms in the second n-type oxide semiconductor material, and when Y is selected from a combination of multiple rare earth elements, the doping proportion of Y in the second n-type oxide semiconductor material refers to the percentage of the number of atoms of the rare earth elements selected by Y in the total number of atoms in the second n-type oxide semiconductor material.

[0074] For example, when Y is selected from rare earth elements (such as neodymium (Nd)), and the second n-type oxide semiconductor material is indium tin zinc oxide (ITZO) doped with Y, the doping ratio of Y in the second n-type oxide semiconductor material refers to the percentage of the number of atoms of neodymium (Nd) in the total number of atoms in the second n-type oxide semiconductor material. For example, in the second n-type oxide semiconductor material, the percentage of the number of atoms of In in the total number of atoms in the second n-type oxide semiconductor material can be 1%, the percentage of the number of atoms of Sn in the total number of atoms in the second n-type oxide semiconductor material can be 2%, the percentage of the number of atoms of Zn in the total number of atoms in the second n-type oxide semiconductor material can be 2%, and the percentage of the number of atoms of Nd in the total number of atoms in the second n-type oxide semiconductor material can be 0.17%. In this case, the ratio of the number of atoms of In, Sn, Zn, and Nd can be 1:2:2:0.17.

[0075] For example, when Y is selected from rare earth elements (such as neodymium (Nd) and praseodymium (Pr)), and the second n-type oxide semiconductor material is indium tin zinc oxide (ITZO) doped with Y, the doping ratio of Y in the second n-type oxide semiconductor material refers to the percentage of the sum of the number of atoms of neodymium (Nd) and praseodymium (Pr) in the total number of atoms in the second n-type oxide semiconductor material. For example, in the second n-type oxide semiconductor material, the percentage of the number of atoms of In in the total number of atoms in the second n-type oxide semiconductor material can be 1%, the percentage of the number of atoms of Sn in the total number of atoms in the second n-type oxide semiconductor material can be 2%, the percentage of the number of atoms of Zn in the total number of atoms in the second n-type oxide semiconductor material can be 2%, the percentage of the number of atoms of Nd in the total number of atoms in the second n-type oxide semiconductor material can be 0.17%, and the percentage of the number of atoms of Pr in the total number of atoms in the second n-type oxide semiconductor material can be 0.13%. In this case, the percentage of the sum of the number of atoms of neodymium (Nd) and praseodymium (Pr) in the total number of atoms in the second n-type oxide semiconductor material is 0.3%.

[0076] In some embodiments, the first n-type metal oxide semiconductor material is further doped with Z, which is selected from one or more combinations of rare earth elements. The type of rare earth element doped in the first n-type metal oxide semiconductor material can be the same as or different from the type of rare earth element doped in the second n-type metal oxide semiconductor material.

[0077] That is, the first n-type metal oxide semiconductor material can also be doped with one or more combinations of the above-mentioned 17 types of rare earth elements (i.e., Z). In this case, the type of rare earth element contained in Z can be the same as or different from the type of rare earth element contained in Y.

[0078] For example, when Y is selected from neodymium (Nd), Z can be neodymium (Nd) or a combination of one or more elements other than neodymium (Nd) from the above-mentioned 17 types of rare earth elements.

[0079] In these embodiments, the presence of rare earth elements in the first n-type metal oxide semiconductor material can change the relaxation path of photo-generated carriers in the first semiconductor layer 12a, thereby further reducing the activation energy required for the recombination of photo-generated electrons in the first semiconductor layer 12a, and further improving the light stability of the thin film transistor.

[0080] In addition, the first material layer 12a can also be formed by co-sputtering the single element or compound corresponding to the doped rare earth element (e.g., in the case of praseodymium (Pr), the single element corresponding to the rare earth element is praseodymium (Pr) and the compound corresponding to the rare earth element is a compound of praseodymium (Pr)) and the metal oxide selected from the first n-type metal oxide semiconductor material in a certain gas atmosphere (e.g., an oxygen-containing atmosphere) to achieve the doping of the rare earth elements contained in Z.

[0081] In the above-mentioned first material layer 12a, the type of element contained in the first material layer 12a can be the same as or different from the type of element contained in the second semiconductor layer, which is not specifically limited here.

[0082] In some embodiments, the type of element contained in the first semiconductor layer 12a is the same as the type of element contained in the second semiconductor layer 12b, and the atomic number ratio of each element is different.

[0083] For example, when the first semiconductor layer 12a and the second semiconductor layer 12b are both selected from indium zinc tin oxide doped with neodymium (Nd), the atomic number ratio of indium and tin in the first semiconductor layer 12a (i.e., the percentage of the atomic number of indium and tin in the total atomic number of the first semiconductor layer 12a) can be greater than the atomic number ratio of indium and tin in the second semiconductor layer 12b (i.e., the percentage of the atomic number of indium and tin in the total atomic number of the first semiconductor layer 12a). The doping ratio of neodymium (Nd) in the second semiconductor layer 12b (i.e., the percentage of the atomic number of neodymium (Nd) in the total atomic number of the first semiconductor layer 12a) can be greater than the doping ratio of neodymium (Nd) in the first semiconductor layer 12a (i.e., the percentage of the atomic number of neodymium (Nd) in the total atomic number of the first semiconductor layer 12a).

[0084] In these embodiments, the target materials used by the first semiconductor layer 12a and the second semiconductor layer 12b can be the same, except that different sputtering rates are controlled during the sputtering process to achieve different atomic number ratios of material composition.

[0085] Here, the thickness d1 of the first material layer 12a and the thickness d2 of the second material layer 12b are not specifically limited, as long as the material of the first material layer 12a is selected from the first n-type metal oxide semiconductor material and the material of the second material layer 12b is selected from the second n-type metal oxide semiconductor material.

[0086] In some embodiments, as shown in FIGS. 1A and 1B, the thickness d2 of the second material layer 12b is greater than 10 nm. FIG. 3A and FIG. 3B As shown in FIGS. 1A and 1B, the thickness d2 of the second material layer 12b is greater than 10 nm.

[0087] In these embodiments, for example, when the thickness d of the semiconductor layer 12 is 30 nm, the thickness d2 of the second material layer 12b can be 15 nm, 20 nm, 25 nm, etc. At this time, correspondingly, the thickness d1 of the first material layer 12a is the thickness d of the semiconductor layer 12 minus the thickness d2 of the second material layer 12b, i.e., 15 nm, 10 nm, and 5 nm, respectively.

[0088] It is found through experiments that by limiting the thickness of the second material layer 12b to a range greater than 10 nm, the stability of the thin film transistor 1 under the NBIS condition can be improved while maintaining a relatively high carrier mobility of the thin film transistor 1. For example, in the case where the thickness d of the semiconductor layer 12 is 30 nm, when the thickness d1 of the first material layer 12a is 5 nm and the thickness d2 of the second material layer 12b is 25 nm, the carrier mobility of the thin film transistor 1 can reach 27.2 cm 2Vs, the threshold voltage of the thin film transistor 1 under NBIS is only negatively shifted by 1.56V. When the thickness d1 of the first material layer 12a is 10nm and the thickness d2 of the second material layer 12b is 20nm, the carrier mobility of the thin film transistor 1 can reach 36.4cm 2 Vs, the threshold voltage of the thin film transistor 1 under NBIS is only negatively shifted by 1.12V. When the thickness d1 of the first material layer 12a is 15nm and the thickness d2 of the second material layer 12b is 15nm, the carrier mobility of the thin film transistor 1 can reach 49.3cm 2 Vs, the threshold voltage of the thin film transistor 1 under NBIS is only negatively shifted by 1.70V. While the thickness d1 of the first material layer 12a is 20nm and the thickness d2 of the second material layer 12b is 10nm, the carrier mobility of the thin film transistor 1 can reach 50.1cm 2 Vs, the threshold voltage of the thin film transistor 1 under NBIS is only negatively shifted by 1.56V. When the thickness d1 of the first material layer 12a is 10nm and the thickness d2 of the second material layer 12b is 20nm, the carrier mobility of the thin film transistor 1 can reach 36.4cm

[0089] In addition, it is found through experiments that, by reasonably setting the thickness d1 of the first material layer 12a, the carrier mobility and the light stability of the thin film transistor 1 can be simultaneously considered, and the thickness d1 of the first material layer 12a does not need to be limited in the range of less than 10nm. This is because: the photoelectron relaxation ability of the rare earth doping in the second material layer 12b is sufficient to relax the total photoelectron of the first material layer 12a and the second material layer 12b, so that high mobility and high light stability can be realized in a wider range of the thickness d1 of the first material layer 12a, without the need for an excessively thin first material layer 12a, thereby improving the uniformity of the first material layer 12a.

[0090] In some embodiments, when the thickness d2 of the second material layer 12b is less than or equal to 15nm, the ratio of the thickness d1 of the first material layer 12a to the thickness d2 of the second material layer 12b is less than or equal to 1.

[0091] That is, when the thickness d of the semiconductor layer 12 is 30nm, the thickness d2 of the second material layer 12b can be 15nm, and at this time, the thickness d1 of the first material layer 12a can also be 15nm. In this case, the bias stability of the thin film transistor 1 under NBIS is the best.

[0092] In some embodiments, when the thickness d2 of the second material layer 12b is greater than 15 nm, the thickness d1 of the first material layer 12a is greater than or equal to 20 nm, and the ratio of the thickness d1 of the first material layer 12a to the thickness d2 of the second material layer 12b is less than or equal to 2.

[0093] In some embodiments, when the thickness d1 of the first material layer 12a is 20 nm, the thickness d2 of the second material layer 12b can be 20 nm, 30 nm, etc.

[0094] It is found through experiments that, when the thickness d1 of the first material layer 12a is kept in a range greater than 20 nm, the thickness d2 of the second material layer 12b is greater than 15 nm, and the ratio of the thickness d1 of the first material layer 12a to the thickness d2 of the second material layer 12b is less than or equal to 2, the bias stability of the thin film transistor 1 under NBIS can be improved while ensuring a higher carrier mobility of the thin film transistor 1.

[0095] For example, when the thickness d1 of the first material layer 12a is 20 nm, the thickness d2 of the second material layer 12b can be 16 nm, 20 nm, 25 nm, or 30 nm, etc. It is found through experiments that, when the thickness d1 of the first material layer 12a is 20 nm and the thickness d2 of the second material layer 12b is 20 nm, the carrier mobility of the thin film transistor 1 can reach 50.1 cm 2 Vs, and the threshold voltage of the thin film transistor under NBIS is negatively shifted by 4.66 V. When the thickness d1 of the first material layer 12a is 20 nm and the thickness d2 of the second material layer 12b is 30 nm, the carrier mobility of the thin film transistor 1 can reach 47.0 cm 2 Vs, and the threshold voltage of the thin film transistor 1 under NBIS is negatively shifted by only 1.56 V. It can be known that, when the thickness d1 of the first material layer 12a is 20 nm, the NBIS stability of the thin film transistor 1 can be improved by increasing the thickness d2 of the second material layer 12b, and meanwhile, as the thickness d2 of the second material layer 12b continuously increases, the carrier mobility of the thin film transistor 1 is not affected. In addition, as the thickness d2 of the second material layer 12b continuously increases, the bias stability of the thin film transistor 1 under NBIS shows a trend of increase.

[0096] In order to avoid the problem of insufficient uniformity caused by too thin thickness d1 of the first material layer 12a, in some embodiments, the thickness d1 of the first material layer 12a is greater than or equal to 10 nm.

[0097] In some embodiments, the thickness d of the semiconductor layer 12 is 30 nm to 70 nm. The application requirements can be met.

[0098] Based on the above specific embodiments, in order to objectively evaluate the technical effects of the technical solutions provided by the present disclosure, the following will describe the technical solutions provided by the present disclosure in detail through Examples and Comparative Examples.

[0099] Comparative Example 1

[0100] The preparation method of the thin film transistor in Comparative Example 1 is as follows:

[0101] Step 1), p-type heavily doped silicon was used as the bottom gate (gate 13) and the substrate 11, and after ultrasonic cleaning and drying, a 100 nm thick SiO2 layer was grown thereon as the gate insulating layer 14.

[0102] Step 2), a layer of indium tin zinc oxide (ITZO, In:Sn:Zn=2:1:2, i.e., the atomic ratio of In, Sn and Zn is 2:1:2) thin film was deposited on the gate insulating layer 14 by magnetron sputtering, with a thickness of 30 nm; the magnetron sputtering deposition parameters were: direct current power of 80 W, argon flow rate of 20 sccm (Standard Cubic Centimeter per Minute), oxygen flow rate of 10 sccm, working pressure of 0.18 Pa, and the indium tin zinc oxide (ITZO, In:Sn:Zn=2:1:2) thin film was patterned to obtain the semiconductor layer 12.

[0103] Step 3), the source 15 and the drain 16 (such as indium tin oxide (ITO) thin film) were deposited on the substrate with the semiconductor layer 12 formed thereon by magnetron sputtering, with a thickness of 100 nm; the width and length of the channel of the semiconductor layer 12 of the thin film transistor 1 were defined as 800 μm and 400 μm, respectively, by using a mask plate process.

[0104] Step 4), annealing was completed by heat treatment at 350°C for 1 h in air atmosphere to obtain the ITZO thin film transistor.

[0105] Comparative Example 2

[0106] The preparation method of the thin film transistor in Comparative Example 2 is basically the same as that of the thin film transistor 1 in Comparative Example 1, except that the material of the semiconductor layer 12 in Step 2) in Comparative Example 2 is praseodymium-doped indium tin zinc oxide (ITZO:Pr, In:Sn:Zn:Pr=1:2:2:0.17, i.e., the atomic ratio of In, Sn, Zn and Pr is 1:2:2:0.17), and the magnetron sputtering deposition parameters are: radio frequency power of 80 W, argon flow rate of 15 sccm, and working pressure of 0.1 Pa.

[0107] Example 1

[0108] The fabrication method of the thin-film transistor 1 in Experimental Example 1 is basically the same as that in Comparative Example 1. The difference is that in step 2) of Experimental Example 1, the semiconductor layer 12 includes a first material layer 12a and a second material layer 12b. The material of the first material layer 12a is indium zinc tin oxide (ITZO, In:Sn:Zn = 2:1:2), and the material of the second material layer 12b is praseodymium-doped indium zinc tin oxide (ITZO:Pr, In:Sn:Zn:Pr = 1:1:2). 2:2:0.17), wherein the thickness d1 of the first material layer 12a is 5 nm, and the thickness d2 of the second material layer 12b is 25 nm. The preparation method of the first material layer 12a can refer to the preparation method of the indium zinc tin oxide (ITZO) thin film in Comparative Example 1, and the preparation method of the second material layer 12b can refer to the preparation method of the praseodymium-doped indium zinc tin oxide (ITZO:Pr, In:Sn:Zn:Pr=1:2:2:0.17) thin film in Comparative Example 2.

[0109] Experiment Example 2

[0110] The fabrication method of the thin-film transistor in Experiment 2 is basically the same as that in Experiment 1. The difference is that the thickness d1 of the first material layer 12a in Experiment 2 is 10 nm, and the thickness d2 of the second material layer 12b is 20 nm.

[0111] Experimental Example 3

[0112] The fabrication method of the thin-film transistor in Experiment 3 is basically the same as that in Experiment 1. The difference is that the thickness d1 of the first material layer 12a in Experiment 3 is 15 nm, and the thickness d2 of the second material layer 12b is 15 nm.

[0113] Experiment Example 4

[0114] The fabrication method of the thin-film transistor in Experiment 4 is basically the same as that in Experiment 1. The difference is that the thickness d1 of the first material layer 12a in Experiment 4 is 20 nm, and the thickness d2 of the second material layer 12b is 10 nm.

[0115] like FIG. 4A As shown, the monolayer semiconductor layer indium zinc tin (ITZO) thin-film transistor prepared in Comparative Example 1 has a carrier mobility μ FE It is 51.6cm 2 / Vs, subthreshold slope SS is 0.15V / dec, switching current ratio I on / I off 1.31×10 8 .like FIG. 4BAs shown, the indium zinc tin (ITZO) thin-film transistor prepared in Comparative Example 1 exhibits poor negative bias photo-irradiation stress (NBIS) stability, with a threshold voltage ΔV reaching a low value in the 3600s test. th The negative shift is greater than 15V.

[0116] like FIG. 4A As shown, the indium zinc tin (ITZO:Pr) thin-film transistor with a single praseodymium-doped semiconductor layer prepared in Comparative Example 2 has a carrier mobility μ FE It is 16.2cm 2 / Vs, subthreshold slope SS is 0.20V / dec, switching current ratio I on / I off It is 0.28×10 8 .like FIG. 4C As shown, the negative bias photo-irradiation stress (NBIS) stability of the praseodymium-doped indium zinc tin oxide (ITZO:Pr) thin-film transistor prepared in Comparative Example 2 is shown in the threshold voltage ΔV during a 3600s test. th The negative shift is only 0.71V.

[0117] like FIG. 4D As shown, the double-layer semiconductor ITZO / ITZO:Pr thin-film transistor prepared in Experimental Example 1 (with the first material layer (ITZO) having a thickness d1 of 5 nm and the second material layer (ITZO:Pr) having a thickness d2 of 25 nm) exhibits a carrier mobility μ FE Height 27.2cm 2 / Vs, subthreshold slope SS as low as 0.22V / dec, switching current ratio I on / I off Up to 0.85×10 8 .like FIG. 4E As shown, the double-layer semiconductor ITZO / ITZO:Pr thin-film transistor 1 prepared in Experimental Example 1 (with the first material layer having a thickness d1 of 5 nm and the second material layer having a thickness d2 of 25 nm) exhibits excellent negative bias photo-irradiation stress (NBIS) stability. In a 3600s test, the threshold voltage ΔV... th Only a negative shift of 1.56V.

[0118] like FIG. 4D As shown, the double-layer semiconductor ITZO / ITZO:Pr thin-film transistor prepared in Experimental Example 2 (with the first material layer (ITZO) having a thickness d1 of 10 nm and the second material layer (ITZO:Pr) having a thickness d2 of 20 nm) exhibits a carrier mobility μ FE Height 36.4cm 2 / Vs, subthreshold slope SS as low as 0.15V / dec, switching current ratio I on / Ioff Up to 1.18×10 8 .like FIG. 4F As shown, the double-layer semiconductor ITZO / ITZO:Pr thin-film transistor prepared in Experimental Example 2 (with the first material layer having a thickness d1 of 10 nm and the second material layer having a thickness d2 of 20 nm) exhibits excellent negative bias photo-irradiation stress (NBIS) stability, with a threshold voltage ΔV reaching a certain value in a 3600s test. th Only a negative shift of 1.12V.

[0119] like FIG. 4D As shown, the double-layer semiconductor ITZO / ITZO:Pr thin-film transistor prepared in Experimental Example 3 (where the thickness d1 of the first material layer (ITZO) is 15 nm and the thickness d2 of the second material layer (ITZO:Pr) is 15 nm) has a carrier mobility μ FE Height 49.3cm 2 / Vs, subthreshold slope SS as low as 0.19V / dec, switching current ratio I on / I off Up to 1.70×10 8 .like FIG. 4G As shown, the double-layer semiconductor ITZO / ITZO:Pr thin-film transistor prepared in Experimental Example 3 (with the first material layer (ITZO) having a thickness d1 of 15 nm and the second material layer (ITZO:Pr) having a thickness d2 of 15 nm) exhibits excellent negative bias photo-irradiation stress (NBIS) stability, with a threshold voltage ΔV reaching a certain value in the 3600s test. th Only a negative shift of 1.70V.

[0120] like FIG. 4D As shown, the double-layer semiconductor ITZO / ITZO:Pr thin-film transistor prepared in Experimental Example 4 (with the first material layer (ITZO) having a thickness d1 of 20 nm and the second material layer (ITZO:Pr) having a thickness d2 of 10 nm) exhibits a carrier mobility μ FE Up to 50.1cm tall 2 / Vs, subthreshold slope SS as low as 0.25V / dec, switching current ratio I on / I off Up to 1.03×10 8 .like FIG. 4H As shown, the negative bias photo-irradiation stress (NBIS) stability of the double-layer semiconductor ITZO / ITZO:Pr thin-film transistor prepared in Experimental Example 4 (where the thickness d1 of the first material layer (ITZO) is 20 nm and the thickness of the second material layer (ITZO:Pr) is 10 nm) deteriorates, and the threshold voltage ΔV decreases in the 3600s test. th The negative shift is 9.13V.

[0121] The performance parameters of the thin film transistors in the above Comparative Examples 1 to 2 and Experimental Examples 1 to 4 are shown in Table 1 below.

[0122] Table 1

[0123] d1 / d2 Vth(V) μ FE( cm 2 / Vs ) ]]> SS(V / dec) I on / I off (×10 8 )]]> NBIS 5nm / 25nm 0.22 27.2 0.22 0.85 -1.56 10nm / 20nm 0.02 36.4 0.15 1.18 -1.12 15nm / 15nm -0.30 49.3 0.19 1.70 -1.7 20nm / 10nm -0.05 50.1 0.25 1.03 -5.75 ITZO:Pr 1.16 16.2 0.20 0.28 -0.71 ITZO -0.14 51.6 0.15 1.31 -15

[0124] As shown in Table 1 and FIG. 4A to FIG. 4F , by setting two layers of material, with the thickness of the semiconductor layer 12 being constant, the thin film transistor can have both the characteristics of high carrier mobility of the first material layer 12a and good negative bias illumination stress stability of the second material layer 12b. In addition, as the ratio of the thickness d1 of the first material layer 12a to the thickness d2 of the second material layer 12b increases, the carrier mobility μ FE increases, while the NBIS stability changes little. When the ratio of the thickness d1 of the first material layer 12a to the thickness d2 of the second material layer 12b is 15 nm / 15 nm, the thin film transistor has the best performance.

[0125] Experimental Example 5

[0126] The preparation method of the thin film transistor in Experimental Example 5 is basically the same as that in Experimental Example 1, except that the thickness d1 of the first material layer 12a is 20 nm and the thickness d2 of the second material layer 12b is 20 nm in Experimental Example 5.

[0127] Experimental Example 6

[0128] The preparation method of the thin film transistor in Experimental Example 6 is basically the same as that in Experimental Example 1, except that the thickness d1 of the first material layer 12a is 20 nm and the thickness d2 of the second material layer 12b is 30 nm in Experimental Example 6.

[0129] As shown in Table 1 and FIG. 4I , the thin film transistor prepared in Experimental Example 5 (the thickness d1 of the first material layer (ITZO) is 20 nm and the thickness d2 of the second material layer (ITZO:Pr) is 20 nm) has a carrier mobility μ FE as high as 47.0 cm 2 / Vs, a subthreshold slope SS as low as 0.20 V / dec, and an on / off current ratio I on / I off as high as 1.16×10 8 . As shown in Table 1 and FIG. 4JAs shown, the negative bias photo-irradiation stress (NBIS) stability of the double-layer semiconductor ITZO / ITZO:Pr thin-film transistor prepared in Experimental Example 5 (where the thickness d1 of the first material layer (ITZO) is 20 nm and the thickness d2 of the second material layer (ITZO:Pr) is 20 nm) is improved compared to that of the transistor with a thickness ratio of 20 / 10. In the 3600s test, the threshold voltage ΔV... th The negative shift is 4.66V.

[0130] like FIG. 4I As shown, the double-layer semiconductor ITZO / ITZO:Pr thin-film transistor prepared in Experimental Example 6 (with the first material layer (ITZO) having a thickness d1 of 20 nm and the second material layer (ITZO:Pr) having a thickness d2 of 30 nm) exhibits a carrier mobility μ FE Height 47.0cm 2 / Vs, subthreshold slope SS as low as 0.17V / dec, switching current ratio I on / I off Up to 0.88×10 8 .like FIG. 4K As shown, the double-layer semiconductor ITZO / ITZO:Pr thin-film transistor 1 prepared in Experimental Example 6 (with the first material layer (ITZO) having a thickness d1 of 20 nm and the second material layer (ITZO:Pr) having a thickness d2 of 30 nm) exhibits excellent negative bias photo-irradiation stress (NBIS) stability. In a 3600s test, the threshold voltage ΔV... th The negative shift is 1.56V.

[0131] The performance parameters of the thin-film transistors in Experiments 4 to 6 are shown in Table 2 below.

[0132] Table 2

[0133] d1 / d2 Vth(V) μ FE( cm 2 / Vs ) ]]> SS(V / dec) I on / I off (×10 8 )]]> NBIS 20nm / 10nm -0.05 50.1 0.25 1.03 -5.75 20nm / 20nm -0.27 47.0 0.20 1.16 -4.66 20nm / 30nm -0.04 47.0 0.17 0.88 -1.56

[0134] Combination FIG. 4I to FIG. 4K As shown in Table 2, with the thickness d1 of the first material layer 12a fixed at 20 nm, increasing the thickness d2 of the second material layer 12b significantly improves the stability of NBIS, while the carrier mobility μ FE There is essentially no change. The thin-film transistor exhibits the best performance when the ratio of the thickness d1 of the first material layer 12a to the thickness d2 of the second material layer 12b is 20nm / 30nm.

[0135] Comparative Example 3

[0136] The fabrication method of the thin-film transistor in Comparative Example 3 is basically the same as that in Comparative Example 2. The difference is that the material of semiconductor layer 12 in Comparative Example 3 is terbium-doped indium zinc tin oxide (ITZO:Tb, In:Sn:Zn:Tb=1:2:2:0.15, that is, the ratio of the number of In, Sn, Zn and Tb atoms is 1:2:2:0.15).

[0137] Experimental Example 7

[0138] The fabrication method of the thin-film transistor in Experiment 7 is basically the same as that in Experiment 1. The difference is that the material of the second material layer 12b in Experiment 7 is terbium-doped indium zinc tin oxide (ITZO:Tb, In:Sn:Zn:Tb=1:2:2:0.15, that is, the ratio of the number of atoms of In, Sn, Zn and Tb is 1:2:2:0.15), and the thickness d1 of the first material layer 12a is 10nm and the thickness d2 of the second material layer 12b is 20nm.

[0139] The terbium-doped indium zinc tin oxide (ITZO:Tb) thin-film transistor with a single semiconductor layer prepared in Comparative Example 3 has a carrier mobility μ FE It is 17.4cm 2 / Vs, subthreshold slope SS is 0.25V / dec, switching current ratio I on / I off It is 0.29×10 8 The negative bias photo-irradiation stress (NBIS) stability of the terbium-doped indium zinc tin oxide (ITZO:Tb) thin-film transistor prepared in Comparative Example 3, with a threshold voltage ΔV in a 3600s test, was compared to that of the terbium-doped indium zinc tin oxide (ITZO:Tb) thin-film transistor. th The negative shift is only 1.12V.

[0140] The double-layer semiconductor ITZO / ITZO:Tb thin-film transistor prepared in Example 7 (with the first material layer (ITZO) having a thickness d1 of 10 nm and the second material layer (ITZO:Tb) having a thickness d2 of 20 nm) exhibits a carrier mobility μ FE Height 39.1cm 2 / Vs, subthreshold slope SS as low as 0.17V / dec, switching current ratio I on / I off Up to 1.23×10 8 The double-layer semiconductor thin-film transistor prepared in Example 7 (ITZO / ITZO:Tb, where the thickness d1 of the first material layer (ITZO) is 10 nm and the thickness d2 of the second material layer (ITZO:Tb) is 20 nm) exhibits good negative bias photo-irradiation stress (NBIS) stability, with a threshold voltage ΔV reaching a certain value in the 3600s test. thThe negative shift is 2.13 V. The performance parameters of the thin film transistors in the above-mentioned Comparative Example 1, Comparative Example 3 and Experimental Example 7 are shown in Table 3.

[0141] Table 3

[0142] d1 / d2 Vth(V) μ FE( cm 2 / Vs ) ]]> SS(V / dec) I on / I off (×10 8 )]]> NBIS 10nm / 20nm -0.21 39.1 0.17 1.23 -2.13 ITZO:Tb 0.41 17.4 0.25 0.29 -1.12 ITZO -0.14 51.6 0.15 1.31 -15

[0143] As can be seen from Table 3, by setting two layers of material, the material of the first material layer 12a is ITZO material, and the material of the second material layer is ITZO:Tb material, the thin film transistor 1 can have both the high carrier mobility of the first material layer 12a and the good NBIS stability of the second material layer 12b.

[0144] In summary, by setting the first material layer 12a and the second material layer 12b, the material of the first material layer 12a is selected from a material with high carrier mobility, which is used as a front channel layer, and the material of the second material layer 12b is an n-type metal oxide semiconductor material doped with a rare earth element, which is used as a back channel layer. The thin film transistor 1 obtained by combining the high carrier mobility of the material of the first material layer 12a and the good stability of the material of the second material layer 12b under NBIS can simultaneously consider the carrier mobility and the light stability, thereby improving the comprehensive performance of the thin film transistor 1. In addition, by reasonably setting the thickness d1 of the first material layer 12a and the thickness d2 of the second material layer 12b, the photoelectron relaxation ability of the second material layer 12b is sufficient to relax the total photoelectron of the first material layer 12a and the second material layer 12b, ensuring good light stability of the thin film transistor and maintaining a wide range of thickness d1 of the first material layer 12a, avoiding the problem of uncontrollable uniformity in the preparation process caused by the too thin thickness d1 of the first material layer 12a.

[0145] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can think of changes or replacements within the technical scope disclosed in the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A thin film transistor comprising: a substrate; a semiconductor layer, a gate electrode, and a source electrode and a drain electrode provided on the substrate; the semiconductor layer includes a first material layer and a second material layer stacked; a material of the first material layer is selected from one or more combinations of a first n-type metal oxide semiconductor material, and a material of the second material layer is selected from one or more combinations of a second n-type metal oxide semiconductor material; the first n-type metal oxide semiconductor material has a carrier mobility greater than or equal to 40 cm 2 Vs, the second n-type metal oxide semiconductor material doped with Y selected from one or more combinations of rare earth elements; wherein the first material layer is closer to the gate electrode than the second material layer, a thickness of the second material layer is greater than 10 nm and less than or equal to 15 nm, and a ratio of a thickness of the first material layer to the thickness of the second material layer is less than or equal to 1.

2. The thin film transistor according to claim 1, wherein a doping ratio of the Y in the second n-type metal oxide semiconductor material is 0.01 at% to 0.30 at%.

3. The thin film transistor according to claim 1 or 2, wherein the first n-type metal oxide semiconductor material is further doped with Z, the Z is selected from one or more combinations of rare earth elements, and a kind of the rare earth elements doped in the first n-type metal oxide semiconductor material is the same as or different from a kind of the rare earth elements doped in the second n-type metal oxide semiconductor material.

4. The thin film transistor according to claim 1 or 2, wherein a kind of elements included in the first material layer is the same as a kind of elements included in the second material layer, and a ratio of an atomic number of each element is different.

5. The thin film transistor according to claim 1 or 2, wherein the first n-type metal oxide semiconductor material is selected from a metal oxide doped with X or not doped with X; the metal oxide includes one or more elements of indium, zinc, tin, and gallium, and an oxygen element, and the X is selected from one or more combinations of aluminum, tungsten, hafnium, tantalum, zirconium, nitrogen, and hydrogen.

6. The thin film transistor according to claim 1, wherein as the ratio of the thickness of the first material layer to the thickness of the second material layer gradually increases, a carrier mobility of the thin film transistor increases.

7. The thin film transistor according to claim 1 or 2, wherein the thickness of the first material layer is greater than or equal to 10 nm.

8. The thin film transistor according to claim 1 or 2, wherein a thickness of the semiconductor layer is 30 nm to 70 nm.

9. A display panel comprising: The thin film transistor according to any one of claims 1 to 8.

10. A display device including the display panel according to claim 9.

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