Integrated circuit and method of operating the same

Abstract

The present disclosure generally relates to integrated circuits and methods of operating the same. An integrated circuit for driving multiple fluid-actuated devices includes a plurality of first nonvolatile memory cells and control logic. Each first nonvolatile memory cell stores a custom bit. The control logic configures the operation of the integrated circuit based on the custom bit.

Description

[0001] This case is a divisional application of the application with international application number PCT / US2019 / 016905, international application date February 6, 2019, entry into the Chinese national phase date August 5, 2021, national application number 201980091354.2, and invention name “Integrated Circuit and Its Operating Method”. Technical Field

[0002] The present disclosure generally relates to integrated circuits including custom bits. Background Art

[0003] An inkjet printing system, an example of a fluid ejection system, may include a printhead, an ink supply that supplies liquid ink to the printhead, and an electronic controller that controls the printhead. The printhead, an example of a fluid ejection device, ejects ink droplets through a plurality of nozzles or orifices onto a print medium (e.g., a sheet of paper) to print on the print medium. In some examples, the orifices are arranged in at least one column or array so that when the printhead and the print medium are moved relative to each other, ink ejection from the orifices in a suitable sequence causes characters or other images to be printed on the print medium. Summary of the Invention

[0004] According to one aspect of the present disclosure, an integrated circuit is provided for a fluid ejection device including a plurality of fluid actuation devices, the integrated circuit comprising: a plurality of first non-volatile memory cells, each first non-volatile memory cell storing a custom bit; and control logic for configuring an operation of the integrated circuit based on the custom bit, wherein the operation is for modifying an address input to the integrated circuit based on the custom bit.

[0005] According to another aspect of the present disclosure, a method for operating an integrated circuit for driving a plurality of fluid actuation devices is provided, the method comprising: reading a plurality of custom bits stored in a corresponding plurality of first non-volatile memory cells; receiving an address from a nozzle data stream; and summing the custom bits and the address to generate a modified address. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A is a block diagram illustrating one example of an integrated circuit for driving multiple fluid actuation devices.

[0007] Figure 1B is a block diagram illustrating another example of an integrated circuit for driving a plurality of fluid actuation devices.

[0008] Figure 2 An example of an address modifier is shown.

[0009] Figure 3is a block diagram illustrating another example of an integrated circuit for driving a plurality of fluid actuation devices.

[0010] Figure 4A is a schematic diagram illustrating one example of a circuit for accessing a memory cell storing a custom bit.

[0011] Figure 4B is a schematic diagram illustrating one example of a circuit for accessing a memory cell storing a lock bit.

[0012] Figure 5 One example of a fluid ejection device is illustrated.

[0013] Figure 6A and Figure 6B One example of a fluid jet die is illustrated.

[0014] Figure 7 is a block diagram illustrating one example of a fluid ejection system.

[0015] Figures 8A to 8C is a flow chart illustrating an example of a method for operating an integrated circuit for driving a plurality of fluid actuation devices. DETAILED DESCRIPTION

[0016] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description and show, by way of illustration, specific examples in which the present disclosure may be practiced. It should be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be understood as limiting, and the scope of the present disclosure is defined by the appended claims. It should be understood that, unless otherwise specifically noted, the features of the various examples described herein may be combined with each other in part or in whole.

[0017] It may be advantageous to have an integrated circuit (e.g., a semiconductor die) behave differently for different geographic regions, for subscribing or non-subscribing customers, or for other reasons. It may be easier to write a few non-volatile memory bits to the integrated circuit (e.g., during manufacturing) to change the behavior of the integrated circuit than to create multiple physical integrated circuits designed to behave differently (which may have to be tracked or managed separately).

[0018] Thus, disclosed herein is an integrated circuit (e.g., a fluid jet die) that includes a plurality of memory cells each storing a custom bit. In one example, the custom bit can be used to modify an address input to the die by summing the custom bit with an address from a nozzle data stream to generate a modified address. The modified address can be used to activate a fluid actuation device or access a memory cell corresponding to the fluid actuation device based on the modified address. In other examples, the custom bit can be used to configure other operations of the integrated circuit, as described below.

[0019] As used herein, a "logic high" signal is a logic "1" or "on" signal or a signal having a voltage approximately equal to the logic power supplied to the integrated circuit (e.g., between approximately 1.8 V and 15 V, such as 5.6 V). As used herein, a "logic low" signal is a logic "0" or "off" signal or a signal having a voltage approximately equal to the logic power ground return of the logic power supplied to the integrated circuit (e.g., approximately 0 V).

[0020] Figure 1A FIG. 1 is a block diagram illustrating an example of an integrated circuit 100 for driving a plurality of fluid actuation devices. The integrated circuit 100 includes a plurality of memory cells 1020 to 102 N , where "N" is any suitable number of memory cells (e.g., four memory cells). Integrated circuit 100 also includes control logic 106. Control logic 106 is provided through signal paths 1010 to 101 respectively. N electrically coupled to each memory cell 1020 to 102 N .

[0021] Each of the first memory cells 1020 to 102 N Each first memory cell 1020 to 102 stores a custom bit. N Non-volatile memory cells (e.g., floating gate transistors, programmable fuses, write-once memory cells, etc.) may be included. Control logic 106 may include a microprocessor, an application specific integrated circuit (ASIC), or other suitable logic circuitry for controlling the operation of integrated circuit 100. Control logic 106 may prevent access to the plurality of memory cells 1020 to 102 N External read access. Once the custom bits are written to memory cells 1020 to 102 N , such as by writing the lock bits, it is possible to disable access to the plurality of memory cells 1020 to 102 N Write access, as will be referenced below Figure 3 described.

[0022] The control logic 106 can configure the operation of the integrated circuit 100 based on the custom bits. In one example, the operation can be used to modify the address input to the integrated circuit 100 based on the custom bits. In another example, access to additional memory cells (e.g., as described below) of the integrated circuit can be blocked or allowed based on the custom bits. Figure 1B In another example, a data stream (e.g., a nozzle data stream) or at least a portion of a data stream received by the integrated circuit 100 can be inverted based on a custom bit. The data stream or portion of the data stream can be inverted anywhere along the data stream path. Multiple custom bits can be used for multiple inversion points.

[0023] In yet another example, the behavior of bits stored in a configuration register (not shown) of the integrated circuit 100 can be modified based on the custom bits. For example, a delay bit in the configuration register used to set the delay of a function of the integrated circuit 100 can be inverted and / or encoded based on the custom bits. In any case, a single custom bit or a subset of custom bits can be used to configure a single operation of the integrated circuit 100. Thus, the custom bits can be used to configure multiple operations of the integrated circuit 100, where each operation is configured based on a different custom bit.

[0024] Figure 1B 1 is a block diagram illustrating another example of an integrated circuit 120 for driving multiple fluid actuation devices. Integrated circuit 120 includes multiple first memory cells 1020 to 1023 and control logic 106. In addition, integrated circuit 120 includes a fluid actuation device 128 and multiple second memory cells 130. In this example, control logic 106 includes an address modifier 122. Address modifier 122 is electrically coupled to address signal path 124, electrically coupled to each first memory cell 1020 to 1023 via signal paths 1010 to 1013, and electrically coupled to fluid actuation device 128 and multiple second memory cells 130 via modified address signal path 126. Each of multiple second memory cells 130 includes a non-volatile memory cell (e.g., a floating gate transistor, a programmable fuse, etc.). In one example, fluid actuation device 128 includes a nozzle or a fluid pump for ejecting droplets.

[0025] In this example, there are four memory cells 1020 to 1023 to store four custom bits. The custom bits define the integrated circuit 120 as one of 16 separate integrated circuits. Each of the 16 separate integrated circuits operates differently due to the stored custom bits.

[0026] The address modifier 122 receives the address via the address signal path 124. In one example, the address is part of the nozzle data stream input to the integrated circuit 120 from the host printing device, as will be referenced below. Figure 7 The fluid ejection system 700 is described. The address modifier 122 also receives the stored custom bits from each of the first memory cells 1020 to 1023. The address modifier 122 modifies the address input to the integrated circuit 120 based on the custom bits to provide the modified address on the signal path 126. In one example, the control logic 106 activates the fluid actuation device 128 based on the modified address. In another example, the control logic 106 accesses the second memory cell 130 based on the modified address.

[0027] Figure 2 An example of an address modifier 122 is shown. In this example, the address modifier 122 is a four-bit adder. A first input of the four-bit adder 122 receives four address bits (ADDR0, ADDR1, ADDR2, and ADDR3) via signal path 124. A second input of the four-bit adder 122 receives four custom bits (CUST0, CUST1, CUST2, and CUST3) via signal paths 1010 through 1013, respectively. The four-bit adder 122 adds the four address bits and the four custom bits to generate a modified address comprising four bits on signal path 126. In one example, the most significant bit of the sum is discarded.

[0028] Figure 3 FIG. 1 is a block diagram illustrating another example of an integrated circuit 200 for driving a plurality of fluid actuation devices. The integrated circuit 200 includes a plurality of first memory cells 2020 to 202 N , a plurality of first storage elements 2040 to 204 N and control logic 206. In addition, the integrated circuit 200 includes a second memory unit 222, a second storage element 224, a write circuit 230, and a read circuit 232. The control logic 206 is respectively connected to the second memory unit 222 through the signal paths 2010 to 201 N electrically coupled to each first memory cell 2020 to 202 N , respectively, through signal paths 2030 to 203 N electrically coupled to each first storage element 2040 to 204 N , and is electrically coupled to the reset signal path 210. Each of the first memory cells 2020 to 202 N Respectively through signal paths 2080 to 208 N electrically coupled to corresponding first storage elements 2040 to 204 N .

[0029] The control logic 206 is also electrically coupled to the second memory unit 222 via a signal path 221 and to the storage element 224 via a signal path 223. The second memory unit 222 is electrically coupled to the storage element 224 via a signal path 228. Each of the first memory units 2020 to 202 N , the second memory cell 222 , the write circuit 230 , and the read circuit 232 are electrically coupled to a single interface (eg, a single conductor) 234 . The read circuit 232 is electrically coupled to an interface (eg, a sense interface) 236 .

[0030] The reset signal path 210 can be electrically coupled to a reset interface, which can be a contact pad, pin, bump, wire, or other suitable electrical interface for transmitting signals to and / or from the integrated circuit 200. The reset interface can be electrically coupled to a fluid ejection system (e.g., a host printing device, as will be referenced below). Figure 7 The sensing interface 236 may be a contact pad, pin, bump, wire, or other suitable electrical interface for transmitting signals to and / or from the integrated circuit 200. The sensing interface 236 may be electrically coupled to a fluid ejection system (e.g., a host printing device such as Figure 7 Fluid injection system 700).

[0031] Each of the first memory cells 2020 to 202 N Each first memory cell 2020 to 202 stores a custom bit. N Each of the first storage elements 2040 to 204 includes a non-volatile memory cell (eg, a floating gate transistor, a programmable fuse, etc.). N Control logic 206 may include a microprocessor, an application specific integrated circuit (ASIC), or other suitable logic circuitry for controlling the operation of integrated circuit 200.

[0032] In response to the reset signal on the reset signal path 210, the control logic 206 reads (eg, in response to a first edge of the reset signal) the data stored in each of the first memory cells 2020 to 2021. N and latching each custom bit (eg, in response to a second edge of a reset signal) in a corresponding first storage element 2040 to 204 N In one example, the control logic 206 configures the operation of the integrated circuit 200 based on the latched custom bits. In one example, the operation may modify the address input to the integrated circuit 200 based on the latched custom bits. In other examples, other operations of the integrated circuit 200 may be modified based on the latched custom bits, as previously described above.

[0033] The second memory cell 222 stores a lock bit. The second memory cell 222 includes a non-volatile memory cell (e.g., a floating-gate transistor, a programmable fuse, etc.). The second storage elements 224 include latches or other suitable circuits that output a logic signal (i.e., a logic high signal or a logic low signal) that can be directly used by digital logic. In response to the reset signal, the control logic 206 reads (e.g., in response to a first edge of the reset signal) the lock bit stored in the second memory cell 222 and latches the lock bit in the second storage element 224 (e.g., in response to a second edge of the reset signal). In addition, the control logic 206 allows or prevents writing to the plurality of first memory cells 2020 to 2024 based on the latched lock bit. N In one example, the control logic 206 also allows or prevents writing to the second memory cell 222 based on the latched lock bit. For example, if a "0" lock bit is stored in the second memory cell 222, the data stored in the first memory cells 2020 to 2022 may be modified. N Once the "1" lock bit is written to the second memory cell 222, the data stored in the first memory cells 2020 to 202 cannot be modified. N The customization bit in the second memory unit 222 cannot be modified and the lock bit stored in the second memory unit 222 cannot be modified.

[0034] The write circuit 230 writes the corresponding custom bits to the plurality of first memory cells 2020 to 202 through a single interface 234. N The write circuit 230 may also write the lock bit to the second memory cell 222 through a single interface 234. In one example, the write circuit 230 may include a voltage regulator and / or a circuit for writing the custom bit to the first memory cells 2020 to 202 N And write the lock bit to other appropriate logic circuits of the second memory unit 222.

[0035] The read circuit 232 enables external access (eg, via the sense interface 236) to read the plurality of first memory cells 2020 to 202 through the single interface 234. N The read circuit 232 may also enable external access (e.g., via the sense interface 236) to read the lock bit of the second memory cell 222 through the single interface 234. In one example, the read circuit 232 may include a transistor switch or a circuit for enabling access to the first memory cells 2020 to 2022 through the sense interface 236. Nand other suitable logic circuits for external read access to the second memory cell 222. In one example, the control logic 206 allows or blocks external read access to the plurality of first memory cells 2020 to 202 based on the latched lock bit. N and external read access to the second memory cell 222. For example, if a "0" lock bit is stored in the second memory cell 222, the lock bits stored in the first memory cells 2020 to 202 N The custom bit in the second memory cell 222 and the lock bit stored in the second memory cell 222 can be read by the read circuit 232. Once the "1" lock bit is written to the second memory cell 222, the data stored in the first memory cells 2020 to 202 N The custom bit in the second memory cell 222 and the lock bit stored in the second memory cell 222 cannot be read by the read circuit 232.

[0036] Figure 4A is a schematic diagram illustrating one example of a circuit 300 for accessing a memory cell storing a custom bit. In one example, the circuit 300 is Figure 1A Integrated circuit 100, Figure 1B Integrated circuit 120 or Figure 3 3. Circuit 300 includes a memory cell 302, a latch 304, an internal (reset) read voltage regulator 306, a write voltage regulator 308, an inverter 310, AND gates 312 and 316, OR gates 314 and 318, transistors 320 and 322, and a sense pad 324. Memory cell 302 includes a floating-gate transistor 330 and transistors 332, 334, and 336.

[0037] The input of inverter 310 is electrically coupled to a lock signal path 340. The output of inverter 310 is electrically coupled to a first input of an AND gate 312 via a signal path 311. A second input of AND gate 312 is electrically coupled to a custom bit enable signal path 338. A third input of AND gate 312 is electrically coupled to a select signal (ADDR[X], which corresponds to one of Y address bits from the nozzle data stream, where "Y" is any suitable number of bits (e.g., 4)) path 342. The output of AND gate 312 is electrically coupled to a first input of an OR gate 314 via a signal path 313. A second input of OR gate 314 is electrically coupled to a reset signal path 344. The output of OR gate 314 is electrically coupled to the gate of transistor 332 of memory cell 302 and the gate (G) input of latch 304 via a signal path 315.

[0038] A first input of AND gate 316 is electrically coupled to a write enable signal path 346. A second input of AND gate 316 is electrically coupled to a fire signal path 348. An output of AND gate 316 is electrically coupled to the gate of transistor 334 of memory cell 302 via signal path 317. A first input of OR gate 318 is electrically coupled to the fire signal path 348. A second input of OR gate 318 is electrically coupled to the reset signal path 344. An output of OR gate 318 is electrically coupled to the gate of transistor 336 of memory cell 302 via signal path 319.

[0039] The input of internal (reset) read voltage regulator 306 is electrically coupled to reset signal path 344. The output of internal (reset) read voltage regulator 306 is electrically coupled to one side of the source-drain path of floating-gate transistor 330 of memory cell 302 via signal path 323. The input of write voltage regulator 308 is electrically coupled to memory write signal path 350. The output of write voltage regulator 308 is electrically coupled to one side of the source-drain path of floating-gate transistor 330 of memory cell 302 via signal path 323. Sense pad 324 is electrically coupled to one side of the source-drain path of transistor 320. The gate of transistor 320 and the gate of transistor 322 are electrically coupled to read enable signal path 352. The other side of the source-drain path of transistor 320 is electrically coupled to one side of the source-drain path of transistor 322 via signal path 321. The other side of the source-drain path of transistor 322 is electrically coupled to one side of the source-drain path of floating-gate transistor 330 of memory 302 through signal path 323 .

[0040] The other side of the source-drain path of floating-gate transistor 330 is electrically coupled to one side of the source-drain path of transistor 332 and the data (D) input of latch 304 via signal path 331. Another input of latch 304 is electrically coupled to a preset signal path 354. The output (Q) of latch 304 is electrically coupled to a custom bit signal path 356. The other side of the source-drain path of transistor 332 is electrically coupled to one side of the source-drain path of transistor 334 and one side of the source-drain path of transistor 336 via signal path 333. The other side of the source-drain path of transistor 334 is electrically coupled to a common or ground node 335. The other side of the source-drain path of transistor 336 is electrically coupled to a common or ground node 335.

[0041] Although circuit 300 includes one memory cell 302 and one corresponding latch 304 for storing a custom bit, circuit 300 may include any suitable number of memory cells 302 and corresponding latches 304 for storing a desired number of custom bits. For each custom bit, each memory cell and corresponding latch will be accessed in a manner similar to that described for memory cell 302 and latch 304.

[0042] Circuit 300 receives a custom enable signal on a custom enable signal path 338, a lock signal on a lock signal path 340, an address or select signal on a select signal path 342, a reset signal on a reset signal path 344, a write enable signal on a write enable signal path 346, an excitation signal on an excitation signal path 348, a memory write signal on a memory write signal path 350, a read enable signal on a read enable signal path 352, and a preset signal on a preset signal path 354. The preset signal can be used to overwrite latch 304 during testing to output a desired logic level from latch 304. The custom enable signal and the lock signal can be used to enable or disable write access and external read access to the memory cell storing the custom bit. The address signal can be used to select one of the memory cells storing the custom bit. The custom enable signal, the write enable signal, the memory write signal, the read enable signal, and the preset signal can be based on data stored in a configuration register (not shown) or based on data received from a host printing device. The lock signal is an internal signal output from the latch, such as Figure 3 storage element 224.

[0043] The address signal is received from the host printing device (e.g., via a data interface). The reset signal can be received from the host printing device via the reset interface. The excitation signal can be received from the host printing device via the excitation interface. Each of the data interface, reset interface, and excitation interface can include contact pads, pins, bumps, wires, or other suitable electrical interfaces for transmitting signals to and / or from the circuit 300. Each of the data interface, reset interface, excitation interface, and sense pads 324 can be electrically coupled to a fluid ejection system (e.g., a host printing device, e.g., Figure 7 Fluid injection system 700).

[0044] Inverter 310 receives the lock signal and outputs an inverted lock signal on signal path 311. In response to a logic high custom enable signal, a logic high inverted lock signal, and a logic high select signal, AND gate 312 outputs a logic high signal on signal path 313. In response to a logic low custom enable signal, a logic low inverted lock signal, or a logic low select signal, AND gate 312 outputs a logic low signal on signal path 313.

[0045] In response to a logic high signal or a logic high reset signal on signal path 313, OR gate 314 outputs a logic high signal on signal path 315. In response to a logic low signal and a logic low reset signal on signal path 313, OR gate 314 outputs a logic low signal on signal path 315. In response to a logic high write enable signal and a logic high activate signal, AND gate 316 outputs a logic high signal on signal path 317. In response to a logic low write enable signal or a logic low activate signal, AND gate 316 outputs a logic low signal on signal path 317. In response to a logic high activate signal or a logic high reset signal, OR gate 318 outputs a logic high signal on signal path 319. In response to a logic low activate signal and a logic low reset signal, OR gate 318 outputs a logic low signal on signal path 319.

[0046] In response to a logic high signal on signal path 315, transistor 332 turns on (i.e., conducts) to enable access to memory cell 302. In response to a logic low signal on signal path 315, transistor 332 turns off to disable access to memory cell 302. In response to a logic high signal on signal path 317, transistor 334 turns on to enable write access to memory cell 302. In response to a logic low signal on signal path 317, transistor 334 turns off to disable write access to memory cell 302. In response to a logic high signal on signal path 319, transistor 336 turns on to enable read access to memory cell 302. In response to a logic low signal on signal path 319, transistor 336 turns off to disable read access to memory cell 302. In one example, transistor 334 is a stronger device and transistor 336 is a weaker device. Thus, a stronger device may be used to enable write access, and a weaker device may be used to enable read access to improve the margin for latching the voltage on the signal path 331 .

[0047] In response to a logic high reset signal, internal (reset) read voltage regulator 306 is enabled to output a read voltage bias to signal path 323. In response to a logic low reset signal, internal (reset) read voltage regulator 306 is disabled. Thus, in response to the reset signal transitioning from logic low to logic high, transistors 332 and 336 turn on and internal (reset) read voltage regulator 306 is enabled to read the state of floating-gate transistor 330 (i.e., the resistance representing the stored custom bit). The state of floating-gate transistor 330 is passed to the data (D) input of latch 304 (i.e., as a voltage representing the stored custom bit). In response to the reset signal transitioning from logic high to logic low, the custom bit stored in floating-gate transistor 330 is latched by latch 304, transistors 332 and 336 turn off, and internal (reset) read voltage regulator 306 is disabled. Thus, the custom bit is then available at the output (Q) of latch 304 and, therefore, available to other digital logic on custom bit signal path 356.

[0048] In response to a logic high read enable signal, transistors 320 and 322 are turned on to enable external access to memory cell 302 through sense pad 324. In response to a logic low read enable signal, transistors 320 and 322 are turned off to disable external access to memory cell 302 through sense pad 324. Thus, in response to a logic high custom enable signal, a logic low lock signal, a logic high address signal, a logic high read enable signal, and a logic high fire signal, transistors 320, 322, 332, and 336 are turned on to allow floating-gate transistor 330 to be read by an external circuit through sense pad 324.

[0049] In response to a logic high memory write signal, write voltage regulator 308 is enabled to apply a write voltage to signal path 323. In response to a logic low memory write signal, write voltage regulator 308 is disabled. Thus, in response to a logic high custom enable signal, a logic low lock signal, a logic high address signal, a logic high write enable signal, a logic high memory write signal, and a logic high fire signal, transistors 332, 334, and 336 are turned on to allow floating-gate transistor 330 to be written to by write voltage regulator 308.

[0050] Figure 4B is a schematic diagram illustrating one example of a circuit 370 for accessing a memory cell storing a lock bit. In one example, the circuit 370 is Figure 3 The circuit 370 is similar to the previously referenced Figure 4ACircuit 300 is described and illustrated except that in circuit 370, memory cell 302 is replaced with memory cell 372 and latch 304 is replaced with latch 374. Memory cell 372 stores a lock bit and latch 374 latches the lock bit in response to a reset signal.

[0051] Memory cell 372 is similar to memory cell 302 described previously. Latch 374 is similar to latch 304 described previously, except that latch 374 does not include a preset signal input. The output (Q) of latch 374 provides a lock signal on lock signal path 340, which is an input to inverter 310 (see also FIG. Figure 4A Inverter 310). Instead of the select signal input to AND gate 312, the nozzle data lock bit signal is input to AND gate 312 via nozzle data lock bit signal path 376. The nozzle data lock bit signal can be used to select memory cell 372. The nozzle data lock bit signal can be based on data received from the host printing device via the data interface. As previously described, similar to Figure 4A 302, the memory cell 372 may be enabled for write or read access.

[0052] Figure 5 An example of a fluid ejection device 500 is illustrated. The fluid ejection device 500 includes a sensing interface 502, a first fluid ejection assembly 504, and a second fluid ejection assembly 506. The first fluid ejection assembly 504 includes a carrier 508 and a plurality of elongated substrates 510, 512, and 514 (e.g., fluid ejection dies, which will be described below with reference to FIG6). The carrier 508 includes electrical wiring 516 that is coupled to an interface (e.g., a sensing interface) of each of the elongated substrates 510, 512, and 514 and to the sensing interface 502. The second fluid ejection assembly 506 includes a carrier 520 and an elongated substrate 522 (e.g., a fluid ejection die). The carrier 520 includes electrical wiring 524 that is coupled to an interface (e.g., a sensing interface) of the elongated substrate 522 and to the sensing interface 502. In one example, the first fluid ejection assembly 504 is a color (eg, cyan, magenta, and yellow) inkjet or fluid ejection print cartridge or pen, and the second fluid ejection assembly 506 is a black inkjet or fluid ejection print cartridge or pen.

[0053] In one example, each of the elongated substrates 510, 512, 514, and 522 includes Figure 1A Integrated circuit 100, Figure 1B Integrated circuit 120, Figure 3 Integrated circuit 200 or Figure 4A and Figure 4BThus, the sensing interface 502 can be electrically coupled to the sensing interface 236 ( Figure 3 ) or sensing pad 324 ( Figure 4A and Figure 4B ). The memory cells of each elongated substrate 510 , 512 , 514 , and 522 may be accessed through the sensing interface 502 and the electrical wiring 516 and 524 .

[0054] In one example, the customization bits of each elongated substrate 510, 512, and 514 of the first fluid ejection assembly 504 vary between each elongated substrate. In one example, each elongated substrate 510, 512, 514, and 522 includes four non-volatile memory cells for storing four customization bits. Thus, the customization bits can define the fluid ejection assembly 504 as one of 4096 individual fluid ejection devices and define the fluid ejection assembly 506 as one of 16 individual fluid ejection devices.

[0055] Figure 6A One example of a fluid jet die 600 is illustrated, and Figure 6B An enlarged view of the end of a fluid jet die 600 is shown. In one example, the fluid jet die 600 includes Figure 1A Integrated circuit 100, Figure 1B Integrated circuit 120, Figure 3 Integrated circuit 200 or Figure 4A and Figure 4B Circuit 300 and / or 370 of FIG. Die 600 includes a first column 602 of contact pads, a second column 604 of contact pads, and a column 606 of fluid actuation devices 608 .

[0056] The second column of contact pads 604 is aligned with and spaced a distance (i.e., along the Y-axis) from the first column of contact pads 602. The column 606 of fluid actuation devices 608 is arranged longitudinally relative to the first column of contact pads 602 and the second column of contact pads 604. The column 606 of fluid actuation devices 608 is also arranged between the first column of contact pads 602 and the second column of contact pads 604. In one example, the fluid actuation device 608 is a nozzle or a fluid pump for ejecting droplets.

[0057] In one example, the first column of contact pads 602 includes six contact pads. The first column of contact pads 602 may include, in order, the following contact pads: a data contact pad 610, a clock contact pad 612, a logic power ground return contact pad 614, a multi-purpose input / output contact (e.g., sense) pad 616, a first high-voltage power supply contact pad 618, and a first high-voltage power supply ground return contact pad 620. Thus, the first column of contact pads 602 includes the data contact pad 610 at the top of the first column 602, the first high-voltage power ground return contact pad 620 at the bottom of the first column 602, and the first high-voltage power supply contact pad 618 directly above the first high-voltage power ground return contact pad 620. Although the contact pads 610, 612, 614, 616, 618, and 620 are illustrated in a particular order, in other examples, the contact pads may be arranged in a different order.

[0058] In one example, the second column of contact pads 604 includes six contact pads. The second column of contact pads 604 may include, in order, the following contact pads: a second high-voltage power ground return contact pad 622, a second high-voltage power supply contact pad 624, a logic reset contact pad 626, a logic power supply contact pad 628, a mode contact pad 630, and an excitation contact pad 632. Thus, the second column of contact pads 604 includes the second high-voltage power ground return contact pad 622 at the top of the second column 604, the second high-voltage power supply contact pad 624 directly below the second high-voltage power ground return contact pad 622, and the excitation contact pad 632 at the bottom of the second column 604. Although the contact pads 622, 624, 626, 628, 630, and 632 are illustrated in a particular order, in other examples, the contact pads may be arranged in a different order.

[0059] The data contact pads 610 can be used to input serial data into the die 600 for selecting a fluid actuation device, a memory bit, a thermal sensor, a configuration mode (e.g., via a configuration register), etc. The data contact pads 610 can also be used to output serial data from the die 600 for reading a memory bit, a configuration mode, status information (e.g., via a status register), etc. The clock contact pads 612 can be used to input a clock signal into the die 600 to shift the serial data on the data contact pads 610 into the die or shift the serial data out of the die to the data contact pads 610. The logic power ground return contact pads 614 provide a ground return path for the logic power (e.g., approximately 0V) supplied to the die 600. In one example, the logic power ground return contact pads 614 are electrically coupled to the semiconductor (e.g., silicon) substrate 640 of the die 600. The multipurpose input / output contact pads 616 can be used for analog sensing and / or digital test modes of the die 600. In one example, a multi-purpose input / output contact (eg, sense) pad 616 may provide Figure 3 The sensing interface 236 or Figure 4A and Figure 4B The sensing pad 324 is provided.

[0060] The first high-voltage power supply contact pad 618 and the second high-voltage power supply contact pad 624 can be used to supply a high voltage (e.g., approximately 32V) to the die 600. The first high-voltage power ground return contact pad 620 and the second high-voltage power ground return contact pad 622 can be used to provide a power ground return (e.g., approximately 0V) for the high-voltage power supply. The high-voltage power ground return contact pads 620 and 622 are not directly electrically connected to the semiconductor substrate 640 of the die 600. The specific contact pad order of having the high-voltage power supply contact pads 618 and 624 and the high-voltage power ground return contact pads 620 and 622 as the innermost contact pads can improve power delivery to the die 600. Having the high-voltage power ground return contact pads 620 and 622 at the bottom of the first column 602 and the top of the second column 604, respectively, can improve manufacturing reliability and improve ink short circuit protection.

[0061] Logic reset contact pad 626 can be used as a logic reset input to control the operating state of die 600. In one example, logic reset contact pad 626 can be electrically coupled to Figure 3 The reset signal path 210 or Figure 4A and Figure 4B6. The logic power supply contact pad 628 can be used to supply logic power (e.g., between about 1.8V and 15V, such as 5.6V) to the die 600. The mode contact pad 630 can be used as a logic input to control access to enable / disable the configuration mode (i.e., functional mode) of the die 600. The fire contact pad 632 can be used as a logic input to latch the loaded data from the data contact pad 610 and enable the fluidic actuation device or memory element of the die 600. In one example, the fire contact pad 632 can be electrically coupled to the Figure 4A and Figure 4B The excitation signal path 348.

[0062] Die 600 includes an elongated substrate 640 having a length 642 (along the Y-axis), a thickness 644 (along the Z-axis), and a width 646 (along the X-axis). In one example, length 642 is at least twenty times greater than width 646. Width 646 can be 1 mm or less and thickness 644 can be less than 500 microns. Fluid actuation devices 608 (e.g., fluid actuation logic) and contact pads 610 to 632 are provided on elongated substrate 640 and arranged along length 642 of the elongated substrate. Fluid actuation devices 608 have a stripe length 652 that is less than length 642 of elongated substrate 640. In one example, stripe length 652 is at least 1.2 cm. Contact pads 610 to 632 can be electrically coupled to fluid actuation logic. A first column of contact pads 602 can be arranged near a first longitudinal end 648 of elongated substrate 640. The second column of contact pads 604 may be arranged near a second longitudinal end 650 of the elongated substrate 640 opposite the first longitudinal end 648 .

[0063] Figure 7 is a block diagram illustrating one example of a fluid ejection system 700. Fluid ejection system 700 includes a fluid ejection assembly, such as a printhead assembly 702, and a fluid supply assembly, such as an ink supply assembly 710. In the illustrated example, fluid ejection system 700 also includes a service station assembly 704, a carriage assembly 716, a print media transport assembly 718, and an electronic controller 720. Although the following description provides examples of systems and assemblies for fluid processing related to ink, the disclosed systems and assemblies are also applicable to processing fluids other than ink.

[0064] Printhead assembly 702 includes the previously referenced Figure 6A and Figure 6BAt least one printhead or fluid ejection die 600 is described and illustrated as ejecting ink droplets or liquid droplets through a plurality of orifices or nozzles 608. In one example, the droplets are directed toward a medium, such as a print medium 724, to be printed onto the print medium 724. In one example, the print medium 724 includes any type of suitable sheet material, such as paper, card stock, transparency film, Mylar, fabric, etc. In another example, the print medium 724 includes a medium for three-dimensional (3D) printing, such as a powder bed, or a medium for bioprinting and / or drug discovery testing, such as a reservoir or container. In one example, the nozzles 608 are arranged in at least one column or array such that properly sequenced ejection of ink from the nozzles 608 causes characters, symbols, and / or other graphics or images to be printed on the print medium 724 as the printhead assembly 702 and the print medium 724 move relative to each other.

[0065] Ink supply assembly 710 supplies ink to printhead assembly 702 and includes a reservoir 712 for storing ink. Thus, in one example, ink flows from reservoir 712 to printhead assembly 702. In one example, printhead assembly 702 and ink supply assembly 710 are housed together in an inkjet or fluid jet print cartridge or pen. In another example, ink supply assembly 710 is separate from printhead assembly 702 and supplies ink to printhead assembly 702 via an interface connection 713 (e.g., a supply tube and / or a valve).

[0066] Carriage assembly 716 positions printhead assembly 702 relative to print media transport assembly 718, and print media transport assembly 718 positions print media 724 relative to printhead assembly 702. Thus, print zone 726 is defined adjacent to nozzles 608 in the area between printhead assembly 702 and print media 724. In one example, printhead assembly 702 is a scanning printhead assembly, such that carriage assembly 716 moves printhead assembly 702 relative to print media transport assembly 718. In another example, printhead assembly 702 is a non-scanning printhead assembly, such that carriage assembly 716 secures printhead assembly 702 at a specified position relative to print media transport assembly 718.

[0067] Service station assembly 704 provides for ejecting, wiping, capping, and / or priming of printhead assembly 702 to maintain the functionality of printhead assembly 702, and more specifically, nozzles 608. For example, service station assembly 704 may include a rubber blade or wiper that periodically passes over printhead assembly 702 to wipe and clean excess ink from nozzles 608. Additionally, service station assembly 704 may include a cap that covers printhead assembly 702 to protect nozzles 608 from drying out during periods of non-use. Additionally, service station assembly 704 may include an ink reservoir into which printhead assembly 702 ejects ink during spitting to ensure that reservoir 712 maintains an appropriate level of pressure and fluidity and that nozzles 608 do not clog or leak. The functionality of service station assembly 704 may include relative movement between service station assembly 704 and printhead assembly 702.

[0068] Electronic controller 720 communicates with printhead assembly 702 via communication path 703, with service station assembly 704 via communication path 705, with carriage assembly 716 via communication path 717, and with print media transport assembly 718 via communication path 719. In one example, when printhead assembly 702 is installed in carriage assembly 716, electronic controller 720 and printhead assembly 702 can communicate via carriage assembly 716 via communication path 701. Electronic controller 720 can also communicate with ink supply assembly 710 so that, in one embodiment, a new (or used) ink supply can be detected.

[0069] The electronic controller 720 receives data 728 from a host system, such as a computer, and may include memory for temporarily storing the data 728. The data 728 may be sent to the fluid ejection system 700 along an electronic, infrared, optical, or other information transfer path. The data 728 represents, for example, a document and / or file to be printed. Thus, the data 728 forms a print job for the fluid ejection system 700 and includes at least one print job command and / or command parameters.

[0070] In one example, electronic controller 720 provides control of printhead assembly 702, including timing control for ejecting ink droplets from nozzles 608. Thus, electronic controller 720 defines the pattern of ejected ink droplets that form characters, symbols, and / or other graphics or images on print medium 724. The timing control, and therefore the pattern of ejected ink droplets, is determined by print job commands and / or command parameters. In one example, logic and driver circuitry forming part of electronic controller 720 is located on printhead assembly 702. In another example, logic and driver circuitry forming part of electronic controller 720 is located external to printhead assembly 702.

[0071] Figures 8A to 8C is a flow chart illustrating an example of a method 800 for operating an integrated circuit for driving a plurality of fluid actuation devices. In one example, the method 800 may be performed by Figure 1A Integrated circuit 100, Figure 1B Integrated circuit 120, Figure 3 Integrated circuit 200, Figure 4A The circuit 300 and / or Figure 4B The circuit 370 is implemented as Figure 8A As shown, at 802, method 800 includes reading a plurality of custom bits stored in a corresponding plurality of first non-volatile memory cells. At 804, method 800 includes receiving an address from a nozzle data stream. At 806, method 800 includes summing the custom bits and the address to generate a modified address.

[0072] In one example, the plurality of custom bits includes four custom bits and the address includes four bits. In this case, summing the custom bits and the address may include summing the custom bits and the address to generate a modified address including four bits, wherein the most significant bit of the sum is discarded. Figure 8B As shown, at 808, method 800 may further include activating a fluid actuation device based on the modified address. Figure 8C As illustrated, at 810, the method 800 can further include accessing a second non-volatile memory cell of the plurality of second non-volatile memory cells based on the modified address.

[0073] Although specific examples have been illustrated and described herein, various alternative and / or equivalent embodiments may be substituted for the specific examples shown and described without departing from the scope of the present disclosure. This application is intended to cover any modifications or variations of the specific examples discussed herein. Therefore, the present disclosure is intended to be limited only by the claims and their equivalents.

Claims

1. An integrated circuit for a fluid ejection die including a plurality of fluid actuation devices, the integrated circuit comprising: a plurality of first nonvolatile memory cells, each first nonvolatile memory cell storing a custom bit; a second non-volatile memory unit; as well as control logic for configuring operation of the fluid actuation device based on the customization bits, wherein whether at least one of the customization bits stored in the plurality of first non-volatile memory cells is allowed to be modified is determined based on information stored in the second non-volatile memory cell, wherein the operation is for modifying an address to the fluid actuation device based on the custom bit; wherein the control logic provides access to one of the plurality of second non-volatile memory cells based on the modified address; and The operation includes at least one of: preventing or allowing access to further memory cells of the integrated circuit, inverting at least part of a data stream received by the integrated circuit, or modifying a bit stored in a configuration register of the integrated circuit.

2. The integrated circuit of claim 1, wherein: The control logic includes an address modifier electrically coupled to an address signal path, electrically coupled to each of the plurality of first nonvolatile memory cells through a respective signal path, and electrically coupled to the fluid actuation device through a modified address signal path.

3. The integrated circuit of claim 2, wherein: The address modifier receives the address via the address signal path and receives the stored customization bits from each first non-volatile memory cell.

4. An integrated circuit as claimed in claim 2 or 3, wherein: The address modifier modifies the address based on the custom bits and provides the modified address on the modified address signal path.

5. The integrated circuit according to any one of claims 1 to 3, wherein: The address is part of the nozzle data stream input to the integrated circuit.

6. The integrated circuit according to any one of claims 1 to 3, wherein: The fluid ejection die is used to fire a fluid actuation device based on a modified address received from the control logic.

7. The integrated circuit according to any one of claims 1 to 3, wherein: The plurality of first nonvolatile memory cells includes four memory cells, and The customization bits define the integrated circuit as one of 16 separate integrated circuits.

8. The integrated circuit of any one of claims 1 to 3, for a plurality of fluid ejection dies, wherein the control logic is used to configure the operation of each fluid ejection die based on the customization bits, and wherein the customization bits vary for each of the fluid ejection dies.

9. The integrated circuit of claim 8, wherein for each fluid ejection die, the operation is to modify an address input to the fluid ejection die based on the custom bits.

10. The integrated circuit of claim 9, wherein for each fluid ejection die, the control logic is to activate the fluid actuation device based on the modified address.

11. The integrated circuit of claim 9 or 10, wherein for each fluid ejection die, the control logic is to access the second non-volatile memory unit based on the modified address.

12. A fluid jet die comprising: a plurality of fluid-actuated devices; a plurality of first nonvolatile memory cells, each first nonvolatile memory cell storing a custom bit; a second non-volatile memory unit; as well as control logic for configuring operation of the fluid ejection die based on the customization bits, wherein whether at least one of the customization bits stored in the plurality of first non-volatile memory cells is allowed to be modified is determined based on information stored in the second non-volatile memory cell, wherein, when the at least one custom bit is allowed to be modified, the control logic provides access to one of the plurality of second non-volatile memory cells based on the modified address; and The operation includes at least one of: preventing or allowing access to further memory cells of the integrated circuit, inverting at least part of a data stream received by the integrated circuit, or modifying a bit stored in a configuration register of the integrated circuit.

13. A fluid ejection device comprising: An integrated circuit as claimed in any one of claims 1 to 11; as well as One or more fluid-jet dies, each fluid-jet die comprising a plurality of fluid actuation devices.

14. A fluid ejection device comprising: carrier; as well as a plurality of fluid jet dies, each fluid jet die comprising the fluid jet die of claim 12, The plurality of fluid jet dies are arranged parallel to each other on the carrier, each fluid jet die having a length, a thickness, and a width, the length being at least twenty times the width.

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