Circuit for measuring the voltage of a diode for sensing temperature

Abstract

The present application relates to the field of integrated circuit technologies, and discloses a circuit for measuring the voltage of a diode for sensing temperature. The cathode of the diode is coupled to a voltage source, and the anode is coupled to a charge pump power supply through a bias current source. The circuit includes: an operational amplifier, a first input terminal of which is coupled to the anode of the diode through a unit resistor, and a second input terminal of which is coupled to the cathode of the diode; a first PMOS transistor, a gate of the first PMOS transistor is coupled to an output terminal of the operational amplifier, and a source of the first PMOS transistor is coupled between the first input terminal of the operational amplifier and the unit resistor coupled thereto; a first NMOS transistor, a drain of the first PMOS transistor is coupled to a drain and a gate of the first NMOS transistor, and the drain of the first NMOS transistor is coupled to a ground terminal; a compensation unit. The present application converts the voltage difference across the diode from the high voltage side to the low voltage side, with higher precision and lower power consumption.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a circuit for measuring the voltage of a diode for sensing temperature. Background Art

[0002] As is well known, the junction voltage of a diode that varies with temperature can be utilized to sense temperature, and it is excited with a fixed or a current having a certain temperature coefficient, as Figure 1 shown. It can be seen that the junction voltage Vd has a linear relationship with the absolute temperature T, where the relationship between the junction voltage Vd and the absolute temperature T is as Figure 2 shown. If the junction voltage Vd is quantized by an ADC, Vd can be used to estimate the temperature T.

[0003] In some application scenarios, the diode can only be used when its cathode is connected to the power supply, for example, when restricted by semiconductor manufacturing processes. In these cases, a voltage VCP higher than the power supply VCC is usually generated by a charge pump to supply current to the temperature-sensing diode, as Figure 3 shown.

[0004] The temperature information is represented by the voltage difference across the diode between VCC and VCC + Vd, which is referred to as "high side" or "high voltage side" in the literature. In most cases, it needs to be shifted down to a lower voltage Vd, referred to as "low side" or "low voltage side", for further signal processing, such as ADC sampling. Figure 4 The schematic diagram of converting the voltage difference across the diode from the high side to the low side using a level shifter and a voltage-to-current converter is shown in

[0005] However, the signal processing converters in this solution introduce errors, limiting the overall accuracy of temperature sensing. Summary of the Invention

[0006] The purpose of this application is to provide a circuit for measuring the voltage of a diode for sensing temperature, which can convert the voltage difference across the diode from the high side to the low side with higher accuracy and lower power consumption.

[0007] This application discloses a circuit for measuring the voltage of a diode for sensing temperature, wherein the cathode of the diode is coupled to a voltage source, and the anode of the diode is coupled to a charge pump power supply through a bias current source. The circuit includes:

[0008] An operational amplifier, the first input terminal of the operational amplifier is coupled to the anode of the diode through a unit resistor, and the second input terminal of the operational amplifier is coupled to the cathode of the diode;

[0009] A first PMOS transistor, the gate of the first PMOS transistor being coupled to the output terminal of the operational amplifier, and the source of the first PMOS transistor being coupled between the first input terminal of the operational amplifier and the unit resistor coupled thereto;

[0010] A first NMOS transistor, the drain of the first PMOS transistor being coupled to the drain and gate of the first NMOS transistor, and the drain of the first NMOS transistor being coupled to the ground terminal;

[0011] A compensation unit, the compensation unit including a second PMOS transistor, a third PMOS transistor, and a second NMOS transistor, the sources of the second PMOS transistor and the third PMOS transistor both being coupled to the power supply, the drain of the second PMOS transistor being coupled to the anode of the diode and the end of the unit resistor coupled to the first input terminal of the operational amplifier away from the first input terminal, the gate of the second PMOS transistor and the gates and drains of the third PMOS transistor being connected and coupled to the drain of the second NMOS transistor, the gate of the second NMOS transistor being coupled to the gate and drain of the first NMOS transistor, and the source of the second NMOS transistor being coupled to the ground terminal.

[0012] In a preferred example, the voltage of the charge pump power supply is higher than the voltage of the voltage source.

[0013] In a preferred example, the voltage of the anode of the diode is the voltage of the voltage source plus an induced voltage, and the induced voltage has a linear relationship with temperature.

[0014] In a preferred example, a first level shifter is coupled between the unit resistor and the anode of the diode, which includes a third NMOS transistor and a current source, the source of the third NMOS transistor being coupled to the voltage source, the gate being coupled to the anode of the diode, and the drain being coupled to the unit resistor and coupled to the ground terminal through the current source; a second level shifter is coupled between the second input terminal of the operational amplifier and the cathode of the diode, which includes a fourth NMOS transistor and a current source, the source of the fourth NMOS transistor being coupled to the voltage source, the gate being coupled to the cathode of the diode, and the drain being coupled to the second input terminal of the operational amplifier and coupled to the ground terminal through the current source; wherein, the sources of the second PMOS transistor and the third PMOS transistor are both coupled to the voltage source.

[0015] In a preferred example, the first input terminal and the second input terminal of the operational amplifier are each coupled to the cathode and anode of a diode through a unit resistor. A current source is coupled between the first input terminal and the unit resistor coupled thereto to the ground terminal. Wherein, the second PMOS transistor of the compensation unit provides a sum current of the ratio of the current source to the induced voltage and the unit resistor to the first input terminal of the operational amplifier. Wherein, the source electrodes of the second PMOS transistor and the third PMOS transistor are both coupled to the charge pump power supply.

[0016] In a preferred example, the first input terminal and the second input terminal of the operational amplifier are each coupled to the cathode and anode of a diode through a unit resistor. A current source is coupled between the first input terminal and the unit resistor coupled thereto to the ground terminal, and a current source is coupled between the second input terminal and the unit resistor coupled thereto to the ground terminal. Wherein, the second PMOS transistor of the compensation unit provides a current of the ratio of the induced voltage to the unit resistor to the first input terminal of the operational amplifier. Wherein, the source electrodes of the second PMOS transistor and the third PMOS transistor are both coupled to the charge pump power supply.

[0017] In a preferred example, further included is:

[0018] A mirror circuit, the mirror circuit includes a fifth NMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor. The gate of the fifth NMOS transistor is coupled to the gate and drain of the first NMOS transistor. The source of the fifth NMOS transistor is coupled to the ground terminal. The drain of the fifth NMOS transistor is coupled to the gate and drain of the fourth PMOS transistor and the gate of the fifth PMOS transistor. The source electrodes of the fourth PMOS transistor and the fifth PMOS transistor are coupled to the voltage source. The drain of the fifth PMOS transistor is coupled to a unit resistor.

[0019] In a preferred example, the mirror ratio between the fourth PMOS transistor and the fifth PMOS transistor is 1:1.

[0020] In a preferred example, the operational amplifier operates in a voltage domain between the voltage of the ground terminal and the voltage source.

[0021] In the embodiments of the present application, a single operational amplifier loop is used to convert a signal from the high voltage side to the low voltage side, which is more accurate than a multi-operational amplifier solution. Moreover, by adjusting the current source Ios connected to the input terminal of the operational amplifier, the input common-mode voltage of the operational amplifier can be well controlled, the circuit design is easier, and the performance is better. In addition, there may be no open-loop level converter in the present application, so the accuracy is higher and the power consumption is lower.

[0022] A large number of technical features are described in the specification of this application, which are distributed in various technical solutions. If all possible combinations of technical features (i.e., technical solutions) of this application are to be listed, the specification will become overly lengthy. To avoid this problem, each technical feature disclosed in the above-mentioned invention content of this application, each technical feature disclosed in the following various embodiments and examples, and each technical feature disclosed in the drawings can be freely combined with each other to form various new technical solutions (all of these technical solutions should be regarded as having been described in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, features A+B+C are disclosed, and in another example, features A+B+D+E are disclosed, and features C and D are equivalent technical means that perform the same function. Technically, only one of them can be used, and it is impossible to use both at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be regarded as having been described because it is technically infeasible, while the solution of A+B+C+E should be regarded as having been described. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic diagram of a diode sensing temperature in the prior art.

[0024] Figure 2 is the relationship between the diode junction voltage and the junction temperature in the prior art.

[0025] Figure 3 is a schematic diagram of an application scenario where the cathode of a diode is connected to a power supply in the prior art.

[0026] Figure 4 is a schematic diagram of using a level converter to convert the voltage difference across a diode from the high side to the low side in the prior art.

[0027] Figure 5 is a schematic diagram of converting the voltage difference across a diode from the high side to the low side in an embodiment of this application.

[0028] Figure 6 is a schematic diagram of converting the voltage difference across a diode from the high side to the low side in another embodiment of this application.

[0029] Figure 7 is a schematic diagram of converting the voltage difference across a diode from the high side to the low side in yet another embodiment of this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] In the following description, many technical details are presented for the better understanding of this application by the reader. However, those of ordinary skill in the art can understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can still be implemented.

[0031] To make the objectives, technical solutions, and advantages of this application clearer, the following will further describe the implementation manners of this application in detail with reference to the accompanying drawings.

[0032] Embodiment 1

[0033] An embodiment of this application discloses a circuit for measuring the voltage of a diode for sensing temperature, and its structure is as Figure 5 shown. The cathode of the diode 101 is coupled to the voltage source VCC, and the anode of the diode 101 is coupled to the charge pump power supply VCP through the bias current source IB. In one embodiment, the voltage VCP of the charge pump power supply is higher than the voltage VCC of the voltage source. The voltage of the anode of the diode 101 is the voltage of the voltage source plus the induced voltage, that is, the voltage of the anode of the diode 101 is VCC + Vd, where the induced voltage Vd has a linear relationship with the temperature. The measurement circuit includes an operational amplifier 102, a first PMOS transistor P1, a first NMOS transistor N1, and a compensation unit 103.

[0034] The first input terminal of the operational amplifier 102 is coupled to the cathode of the diode 101 through a unit resistor R, and the second input terminal is coupled to the anode of the diode 101. For example, in this embodiment, the positive input terminal of the operational amplifier 102 is coupled to the cathode of the diode 101, and the negative input terminal is coupled to the anode of the diode 101 as an example for illustration. A first level converter 104 is coupled between the unit resistor R and the anode of the diode 101, and a second level converter 105 is coupled between the positive input terminal of the operational amplifier 101 and the cathode of the diode 101. The first level converter 104 includes a third NMOS transistor N3 and a current source IOS. The source of the third NMOS transistor N3 is coupled to the voltage source VCC, the gate of the third NMOS transistor N3 is coupled to the anode of the diode 101, and the drain of the third NMOS transistor N3 is coupled to the unit resistor R and is coupled to the ground terminal GND through the current source IOS. The second level converter 105 includes a fourth NMOS transistor N5 and a current source IOS. The source of the fourth NMOS transistor N4 is coupled to the voltage source VCC, the gate of the fourth NMOS transistor N4 is coupled to the cathode of the diode 101, and the drain of the fourth NMOS transistor N4 is coupled to the positive input terminal of the operational amplifier 101 and is coupled to the ground terminal GND through the current source IOS. In this embodiment, the ground terminal is usually the reference ground terminal.

[0035] The gate of the first PMOS transistor P1 is coupled to the output terminal of the operational amplifier 102. The source of the first PMOS transistor P1 is coupled between the positive input terminal of the operational amplifier 102 and the unit resistor R coupled thereto. The drain of the first PMOS transistor P1 is coupled to the drain and gate of the first NMOS transistor N1, and the drain of the first NMOS transistor N1 is coupled to the ground terminal.

[0036] In one embodiment, the compensation unit 103 includes a second PMOS transistor P2, a third PMOS transistor P3, and a second NMOS transistor N2. The sources of the second PMOS transistor P2 and the third PMOS transistor P3 are both coupled to the voltage source VCC. The drain of the second PMOS transistor P2 is coupled to the anode of the diode 102 and the end of the unit resistor R coupled to the positive input terminal of the operational amplifier 102 that is far from the positive input terminal. The gate of the second PMOS transistor P2, the gates and drains of the third PMOS transistor P3 are connected and coupled to the drain of the second NMOS transistor N2. The gate of the second NMOS transistor N2 is coupled to the gate and drain of the first NMOS transistor N2, and the source of the second NMOS transistor N2 is coupled to the ground terminal.

[0037] In this embodiment, the anode of the diode 101 outputs the voltage VCC + Vd - Vgs3 to the branch where the negative input terminal of the operational amplifier 102 is located (i.e., to one end of the unit R resistor) through the source of the third NMOS transistor N3, and the cathode of the diode 101 outputs the voltage VCC - Vgs4 to the positive input terminal of the operational amplifier 102 through the source of the fourth NMOS transistor N4. When the circuit is operating normally, Vgs3 = Vgs4. In order to maintain Vgs3 = Vgs4 within the full temperature range, the compensation unit 103 needs to provide a current Vd / R to the branch where the negative input terminal of the operational amplifier 102 is located to compensate for the temperature coefficient of the channel current of the third NMOS transistor N3. This compensation current is equal to the current flowing through the resistor R that varies with temperature, that is, the current flowing through the source of the first PMOS transistor P1. Since the current received by the source of the first PMOS transistor P1 is Vd / R and the drain outputs a current of Vd / R, through the mirroring of the second NMOS transistor N2, the third PMOS transistor P3, and the second PMOS transistor P2, the current Vd / R output by the drain of the second PMOS transistor P2 is mirrored to the branch where the negative input terminal of the operational amplifier 102 is located.

[0038] It should be understood that the drain current of the third NMOS transistor N3 is Vd / R, and converting this current into a voltage gives the induced voltage Vd to be measured. Further, the measurement circuit further includes: a mirror circuit 104, and the mirror circuit 104 includes a fifth NMOS transistor N5, a fourth PMOS transistor P4, and a fifth PMOS transistor P5 (not shown in the figure). The gate of the fifth NMOS transistor N5 is coupled to the gate and drain of the first NMOS transistor N1. The source of the fifth NMOS transistor N5 is coupled to the ground terminal. The drain of the fifth NMOS transistor N5 is coupled to the gates and drains of the fourth PMOS transistor P4 and the fifth PMOS transistor P5. The sources of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are coupled to a voltage source. The drain of the fifth PMOS transistor P5 is coupled to a unit resistor R, and the voltage across the unit resistor R is the induced voltage Vd to be measured. In one embodiment, the mirror ratio between the fourth PMOS transistor P4 and the fifth PMOS transistor P5 is 1:1. The drain voltage of the fifth PMOS transistor P5 is the induced voltage Vd to be measured.

[0039] Relative to Figure 4 In the solution shown, the present application uses a single operational amplifier loop to convert the signal from the high voltage side to the low voltage side, which is more accurate than the solution with multiple operational amplifiers. However, connecting the positive input terminal and the negative input terminal of the operational amplifier 102 in the present application to the level shifters composed of the third NMOS transistor N3 and the fourth NMOS transistor N4 respectively will introduce errors and limit the overall accuracy of temperature sensing.

[0040] Embodiment 2

[0041] Another embodiment of the present application discloses a circuit for measuring the voltage of a diode for sensing temperature, and its structure is as Figure 6 shown. The operational amplifier 202, the first PMOS transistor P1, the first NMOS transistor N1, and the compensation unit 203 in this embodiment are respectively the same as the Figure 5 operational amplifier 101, the first PMOS transistor P1, the first NMOS transistor N1, and the compensation unit 103 shown in, and will not be elaborated here.

[0042] As Figure 6As shown, the positive input terminal of the operational amplifier 202 is coupled to the cathode of the diode 201 through a unit resistor R, the negative input terminal of the operational amplifier 202 is coupled to the anode of the diode 201 through a unit resistor R, and the positive input terminal and the unit resistor coupled thereto are coupled to the ground terminal GND through a current source IOS. In addition, the compensation unit 203 includes a second PMOS transistor P2, a third PMOS transistor P3, and a second NMOS transistor N2. The source electrodes of the second PMOS transistor P2 and the third PMOS transistor P3 are both coupled to the charge pump power supply VCP. The drain of the second PMOS transistor P2 is coupled to the anode of the diode 102 and the end of the unit resistor R coupled to the positive input terminal of the operational amplifier 102 that is far from the positive input terminal. The gates of the second PMOS transistor P2, the third PMOS transistor P3, and the drain are connected and coupled to the drain of the second NMOS transistor N2. The gate of the second NMOS transistor N2 is coupled to the gate and drain of the first NMOS transistor N2. The source of the second NMOS transistor N2 is coupled to the ground terminal.

[0043] In this embodiment, the second PMOS transistor P2 of the compensation unit 203 provides a sum current (i.e., IOS + Vd / R) of the ratio of the current source to the induced voltage and the unit resistor to the negative input terminal of the operational amplifier 202. Specifically, the anode of the diode 201 is connected to the current source IB, the current flowing through the diode 201 is IB, and the current provided by the anode of the diode 201 to the branch where the negative input terminal of the operational amplifier 202 is located is 0. The voltage at the positive input terminal of the operational amplifier 202 is VCC - R*IOS. In order to make the current flowing through the diode 201 equal to IB within the full temperature range, the compensation unit 203 needs to provide the current IOS + Vd / R to the branch where the negative input terminal of the operational amplifier 202 is located. Since the current received by the source of the first PMOS transistor P1 is IOS + Vd / R and the drain outputs a current of IOS + Vd / R, through the mirroring of the second NMOS transistor N2, the third PMOS transistor P3, and the second PMOS transistor P2, the drain output current IOS + Vd / R of the second PMOS transistor P2 is mirrored to the branch where the negative input terminal of the operational amplifier 202 is located.

[0044] Relative to Figure 5 The solution shown, this application uses a single operational amplifier loop to convert the signal from the high voltage side to the low voltage side, which is more accurate than the multi-operational amplifier solution. And, there is no open-loop level converter in this application, so the accuracy is higher and the power consumption is lower. However, the final output current of this application is IOS + Vd / R, making the measured voltage related to both the induced voltage Vd and the current IOS.

[0045] Embodiment Three

[0046] Another embodiment of the present application discloses a circuit for measuring the voltage of a diode for sensing temperature, and its structure is as Figure 7 shown. The operational amplifier 302, the first PMOS transistor P1, the first NMOS transistor N1, and the compensation unit 303 in this embodiment are respectively the same as Figure 6 the operational amplifier 201, the first PMOS transistor P1, the first NMOS transistor N1, and the compensation unit 203 shown in

[0047] As Figure 7 shown, the positive input terminal of the operational amplifier 302 is coupled to the cathode of the diode 301 through a unit resistor R, and the negative input terminal of the operational amplifier 302 is coupled to the anode of the diode 301 through a unit resistor R. The positive input terminal of the operational amplifier 302 and the unit resistor R coupled thereto are coupled to the ground terminal through a current source Ios, and the negative input terminal of the operational amplifier 302 and the unit resistor R coupled thereto are coupled to the ground terminal through a current source Ios.

[0048] In this embodiment, the anode of the diode 301 is connected to the current source IB + IOS, the current flowing through the diode 301 is IB, and the anode of the diode 301 outputs a current IOS to the branch where the negative input terminal of the operational amplifier 302 is located. The voltage at the positive input terminal of the operational amplifier 302 is VCC - R * IOS. In order to make the current flowing through the diode 201 equal to IB + IOS within the full temperature range, the compensation unit 303 needs to provide a current Vd / R to the branch where the negative input terminal of the operational amplifier 302 is located. Since the current received by the source electrode of the first PMOS transistor P1 is Vd / R and the drain electrode outputs a current Vd / R, through the mirroring of the second NMOS transistor N2, the third PMOS transistor P3, and the second PMOS transistor P2, the drain electrode of the second PMOS transistor P2 outputs a current Vd / R and mirrors it to the branch where the negative input terminal of the operational amplifier 302 is located.

[0049] Compared with Figure 4 、 Figure 5 and Figure 6 the schemes shown, the present application uses a single operational amplifier loop to convert the signal from the high-voltage side to the low-voltage side, which is more accurate than the solution with multiple operational amplifiers. Moreover, there is no open-loop level converter in the present application, so the accuracy is higher and the power consumption is lower. In addition, the final output current of the present application is Vd / R, which is only related to the sensed voltage and is convenient for measurement.

[0050] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one" does not exclude the existence of additional identical elements in the process, method, article or device comprising said element. In the application documents of this patent, if it is mentioned that a certain act is performed according to a certain element, it means that the act is performed at least according to that element, including two cases: the act is performed only according to that element, and the act is performed according to that element and other elements. Expressions such as multiple, many times, various, etc. include 2, 2 times, 2 kinds, and more than 2, more than 2 times, more than 2 kinds.

[0051] The term "coupled to" and its derivatives may be used herein. "Coupling" may mean that two or more elements are in direct physical or electrical contact. However, "coupling" may also mean that two or more elements are in contact with each other indirectly, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements referred to as being coupled to each other.

[0052] This specification includes combinations of various embodiments described herein. Separate references to embodiments (such as "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, unless indicated as being mutually exclusive or clearly understood by those skilled in the art as being mutually exclusive, these embodiments are not mutually exclusive. It should be noted that the word "or" is used in a non-exclusive sense in this specification unless the context clearly indicates otherwise or requires otherwise.

[0053] All documents mentioned in this specification are considered to be integrally included in the disclosure of this application so that they can be used as a basis for modification if necessary. In addition, it should be understood that the above are only preferred embodiments of this specification and are not used to limit the protection scope of this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of one or more embodiments of this specification shall be included within the protection scope of one or more embodiments of this specification.

Claims

1. A circuit for measuring the voltage of a diode for sensing temperature, characterized in that, the cathode of the diode is coupled to a voltage source, the anode of the diode is coupled to a charge pump power supply through a bias current source, and the circuit includes: an operational amplifier, a first input terminal of the operational amplifier is coupled to the anode of the diode through a unit resistor, and a second input terminal of the operational amplifier is coupled to the cathode of the diode; a first PMOS transistor, a gate of the first PMOS transistor is coupled to an output terminal of the operational amplifier, and a source of the first PMOS transistor is coupled between the first input terminal of the operational amplifier and the unit resistor coupled thereto; a first NMOS transistor, a drain of the first PMOS transistor is coupled to a drain and a gate of the first NMOS transistor, and a drain of the first NMOS transistor is coupled to a ground terminal; a compensation unit, the compensation unit includes a second PMOS transistor, a third PMOS transistor and a second NMOS transistor, a source of the second PMOS transistor and a source of the third PMOS transistor are both coupled to a power supply, a drain of the second PMOS transistor is coupled to the anode of the diode and an end of the unit resistor coupled to the first input terminal of the operational amplifier away from the first input terminal, a gate of the second PMOS transistor and a gate and a drain of the third PMOS transistor are connected and coupled to a drain of the second NMOS transistor, a gate of the second NMOS transistor is coupled to a gate and a drain of the first NMOS transistor, and a source of the second NMOS transistor is coupled to the ground terminal.

2. The circuit for measuring the voltage of a diode for sensing temperature according to claim 1, characterized in that, the voltage of the charge pump power supply is higher than the voltage of the voltage source.

3. The circuit for measuring the voltage of a diode for sensing temperature according to claim 1, characterized in that, the voltage of the anode of the diode is the voltage of the voltage source plus an induced voltage, and the induced voltage has a linear relationship with temperature.

4. The circuit for measuring the voltage of a diode for sensing temperature according to claim 1, characterized in that, a first level shifter is coupled between the unit resistor and the anode of the diode, and it includes a third NMOS transistor and a current source, a source of the third NMOS transistor is coupled to the voltage source, a gate is coupled to the anode of the diode, a drain is coupled to the unit resistor and is coupled to the ground terminal through the current source; a second level shifter is coupled between the second input terminal of the operational amplifier and the cathode of the diode, and it includes a fourth NMOS transistor and a current source, a source of the fourth NMOS transistor is coupled to the voltage source, a gate is coupled to the cathode of the diode, a drain is coupled to the second input terminal of the operational amplifier and is coupled to the ground terminal through the current source; wherein, the power supply to which the source of the second PMOS transistor and the source of the third PMOS transistor are coupled is the voltage source.

5. The circuit for measuring the voltage of a diode for sensing temperature according to claim 1, characterized in that, the first input terminal and the second input terminal of the operational amplifier are each coupled to the cathode and anode of the diode through a unit resistor, and a current source is coupled between the second input terminal and the unit resistor coupled thereto to the ground terminal, wherein the second PMOS transistor of the compensation unit provides a sum current of the ratio of the current source to the sensed voltage and the unit resistor to the first input terminal of the operational amplifier, and the power supply coupled to the sources of the second PMOS transistor and the third PMOS transistor is the charge pump power supply.

6. The circuit for measuring the voltage of a diode for sensing temperature according to claim 1, characterized in that, the first input terminal and the second input terminal of the operational amplifier are each coupled to the cathode and anode of the diode through a unit resistor, a current source is coupled between the first input terminal and the unit resistor coupled thereto to the ground terminal, and a current source is coupled between the second input terminal and the unit resistor coupled thereto to the ground terminal, wherein the second PMOS transistor of the compensation unit provides a current of the ratio of the sensed voltage to the unit resistor to the first input terminal of the operational amplifier, and the power supply coupled to the sources of the second PMOS transistor and the third PMOS transistor is the charge pump power supply.

7. The circuit for measuring the voltage of a diode for sensing temperature according to claim 1, characterized in that, further comprising: a mirror circuit, the mirror circuit includes a fifth NMOS transistor, a fourth PMOS transistor and a fifth PMOS transistor, the gate of the fifth NMOS transistor is coupled to the gate and drain of the first NMOS transistor, the source of the fifth NMOS transistor is coupled to the ground terminal, the drain of the fifth NMOS transistor is coupled to the gate and drain of the fourth PMOS transistor and the gate of the fifth PMOS transistor, the sources of the fourth PMOS transistor and the fifth PMOS transistor are coupled to the voltage source, and the drain of the fifth PMOS transistor is coupled to a unit resistor.

8. The circuit for measuring the voltage of a diode for sensing temperature according to claim 7, characterized in that, the mirror ratio between the fourth PMOS transistor and the fifth PMOS transistor is 1:

1.

9. The circuit for measuring the voltage of a diode for sensing temperature according to claim 1, characterized in that, the operational amplifier operates in a voltage domain between the voltage of the ground terminal and the voltage source.

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