Pixel array substrate and electrowetting display panel

Abstract

The application discloses a pixel array substrate and an electrowetting display panel. The pixel array substrate comprises a substrate and a plurality of pixel units. The pixel units are arranged on the substrate and each comprises at least one active element, a pixel electrode and at least one storage capacitor. The pixel electrode is electrically connected to the at least one active element and has a plurality of holes. The at least one storage capacitor is electrically connected to the pixel electrode and the at least one active element. The at least one storage capacitor completely overlaps a part of the plurality of holes of the pixel electrode.

Description

Technical Field

[0001] This invention relates to a display technology, and more particularly to a pixel array substrate and an electrowetting display panel. Background Technology

[0002] In recent years, e-paper and e-books have been booming, and display panels with lighter, thinner, and more flexible properties will become the main trend for future development. Electrowetting display panels are a type of display panel that can be applied to e-books and e-paper. A typical electrowetting display panel includes an upper electrode, a lower electrode, and a hydrophilic layer and an ink layer sandwiched between the two electrodes. When no voltage is applied, the ink layer covers the pixel units. This allows incident light to be absorbed by the ink layer, making the pixel units appear dark.

[0003] When a pixel is to be illuminated, a voltage is applied to the ink layer, causing it to shrink and reveal a reflective layer beneath the ink layer within the display unit. This allows incident light to be reflected by the reflective layer, resulting in the illuminated state. However, in an active-matrix drive architecture, the arrangement of related electronic components sacrifices the aperture ratio of the display unit in the illuminated state, which is easily visible to the human eye. Furthermore, the stacked architecture of multiple electrowetting display panels, proposed to meet color display requirements, also generates periodic interference patterns between structures, known as moiré patterns, due to the aforementioned electronic component arrangement, leading to a degradation in display quality. Summary of the Invention

[0004] This invention provides a pixel array substrate, which has a better aperture ratio when used in electrowetting display panels.

[0005] The present invention provides an electrowetting display panel suitable for multi-layer stacking, which has better overall display brightness.

[0006] The pixel array substrate of the present invention includes a substrate and a plurality of pixel units. These pixel units are disposed on the substrate and each includes at least one active element, a pixel electrode, and at least one storage capacitor. The pixel electrode is electrically connected to at least one active element and has a plurality of holes. The at least one storage capacitor is electrically connected to the pixel electrode and the at least one active element. The at least one storage capacitor completely overlaps a portion of the plurality of holes of the pixel electrode.

[0007] The electrowetting display panel of the present invention includes a pixel array substrate, a hydrophobic layer, a counter substrate, a barrier structure layer, an ink layer, and a polar fluid layer. The pixel array substrate includes a substrate and a plurality of pixel units. These pixel units are disposed on the substrate and each includes at least one active element, a pixel electrode, and at least one storage capacitor. The pixel electrode is electrically connected to at least one active element and has a plurality of holes. The at least one storage capacitor is electrically connected to the pixel electrode and the at least one active element. The at least one storage capacitor completely overlaps a portion of the plurality of holes of the pixel electrode. The hydrophobic layer is disposed on the pixel array substrate. The counter substrate overlaps with the pixel array substrate and has a transparent conductive layer. The barrier structure layer is disposed between the pixel array substrate and the counter substrate and defines a plurality of microcavities. The plurality of holes of the pixel electrode overlap these microcavities. The ink layer and the polar fluid layer are disposed within these microcavities. The ink layer is located between the polar fluid layer and the hydrophobic layer.

[0008] Based on the above, in an embodiment of the electrowetting display panel of the present invention, storage capacitors are stacked within some holes of the pixel electrodes of the pixel array substrate. When the display pixels of the electrowetting display panel are in a bright state, the ink layer is concentrated in the area of ​​the multiple holes overlapping the pixel electrodes. At this time, the storage capacitors are still covered by the ink layer and are not exposed in the light-transmitting area. Therefore, the aperture ratio of the electrowetting display panel in the bright state can be effectively increased, thereby improving its display brightness during operation. Attached Figure Description

[0009] Figure 1 This is a top view of the pixel array substrate according to the first embodiment of the present invention;

[0010] Figure 2A and Figure 2B This is a cross-sectional schematic diagram of the electrowetting display panel according to the first embodiment of the present invention;

[0011] Figure 3 yes Figure 2A and Figure 2B A top view of the retaining wall structure layer and pixel electrodes;

[0012] Figure 4 yes Figure 1 A cross-sectional schematic diagram of the pixel array substrate;

[0013] Figures 5A to 5C yes Figure 1 A top view of a portion of the film layers on the pixel array substrate;

[0014] Figure 6 yes Figure 5B An enlarged schematic diagram of a local region of the second metal layer;

[0015] Figure 7 yes Figure 1An enlarged schematic diagram of the storage capacitors on the pixel array substrate;

[0016] Figure 8 This is a top view of the pixel array substrate according to the second embodiment of the present invention;

[0017] Figures 9A to 9C yes Figure 8 A top view of a portion of the film layers on the pixel array substrate;

[0018] Figure 10 This is a top view of the pixel array substrate according to the third embodiment of the present invention;

[0019] Figures 11A to 11C yes Figure 10 A top view of a portion of the film layers on the pixel array substrate.

[0020] Symbol Explanation

[0021] 10: Electrowetting display panel

[0022] 100, 100A, 100B: Pixel array substrate

[0023] 101:Substrate

[0024] 110, 120, 150: Insulation layer

[0025] 120a: Contact hole

[0026] 130: Flattening layer

[0027] 130a: Opening

[0028] 170: Hydrophobic layer

[0029] 200: Opposing substrate

[0030] 310: Ink layer

[0031] 320: Polar fluid layer

[0032] BW: Retaining Wall Structure Layer

[0033] CA: Microchamber

[0034] CL1, CL2, CL3, CL1-A, CL2-A, CL3-A: Connecting wires

[0035] CP1, CP2: Conductive patterns

[0036] CPE1: First capacitor electrode

[0037] CPE2: Second capacitor electrode

[0038] CPE3: Third capacitor electrode

[0039] DA1, DA2, DA3: Circle diameter

[0040] DCL: Driver Circuit Layer

[0041] DE: Drain

[0042] DL, DL-A: Data cable

[0043] G: Gap

[0044] GE1: First gate

[0045] GE2: Second gate

[0046] GL1, GL1-A: First scan line

[0047] GL2, GL2-A: Second scan line

[0048] OP, OP1, OP2, OP3: Holes

[0049] PA: Pixel area

[0050] PE: Pixel Electrode

[0051] PU, PU-A, PU1, PU2, PU1-A, PU2-A: Pixel unit

[0052] S: Spacing

[0053] SC: Semiconductor Pattern

[0054] SCP: Storage Capacitor

[0055] SE: Source

[0056] T, T1, T2: Active (Powered) Components

[0057] TCL: Transparent Conductive Layer

[0058] Z: Direction

[0059] Z1, Z2: Areas

[0060] A-A', B-B': section line Detailed Implementation

[0061] As used herein, “about,” “approximately,” “essentially,” or “substantially” includes the value and the average value within an acceptable range of deviations from a particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and a particular number of errors associated with the measurement (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the value, or, for example, within ±30%, ±20%, ±15%, ±10%, ±5%. Furthermore, the use of “about,” “approximately,” “essentially,” or “substantially” herein may be chosen to select a more acceptable range of deviations or standard deviations depending on the nature of the measurement, the cutting nature, or other properties, and a single standard deviation may not be applicable to all properties.

[0062] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected" to another element, it may be directly on or connected to the other element, or intermediate elements may also be present. Conversely, when an element is referred to as being "directly on" or "directly connected" to another element, no intermediate elements are present. As used herein, "connection" can refer to a physical and / or electrical connection. Furthermore, an "electrical connection" may involve the presence of other elements between the two elements.

[0063] Furthermore, relative terms such as "below" or "bottom" and "above" or "top" may be used herein to describe the relationship between one element and another, as illustrated in the figures. It should be understood that relative terms are intended to include different orientations of the device beyond those shown in the figures. For example, if a device in one figure is flipped, an element described as being "below" to another element will be oriented "above" to that element. Thus, the exemplary term "below" can include both "below" and "above" orientations, depending on the specific orientation of the figure. Similarly, if a device in one figure is flipped, an element described as being "below" or "under" another element will be oriented "above" to that element. Thus, the exemplary terms "above" or "below" can include both "above" and "below" orientations.

[0064] This document describes exemplary embodiments with reference to cross-sectional views as schematic diagrams of idealized embodiments. Therefore, variations in the shape of the illustrations can be expected as a result of, for example, manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include, for example, shape deviations caused by manufacturing processes. For example, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, the acute angles shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the precise shapes of the regions, nor are they intended to limit the claims.

[0065] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0066] Figure 1 This is a top view of a pixel array substrate according to a first embodiment of the present invention. Figure 2A and Figure 2B This is a cross-sectional schematic diagram of an electrowetting display panel according to a first embodiment of the present invention. Figure 3 yes Figure 2A and Figure 2B A top view of the retaining wall structure layer and pixel electrodes. Figure 4 yes Figure 1 A cross-sectional schematic diagram of the pixel array substrate. Figures 5A to 5C yes Figure 1 A top view of a portion of the film layers on the pixel array substrate. Figure 6 yes Figure 5B An enlarged schematic diagram of a local area of ​​the second metal layer. Figure 7 yes Figure 1 An enlarged schematic diagram of the storage capacitors on the pixel array substrate. Figure 2A and Figure 2B The pixel array substrate corresponds to Figure 1 The section line A-A'. Figure 4 Corresponding to Figure 1 The section line B-B'. Figure 6 This corresponds to region Z2 in Figure 5. Figure 7 Corresponding to Figure 1 Region Z1.

[0067] Please refer to Figures 1 to 3 The electrowetting display panel 10 includes a pixel array substrate 100, a hydrophobic layer 170, a counter substrate 200, a barrier structure layer BW, an ink layer 310, and a polar fluid layer 320. The counter substrate 200 overlaps with the pixel array substrate 100. The hydrophobic layer 170 is disposed on the pixel array substrate 100, and an insulating layer 150 may be provided between the hydrophobic layer 170 and the pixel array substrate 100. The barrier structure layer BW is disposed between the pixel array substrate 100 and the counter substrate 200, and defines a plurality of microcavities CA. The ink layer 310 and the polar fluid layer 320 are disposed within these microcavities CA. The ink layer 310 is located between the polar fluid layer 320 and the hydrophobic layer 170.

[0068] The hydrophobic layer 170 is made of materials such as fluoropolymers, Teflon, or other hydrophobic materials, and its thickness can be between 1 micrometer and 2 micrometers. The opposing substrate 200 is made of materials such as inorganic transparent materials (e.g., glass, quartz, or other suitable materials, or combinations thereof), organic transparent materials (e.g., polyimide, polymethyl methacrylate, plastics, polycarbonate, or other suitable materials, or derivatives thereof), or combinations thereof, whether rigid or flexible light-transmitting materials. This invention uses glass as an example, but is not limited to this.

[0069] In this embodiment, the ink layer 310 is adapted to absorb light within a specific wavelength range, and its hydrophilicity can be altered by energizing the polar fluid layer 320. For example, a driving circuit layer DCL and a pixel electrode PE electrically connected to each other may be provided on the pixel array substrate 100. A transparent conductive layer TCL may be provided on the opposing substrate 200. When the pixel electrode PE and the transparent conductive layer TCL are not energized, the polar fluid layer 320 is pushed away from the hydrophobic layer 170 by the ink layer 310, and the hydrophobic layer 170 is covered by the ink layer 310 (e.g., Figure 2A (As shown). At this time, the light incident on the microcavity CA will be largely absorbed by the ink layer 310, resulting in a dark state of electrowetting display panel 10.

[0070] Conversely, when the pixel electrode PE and the transparent conductive layer TCL are energized (e.g., electrically connected to a DC voltage source), the charge distribution generated on the surface of the hydrophobic layer 170 increases its affinity for the polar fluid layer 320. This causes the polar fluid layer 320 to push the ink layer 310 away and adsorb it onto the hydrophobic layer 170 (e.g., ...). Figure 2B (As shown). At this time, some of the light incident on the microcavity CA is not absorbed by the ink layer 310, but passes through the microcavity CA and is reflected by the reflective layer (not shown) to present the bright state of the electrowetting display panel 10. The polar fluid layer 320 is, for example, water or alcohol, but is not limited thereto.

[0071] Furthermore, the pixel array substrate 100 includes a substrate 101 and a plurality of pixel units PU disposed on the substrate 101. Although Figure 1 Only pixel units PU1 and PU2 arranged adjacently along the horizontal direction are shown for illustrative purposes. However, it should be understood that the plurality of pixel units PU in this embodiment can be arranged separately along the horizontal direction. Figure 1 The pixels are arranged in multiple columns and rows in the horizontal and vertical directions to form a complete display surface. In this embodiment, each pixel unit PU may have a pixel electrode PE, and the pixel electrode PE may define a pixel area PA of the electrowetting display panel 10. That is, each pixel area PA contains one pixel unit.

[0072] Please refer to Figure 1 and Figure 4 The driving circuit layer (DCL) includes active elements (T) and storage capacitors (SCP). Pixel electrodes (PE) are electrically connected to the active elements (T) and storage capacitors (SCP). The active elements (T), storage capacitors (SCP), and pixel electrodes (PE) can constitute a pixel unit (PU). It is particularly noteworthy that the number of active elements (T) and storage capacitors (SCP) in each pixel unit (PU) can be multiple. For example, in this embodiment, the number of active elements (T) in each pixel unit (e.g., pixel unit PU1 and pixel unit PU2) can be two (e.g., a first active element T1 and a second active element T2), and the number of storage capacitors (SCP) can be twelve. However, the invention is not limited to this. In other embodiments not shown, the number of active elements (T) and storage capacitors (SCP) in each pixel unit can be adjusted according to the electrical requirements of the actual product.

[0073] In this embodiment, the pixel electrode PE has multiple holes OP, and these holes OP overlap with multiple microcavities CA defined by the barrier structure layer BW. The overlap relationship here refers, for example, to two components overlapping each other along the stacking direction (e.g., direction Z) of the substrate 101 and the opposing substrate 200. Figure 2A and Figure 3 (As shown). Unless otherwise specified below, the overlapping relationship between the two components is defined in the same way, and the direction of overlap will not be elaborated further. Although Figure 3 The hole OP shown is approximately located at the geometric center of the microchamber CA that overlaps with it, but the invention is not limited thereto. In other embodiments not shown, the hole OP may also be positioned off-center from the geometric center of the microchamber CA. In this embodiment, the pixel electrode PE is along... Figure 1 The width in the horizontal or vertical direction is, for example, 2.5 mm, while the aperture of the hole OP can be between 180 micrometers and 220 micrometers, but is not limited to this.

[0074] It should be noted that these holes OP can define concentrated areas where the ink layer 310 shrinks due to being displaced by the polar fluid layer 320 when the pixel electrode PE is energized (e.g., Figure 2B (As shown). In other words, regardless of whether the pixel electrode PE and the transparent conductive layer TCL are energized, light will be absorbed by the ink layer 310 and will not be able to pass through the microcavity CA when it is incident on the area defined by the holes OP of the pixel electrode PE.

[0075] To prevent the aperture ratio of the pixel unit PU in the bright state from being affected by the setting of the storage capacitor SCP, the storage capacitor SCP can be placed in the area overlapping with the hole OP of the pixel electrode PE. For example... Figure 1As shown, in this embodiment, the twelve storage capacitors SCP are respectively stacked on a portion of the holes OP of the pixel electrode PE. In this embodiment, the first active element T1 and the second active element T2 of the pixel unit PU may also be stacked on another portion of the holes OP of the pixel electrode PE, but this is not a limitation. In other embodiments, the active elements of the pixel unit may not be stacked on the holes OP of the pixel electrode PE.

[0076] More specifically, in this embodiment, twelve storage capacitors SCP are completely overlapped with the twelve holes OP of the pixel electrode PE, and two active elements T are completely overlapped with the other two holes OP of the pixel electrode PE. For example, the projected area of ​​each of the storage capacitors SCP and the active elements T on the substrate 101 may be less than or equal to the projected area of ​​the holes OP on the substrate 101.

[0077] It is particularly noteworthy that for a hole OP overlapping an active element T or a storage capacitor SCP, at least one of the surrounding adjacent holes OP (e.g., six in this embodiment) also overlaps an active element T or a storage capacitor SCP. This allows for a more continuous arrangement of the twelve storage capacitors SCP and two active elements T, simplifying the design of the wiring used to electrically connect these storage capacitors SCP and the active elements T (e.g., ...). Figure 1 (Connecting wires CL1, CL2, and CL3).

[0078] On the other hand, for a hole OP that overlaps with an active element T or a storage capacitor SCP, at least one of the adjacent multiple holes OP (e.g., six in this embodiment) does not overlap with the active element T or the storage capacitor SCP. Therefore, even if these storage capacitors SCP are arranged in a continuous manner with the two active elements T, a closed loop will not be formed. Accordingly, in the manufacturing process of the electrowetting display panel 10, the fluidity of the ink layer 310 and the polar fluid layer 320 when coated on the hydrophobic layer 170 can be increased, which helps to uniformly disperse the ink layer 310 and the polar fluid layer 320 within the multiple microcavities CA of the barrier structure layer BW.

[0079] For example, such as Figure 1 As shown in pixel unit PU2, the first active element T1 and a storage capacitor SCP are completely overlapped with holes OP1 (i.e., the first hole) and OP2 (i.e., the second hole) arranged adjacent to each other along one direction, while another hole OP3 (i.e., the third hole) arranged adjacent to hole OP1 along another direction is not overlapped with any storage capacitor SCP or active element T.

[0080] Please refer to Figure 2AA gap G may be provided between the barrier structure layer BW and the hydrophobic layer 170, and multiple microcavities CA may be connected through the gap G. For example, the barrier structure layer BW and the hydrophobic layer 170 have a spacing S along the Z direction, and this spacing S may be between 0.5 micrometers and 7 micrometers. Accordingly, during the assembly process of the opposing substrate 200 and the pixel array substrate 100, the flowability of the ink layer 310 and the polar fluid layer 320 between different microcavities CA can be increased, which helps to improve the assembly yield.

[0081] Please refer to Figure 1 and Figure 4 Furthermore, the active element T may include a semiconductor pattern SC, a first gate GE1, a second gate GE2, a source SE, and a drain DE. The first gate GE1 is disposed between the substrate 101 and the semiconductor pattern SC, and overlaps with the semiconductor pattern SC. The second gate GE2 is disposed on the side of the semiconductor pattern SC away from the first gate GE1, and overlaps with the semiconductor pattern SC. The source SE and the drain DE are electrically connected to two different locations on the semiconductor pattern SC, respectively. An insulating layer 110 is provided between the first gate GE1 and the semiconductor pattern SC. An insulating layer 120 covers the source SE, the drain DE, and the semiconductor pattern SC, and the second gate GE2 is disposed on the insulating layer 120. That is, the active element T in this embodiment is an active element with a dual-gate structure.

[0082] In this embodiment, the active element T is, for example, an amorphous silicon thin-film transistor (a-Si TFT), but is not limited thereto. In other embodiments, the active element T may also be a low-temperature polycrystalline silicon thin-film transistor (LTPS TFT), a microcrystalline silicon thin-film transistor (micro-Si TFT), or a metal oxide transistor (Metal Oxide Transistor). A planarization layer 130 is covered on the active element T. The pixel electrode PE is disposed on the planarization layer 130 and is electrically connected to the drain DE of the active element T. The thickness of the planarization layer 130 may be in the range of 2.5 micrometers to 3 micrometers.

[0083] On the other hand, the storage capacitor SCP may be, for example, a stacked structure of a first capacitor electrode CPE1, a second capacitor electrode CPE2, and a third capacitor electrode CPE3, but is not limited thereto. An insulating layer 110 is provided between the first capacitor electrode CPE1 and the second capacitor electrode CPE2, and an insulating layer 120 is provided between the second capacitor electrode CPE2 and the third capacitor electrode CPE3.

[0084] Please refer to Figure 4 and Figure 5AThe first gate GE1 of the active element T and the first capacitor electrode CPE1 of the storage capacitor SCP may belong to the same film layer (e.g., a first metal layer). To electrically connect the multiple first capacitor electrodes CPE1 of the multiple storage capacitors SCP to each other, the first metal layer may also have connecting wires CL1 formed therein. The multiple first capacitor electrodes CPE1 are all located on the extension path of the connecting wires CL1 and are electrically connected to the connecting wires CL1. More specifically, these first capacitor electrodes CPE1 may be multiple conductive patterns extending from the connecting wires CL1, and these conductive patterns respectively overlap a portion of the hole OP of the pixel electrode PE.

[0085] Furthermore, a first scan line GL1 is formed in the first metal layer, wherein the first gate GE1 of the first active element T1 and the first gate GE1 of the second active element T2 are both electrically connected to the first scan line GL1. It is particularly noteworthy that, in this embodiment, a portion of the first scan line GL1 conforms to and overlaps with a portion of the edge contour of the pixel electrode PE. More specifically, a portion of the first scan line GL1 can completely overlap with the barrier structure layer BW (e.g., ...). Figure 3 (As shown), but not limited to this. Accordingly, the aperture ratio of the pixel unit PU in the bright state can be further increased, thereby improving the display brightness of the electrowetting display panel 10 during operation.

[0086] Please refer to Figure 4 , Figure 5B and Figure 6 The source (SE) and drain (DE) of the active element T, and the second capacitor electrode (CPE2) of the storage capacitor SCP, may belong to the same film layer (e.g., a second metal layer). To electrically connect the multiple second capacitor electrodes (CPE2) of the multiple storage capacitors SCP, the second metal layer may also have connecting wires (CL2). The multiple second capacitor electrodes (CPE2) are all located on the extension path of the connecting wires (CL2) and are electrically connected to them. More specifically, these second capacitor electrodes (CPE2) may be multiple conductive patterns extending from the connecting wires (CL2), and these conductive patterns overlap the portions of the holes (OP) of the pixel electrode PE. The drain (DE) of the first active element T1 and the drain (DE) of the second active element T2 are both electrically connected to the connecting wires (CL2).

[0087] Furthermore, a data line DL is formed in the second metal layer, wherein the source SE of the first active element T1 and the source SE of the second active element T2 are both electrically connected to the data line DL. It is particularly noteworthy that in this embodiment, the data line DL may conform to a portion of the edge contour of the pixel electrode PE and be spaced apart from the pixel electrode PE, but this is not a limitation. In other embodiments not shown, a portion of the edge contour of the pixel electrode PE may also overlap with the data line DL. More specifically, in this embodiment, the data line DL may completely overlap with the barrier structure layer BW (e.g., Figure 3 (As shown), but not limited to this. Accordingly, the aperture ratio of the pixel unit PU in the bright state can be further increased, thereby improving the display brightness of the electrowetting display panel 10 during operation.

[0088] In this embodiment, the second metal layer may also have a conductive pattern CP1 formed thereon. The conductive pattern CP1 is electrically connected to the connecting wire CL2 and is structurally separated from the second capacitor electrode CPE2.

[0089] Please refer to Figure 4 and Figure 5C The second gate GE2 of the active element T and the third capacitor electrode CPE3 of the storage capacitor SCP may belong to the same film layer (e.g., a third metal layer). To electrically connect the multiple third capacitor electrodes CPE3 of the multiple storage capacitors SCP to each other, the third metal layer may also have connecting wires CL3 formed therein. The multiple third capacitor electrodes CPE3 are all located on the extension path of the connecting wires CL3 and are electrically connected to the connecting wires CL3. More specifically, these third capacitor electrodes CPE3 may be multiple conductive patterns extending from the connecting wires CL3, and these conductive patterns respectively overlap the portions of the holes OP of the pixel electrode PE.

[0090] Furthermore, a second scan line GL2 is formed in the third metal layer, wherein the second gate GE2 of the first active element T1 and the second gate GE2 of the second active element T2 are both electrically connected to the second scan line GL2. It is particularly noteworthy that, in this embodiment, a portion of the second scan line GL2 conforms to and overlaps with a portion of the edge contour of the pixel electrode PE. More specifically, a portion of the second scan line GL2 can completely overlap with the barrier structure layer BW (e.g., ...). Figure 3 (As shown), but not limited to this. Accordingly, the aperture ratio of the pixel unit PU in the bright state can be further increased, thereby improving the display brightness of the electrowetting display panel 10 during operation.

[0091] In this embodiment, the third metal layer may also have a conductive pattern CP2. The conductive pattern CP2 is structurally independent of the second capacitor electrode CPE2 and the connecting wire CL3. For example, the insulating layer 120 between the second and third metal layers may have a contact hole 120a. The conductive pattern CP2 of the third metal layer may be disposed within the contact hole 120a of the insulating layer 120 and directly contact the conductive pattern CP1 of the second metal layer. In this embodiment, the planarization layer 130 may have an opening 130a, and the pixel electrode PE disposed on the planarization layer 130 may extend into this opening 130a to contact the conductive pattern CP2. That is, the conductive pattern CP1 of the second metal layer and the conductive pattern CP2 of the third metal layer may serve as an electrical bridging structure between the pixel electrode PE and the drain DE (or connecting wire CL2) of the active element T, but are not limited thereto.

[0092] Please refer to Figure 1 In this embodiment, connecting wires CL1 and CL3 can each have a fixed potential or a ground potential. That is, connecting wires CL1 and CL3 can be, for example, common electrode lines, but are not limited thereto. The potentials of the second capacitor electrode CPE2 and connecting wire CL2 can be adjusted by the control of the active element T. It is particularly noteworthy that, in order to maximize the aperture ratio of the pixel unit PU in the bright state, the first scan line GL1 of the first metal layer and the second scan line GL2 of the second metal layer can be arranged overlapping each other, and the connecting wires CL1 of the first metal layer, CL2 of the second metal layer, and CL3 of the third metal layer can be arranged overlapping each other. For example, the extension paths of connecting wires CL1, CL2, and CL3 among the multiple storage capacitors SCP are substantially the same (e.g., Figures 5A to 5C (As shown).

[0093] Please refer to Figure 1 and Figure 7 In this embodiment, the orthographic projection outline of the capacitor electrode of the storage capacitor SCP on the substrate 101 is, for example, circular, but not limited thereto. In order to reduce the risk of membrane breakage or wire breakage due to topographic discontinuity when connecting the connecting wires of each metal layer to the corresponding capacitor electrode, the circular diameter DA1 of the first capacitor electrode CPE1 of the storage capacitor SCP may be larger than the circular diameter DA2 of the second capacitor electrode CPE2, and the circular diameter DA2 of the second capacitor electrode CPE2 may be larger than the circular diameter DA3 of the third capacitor electrode CPE3.

[0094] The following are some other embodiments to illustrate the present invention in detail, wherein the same components will be marked with the same symbols, and the description of the same technical content will be omitted. For the omitted parts, please refer to the foregoing embodiments, and they will not be repeated below.

[0095] Figure 8 This is a top view of a pixel array substrate according to a second embodiment of the present invention. Figures 9A to 9C yes Figure 8 A top-view schematic diagram of a portion of the film layers on the pixel array substrate. Please refer to... Figure 8 In this embodiment, the pixel array substrate 100A and Figure 1 The difference between the pixel array substrate 100 and the other pixel array substrate 100 lies in the different configurations of the data lines, scan lines, connecting wires, and storage capacitors. Specifically, in this embodiment, the multiple (e.g., three) storage capacitors SCP of each of the multiple pixel units PU-A (e.g., pixel units PU1-A and pixel units PU2-A) are aligned with the two active elements T along one direction (e.g., ...). Figure 8 Arranged in the horizontal direction.

[0096] Accordingly, the connecting wires CL1-A of the first metal layer of the pixel array substrate 100A (such as...) Figure 9A As shown), the connecting wire CL2-A of the second metal layer (as shown) Figure 9B (as shown) and the connecting wire CL3-A of the third metal layer (as shown) Figure 9C (As shown) is also in Figure 8 It extends in the horizontal direction.

[0097] On the other hand, in this embodiment, the first scan line GL1-A of the first metal layer (e.g.) Figure 9A (as shown) and the second scan line GL2-A of the third metal layer (as shown) Figure 9C (As shown) can be selectively parallel to connecting wires CL1-A and CL3-A. That is, in this embodiment, the first scan line GL1-A and the second scan line GL2-A do not have line segments conforming to and overlapping a portion of the edge contour of the pixel electrode PE (e.g., Figure 1 The first scan line GL1 and the second scan line GL2 are segmented lines. Similarly, the data line DL-A in this embodiment may not have line segments conforming to the partial edge contour of the pixel electrode PE (e.g., Figure 1 The broken line segment of the data line DL). More specifically, the data line DL-A is only in a single direction (e.g., Figure 8 Extending in the vertical direction, and the partial holes OP of the pixel electrode PE can overlap with the data line DL-A.

[0098] Figure 10 This is a top view of a pixel array substrate according to a third embodiment of the present invention. Figures 11A to 11C yes Figure 10 A top-view schematic diagram of a portion of the film layers on the pixel array substrate. Please refer to... Figures 10 to 11C In this embodiment, the pixel array substrate 100B and Figure 1 The difference between the pixel array substrate 100 and the other one is that the data lines and scan lines are configured differently.

[0099] In this embodiment, the data line DL-A of the pixel array substrate 100B may not have line segments conforming to the partial edge contour of the pixel electrode PE (e.g., Figure 1 The broken line segment of the data line DL). More specifically, the data line DL-A is only in a single direction (e.g., Figure 10 Extending vertically in the direction of the data line DL-A, and the partial hole OP of the pixel electrode PE can overlap with the data line DL-A. Similarly, in this embodiment, the first scan line GL1-A (as shown in the figure) extends vertically in the direction of the data line DL-A, and a portion of the hole OP of the pixel electrode PE can overlap with the data line DL-A. Figure 11A (as shown) and the second scan line GL2-A (as shown) Figure 11C (As shown) does not have line segments that conform to and overlap with the partial edge contour of the pixel electrode PE (such as... Figure 1 (The broken line segments of the first scan line GL1 and the second scan line GL2).

[0100] Since the connecting wires CL1, CL2, CL3, storage capacitor SCP, and active element T in this embodiment are all similar to Figure 1 The pixel array substrate 100 is described in detail in the relevant paragraphs of the foregoing embodiments, and will not be repeated here. It should be noted that... Figure 8 Pixel array substrate 100A and Figure 10 The pixel array substrate 100B can be used to replace Figure 2A The pixel array substrate 100 is used to form other modified embodiments of the electrowetting display panel 10.

[0101] In summary, in an embodiment of the electrowetting display panel of the present invention, storage capacitors are stacked within some of the holes of the pixel electrodes of the pixel array substrate. When the display pixels of the electrowetting display panel are in a bright state, the ink layer is concentrated in the area overlapping the multiple holes of the pixel electrodes. At this time, the storage capacitors are still covered by the ink layer and are not exposed in the light-transmitting area. Therefore, the aperture ratio of the electrowetting display panel in the bright state can be effectively increased, thereby improving its display brightness during operation.

Claims

1. A pixel array substrate, comprising: a substrate; and a plurality of pixel units disposed on the substrate and each comprising: at least one active element; a pixel electrode electrically connected to the at least one active element and having a plurality of holes; and at least one storage capacitor electrically connected to the pixel electrode and the at least one active element, wherein the at least one storage capacitor completely overlaps a portion of the holes of the pixel electrode, wherein the holes comprise a first hole and a second hole arranged adjacent to each other, a first storage capacitor of the at least one storage capacitor completely overlaps the first hole, and a second storage capacitor of the at least one storage capacitor or a first active element of the at least one active element completely overlaps the second hole. 2.The pixel array substrate of claim 1, wherein an area of a projection of each of the at least one storage capacitor on the substrate is less than or equal to an area of a projection of each of the holes on the substrate. 3.The pixel array substrate of claim 1, wherein the at least one active element completely overlaps another portion of the holes of the pixel electrode. 4.The pixel array substrate of claim 3, wherein an area of a projection of each of the at least one active element on the substrate is less than or equal to an area of a projection of each of the holes on the substrate. 5.The pixel array substrate of claim 4, wherein the holes further comprise a third hole arranged adjacent to the first hole, and the at least one storage capacitor and the at least one active element do not overlap the third hole. 6.The pixel array substrate of claim 1, wherein each of the at least one active element comprises: a semiconductor pattern; a first gate disposed between the semiconductor pattern and the substrate; a second gate disposed on a side of the semiconductor pattern facing away from the first gate; and a source and a drain electrically connected to different two places of the semiconductor pattern respectively, and the drain is electrically connected to the pixel electrode. 7.The pixel array substrate of claim 6, wherein each of the at least one storage capacitor is a stacked structure of a first capacitor electrode, a second capacitor electrode and a third capacitor electrode, the first capacitor electrode and the first gate are in the same film layer, the second capacitor electrode, the source and the drain are in the same film layer, and the third capacitor electrode and the second gate are in the same film layer. 8.The pixel array substrate of claim 1, wherein the at least one active element comprises a first active element and a second active element electrically connected to each other, the holes comprise a first hole and a second hole arranged adjacent to each other, the first active element and the second active element respectively overlap the first hole and the second hole, and both are electrically connected to the same data line and the same scan line. 9.The pixel array substrate of claim 1, further comprising a connecting wire electrically connected to the at least one storage capacitor, wherein the portion of the holes of the pixel electrode overlaps the connecting wire. 10.An electrowetting display panel, comprising: a pixel array substrate, comprising: a substrate; and a plurality of pixel units disposed on the substrate and each comprising: at least one active element; a pixel electrode electrically connected to the at least one active element and having a plurality of holes; and at least one storage capacitor electrically connected to the pixel electrode and the at least one active element, wherein the at least one storage capacitor completely overlaps a portion of the holes of the pixel electrode, wherein the holes comprise a first hole and a second hole arranged adjacent to each other, a first storage capacitor of the at least one storage capacitor completely overlaps the first hole, and a second storage capacitor of the at least one storage capacitor or a first active element of the at least one active element completely overlaps the second hole. at least one storage capacitor electrically connected between the pixel electrode and the at least one active element, wherein the at least one storage capacitor completely overlaps a portion of the holes of the pixel electrode; a hydrophobic layer disposed on the pixel array substrate; a counter substrate disposed in overlapping relation to the pixel array substrate and having a transparent conductive layer; a barrier structure layer disposed between the pixel array substrate and the counter substrate and defining a plurality of microcavities, the holes of the pixel electrode each overlapping a microcavity; an ink layer disposed in the microcavities; and a polar fluid layer disposed in the microcavities, wherein the ink layer is between the polar fluid layer and the hydrophobic layer, wherein the holes include first holes and second holes arranged adjacent to each other, a first storage capacitor of the at least one storage capacitor completely overlaps the first holes, and a second storage capacitor of the at least one storage capacitor or a first active element of the at least one active element completely overlaps the second holes.

11. The electrowetting display panel of claim 10, wherein the at least one active element completely overlaps another portion of the holes of the pixel electrode.

12. The electrowetting display panel of claim 11, wherein each of the at least one storage capacitor or each of the at least one active element has a smaller or equal area of a footprint on the substrate than each of the holes.

13. The electrowetting display panel of claim 10, wherein the holes further include third holes arranged adjacent to the first holes, and the at least one storage capacitor and the at least one active element do not overlap the third holes.

14. The electrowetting display panel of claim 10, wherein each of the at least one active element includes: a semiconductor pattern; a first gate disposed between the semiconductor pattern and the substrate; a second gate disposed on a side of the semiconductor pattern opposite the first gate; and a source and a drain each electrically connected to a different portion of the semiconductor pattern, the drain being electrically connected to the pixel electrode.

15. The electrowetting display panel of claim 14, wherein each of the at least one storage capacitor is a stack structure of a first capacitor electrode, a second capacitor electrode, and a third capacitor electrode, the first capacitor electrode being a same film layer as the first gate, the second capacitor electrode, the source, and the drain being a same film layer, and the third capacitor electrode being a same film layer as the second gate.

16. The electrowetting display panel of claim 10, wherein the at least one active element includes a first active element and a second active element electrically connected to each other, the holes include first holes and second holes arranged adjacent to each other, the first active element and the second active element each overlap the first holes and the second holes, and are each electrically connected to a same data line and a same scan line.

17. The electrowetting display panel of claim 10, further comprising a connection wire electrically connected to the at least one storage capacitor, wherein the portion of the holes of the pixel electrode overlaps the connection wire. ​ 18.The electrowetting display panel of claim 10, wherein a gap is provided between the barrier structure layer and the hydrophobic layer, and the micro-cavities are communicated through the gap.

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