An FPGA-based accelerated stream time series feature extraction method
By using FPGA for real-time data acquisition and feature extraction, combined with parallel computing and buffer management, the problems of high computing cost and high power consumption in existing technologies are solved, and efficient, real-time feature extraction and data processing are achieved.
Patent Information
- Application Number
- CN202310043682.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-01-29
- Publication Date
- 2025-12-09
- Estimated Expiration
- 2043-01-29
AI Technical Summary
Existing technologies in data analysis suffer from high computational costs and high power consumption in the real-time feature extraction process, making it difficult to achieve efficient and real-time feature extraction.
FPGA is used for real-time data acquisition, feature extraction and normalization. Data is transmitted through a first-in-first-out queue. Parallel computing and buffer management are used to achieve efficient and real-time feature extraction.
It achieves efficient and real-time feature extraction, reduces computational latency and power consumption, improves the stability and availability of data processing, and reduces data redundancy.
Smart Images
Figure CN116049652B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of data analysis, in particular to an FPGA-based accelerated streaming time series feature extraction method. BACKGROUND
[0002] With the increase of available data, especially time series data, the importance of different data analysis techniques has increased. One technique used by many data scientists is to find features in sub-sequences of a dataset. Features can be quantified through a process called feature extraction. This feature extraction step is often computationally expensive and usually requires the entire dataset to be available. During the data collection phase, we want to see patterns or features. This can be achieved through real-time feature extraction, computing the feature set while the data is streaming in. FPGA, Field Programmable Gate Array, has access to a large number of I / O, allowing data to flow directly to the computing unit, thus enabling efficient, real-time feature extraction. We provide an FPGA architecture that is capable of extracting features in real-time, while providing latency and power optimization.
[0003] Traditional CPU systems have to pass data through the memory hierarchy before starting computation. FPGA is capable of streaming data points directly to the computing architecture and provides a large number of I / O. The combination of these two features makes FPGA a perfect candidate for performing real-time feature extraction. FPGA can also take advantage of parallelism to reduce the latency of computation, while running at a lower clock frequency in general, thus reducing power consumption. SUMMARY
[0004] The present application provides an FPGA-based accelerated streaming time feature extraction method to solve the problem of efficient, real-time feature extraction, while providing latency and power optimization.
[0005] The FPGA-based accelerated streaming time feature extraction method provided by the present application, the process comprises:
[0006] S1: obtaining sample data points by real-time data acquisition through FPGA;
[0007] S2: extracting time series features of the sample data points through FPGA to obtain time series features and transmitting the time series features of each data point through a first-in-first-out queue to a parallel region;
[0008] S3: simultaneously computing the time series feature scores of each sample data point in the parallel region and writing the feature scores into respective score buffer areas;
[0009] S4: when the score buffer area is full, normalizing the feature scores to obtain a feature vector and writing the feature vector through a first-in-first-out queue to a host.
[0010] Further, the sampling data points obtained by the FPGA real-time data acquisition includes:
[0011] S101: The FPGA receives the data generated by the data generation device in real time;
[0012] S102: The FPGA obtains the NLP time sequence of the data generated by the data generation device, and samples to obtain the sampling data points according to the NLP time sequence.
[0013] Further, the FPGA extracts the time sequence features of the sampling data points to obtain the time sequence features and transmits the time sequence features of each data point to the parallel region through the first-in-first-out queue, including:
[0014] S201: Determine the content and data type contained in the data of the sampling data points;
[0015] S202: The FPGA extracts the time sequence features of the sampling data points according to the content and data type of the sampling data points to obtain the time sequence features;
[0016] S203: Remove the obvious outliers of the time sequence features; use linear interpolation analysis method to fill in the removed values, and use linear interpolation analysis method to fill in the missing features of the time sequence points to obtain the preprocessed time sequence features;
[0017] S204: Transmit the preprocessed time sequence features to the parallel region through the first-in-first-out queue.
[0018] Further, the parallel region simultaneously calculates the time sequence feature scores of each sampling data point and writes the feature scores into the respective score buffer, including:
[0019] S301: The parallel region inputs the preprocessed time sequence features into the machine training model;
[0020] S302: The parallel region simultaneously calculates the preprocessed time sequence features according to the machine training model to obtain the feature scores;
[0021] S303: Write the feature scores into the respective score buffer.
[0022] Further, when the score buffer is full, the feature scores are normalized to obtain the feature vectors, and the feature vectors are written into the host through the first-in-first-out queue, including:
[0023] S401: The system determines whether the score buffer is full;
[0024] S402: If the buffer is not full, the parallel region simultaneously calculates the feature score of each sampled data point and writes the feature score into its respective score buffer;
[0025] S403: If the score buffer is full, the network controller controls the network to pause data transmission and normalizes the data feature scores in the buffer to obtain feature vectors.
[0026] S404: The feature vector is written to the host in a first-in-first-out queue, and then the network controller controls the network to continue data transmission.
[0027] This invention provides an FPGA-based accelerated streaming time series feature extraction system, the system comprising:
[0028] Real-time acquisition module: Obtains sampled data points in real time through FPGA;
[0029] Feature transmission module: The FPGA extracts the time series features of the sampled data points and transmits the time series features of each data point to the parallel area through a first-in-first-out queue;
[0030] Feature score writing module: The parallel region simultaneously calculates the time series feature score for each sampled data point and writes the feature score into its respective score buffer;
[0031] Normalization processing module: When the score buffer is full, the FPGA normalizes the feature scores to obtain feature vectors and writes the feature vectors to the host through a first-in-first-out queue.
[0032] Furthermore, the real-time acquisition module includes:
[0033] Real-time receiving module: The FPGA receives data generated by the data generator in real time;
[0034] Time series sampling module: The FPGA acquires the NLP time series of data generated by the data generation device, and obtains sampled data points based on the NLP time series.
[0035] Furthermore, the feature transmission module includes:
[0036] Content type determination module: determines the content and data type of the sampled data points;
[0037] Time series feature extraction module: The FPGA extracts the time series features of the sampled data points based on the content and data type of the sampled data points.
[0038] Preprocessing module: remove the obvious outliers of the time series features; fill in the removed values by using linear interpolation analysis, and fill in the missing features of the time series points by using linear interpolation analysis to obtain preprocessed time series features;
[0039] Transmission module: transmit the preprocessed time series features to the parallel region through a first-in first-out queue.
[0040] Further, the feature score writing module comprises:
[0041] Input machine training model module: the parallel region inputs the preprocessed time series features into a machine training model;
[0042] Feature score obtaining module: the parallel region obtains feature scores of the preprocessed time series features according to the machine training model;
[0043] Score buffer module: write the feature scores into respective score buffers.
[0044] Further, the normalization processing module comprises:
[0045] Determination module: the system determines whether the score buffer is full;
[0046] Buffer not full module: if the buffer is not full, the parallel region simultaneously calculates feature scores of each sampling data point and writes the feature scores into respective score buffers;
[0047] Buffer full module: if the score buffer is full, the network controller controls the network to pause data transmission, and performs normalization processing on the feature scores of the data in the buffer to obtain a feature vector;
[0048] Feature vector writing module: write the feature vector into the host according to a first-in first-out queue, and then the network controller controls the network to continue data transmission.
[0049] The present application has the following advantages: FPGA can access a large number of I / O, allowing data to flow directly to the computing unit, thereby realizing efficient and real-time feature extraction; FPGA can receive data generated by a data occurrence device in real time, collect time series data features in real time and extract features, so that the features of the data can be seen during the data collection stage, thereby realizing efficient and real-time feature extraction; FPGA can also utilize parallelism to reduce the delay of calculation, and in general cases, it operates at a relatively low clock frequency, thereby reducing power consumption. BRIEF DESCRIPTION OF DRAWINGS
[0050] Figure 1 It is a schematic diagram of an FPGA-based accelerated streaming time feature extraction method;
[0051] Figure 2 Figure 1 is a schematic diagram of an FPGA-based accelerated streaming time feature extraction system. DETAILED DESCRIPTION
[0052] The preferred embodiments of the present application will be described in detail with reference to the accompanying drawings, it should be understood that the preferred embodiments described herein are only used to explain and illustrate the present application, and are not used to limit the present application.
[0053] One embodiment of the present application is an FPGA-based accelerated streaming time feature extraction method, the process includes:
[0054] S1: obtaining sample data points by FPGA real-time data acquisition;
[0055] S2: extracting time series features of the sample data points by FPGA to obtain time series features and transmitting the time series features of each data point to the parallel region through the first-in-first-out queue;
[0056] S3: calculating the time series feature scores of each sample data point in the parallel region at the same time and writing the feature scores into the respective score buffer;
[0057] S4: when the score buffer is full, normalizing the feature scores to obtain a feature vector and writing the feature vector into the host through the first-in-first-out queue.
[0058] The working principle of the above technical solution is that FPGA real-time data acquisition obtains sample data points, and extracts the time series features of the sample data points to obtain time series features and transmits the time series features of each data point to the parallel region through the first-in-first-out queue. The parallel region calculates the time series feature scores of each sample data point at the same time and writes the feature scores into the respective score buffer. When the score buffer is full, the feature scores are normalized to obtain a feature vector and the feature vector is written into the host through the first-in-first-out queue.
[0059] The effect of the above technical solution is that by real-time accessing the data generator, data is obtained more efficiently. By extracting the features of the sample points, the sample point data features can be extracted in real time while the data is being obtained. FPGA transmits the time series features of each data point to the parallel region through the first-in-first-out queue, ensuring the stability, reliability and availability of the data. The parallel region calculates the feature scores and writes them into the respective score buffer at the same time. The parallel region calculates at the same time, which improves the speed and makes the data processing more efficient. When the buffer is full, the feature scores are normalized to classify the features and the feature vector is written into the host through the first-in-first-out queue for better searching and utilization later, and to reduce data redundancy.
[0060] One embodiment of the application, by FPGA real-time data acquisition data points, including:
[0061] S101: FPGA real-time receiving data generated by the data generation device;
[0062] S102: FPGA obtains the NLP time sequence of the data generated by the data generation device, and samples the sampling data points according to the NLP time sequence.
[0063] The working principle of the above technical solution is that FPGA real-time receiving data generated by the data generation device; FPGA obtains the NLP time sequence of the data generated by the data generation device, and samples the sampling data points according to the NLP time sequence.
[0064] The effect of the above technical solution is that FPGA real-time receiving data generated by the data generation device; FPGA obtains the NLP time sequence of the data generated by the data generation device, and samples the sampling data points according to the NLP time sequence; by real-time accessing the data generator, the data is obtained, the data is obtained more efficiently, by obtaining the NLP time sequence, the sampling data points are obtained according to the time sequence, different time periods, time points of the sampling record can be obtained according to the requirements, and the obtained data is more suitable for actual application.
[0065] One embodiment of the application, FPGA extracts the time sequence features of the sampling data points, and transmits the time sequence features of each data point to the parallel region through the first-in first-out queue, including:
[0066] S201: determine the content and data type contained in the sampling data points; the content of the sampling points may include sound, image, temperature, humidity, etc., and the data type includes continuous variable, category variable, etc.;
[0067] S202: FPGA extracts the time sequence features of the sampling data points according to the content and data type of the sampling data points to obtain the time sequence features; different algorithms are set in the FPGA chip, different contents and data types are automatically identified, different feature extraction methods are used for feature extraction according to the content and data type;
[0068] S203: remove the obvious outliers of the time sequence features; use linear interpolation analysis method to fill in the removed values, and use linear interpolation analysis method to fill in the missing features of the time sequence points to obtain the preprocessed time sequence features; FPGA automatically identifies the obvious outliers and missing values on the time sequence, and removes and supplements them;
[0069] S204: transmit the preprocessed time sequence features to the parallel region through the first-in first-out queue.
[0070] The working principle of the technical solution is that the content and data type contained in the data of the sampling data points are determined, different algorithms are set in the FPGA chip, different content and data types are automatically identified, different feature extraction methods are used for feature extraction according to the content and data type, and the FPGA automatically identifies the obvious abnormal values and missing values on the time sequence, removes the abnormal values, and supplements the missing values by using the difference analysis method.
[0071] The effect of the technical solution is that the content and data type contained in the data of the sampling data points are determined, different algorithms are set in the FPGA chip, different content and data types are automatically identified, different feature extraction methods are used for feature extraction according to the content and data type, the FPGA automatically identifies the obvious abnormal values and missing values on the time sequence, the extracted features are preprocessed, the abnormal values are removed, and the missing values are supplemented by using the difference analysis method; the intelligentization and high efficiency of data sampling are realized, the missing and redundancy of data are reduced, and the extracted data is more accurate and has strong usability.
[0072] In an embodiment of the present application, the time sequence feature score of each sampling data point is calculated simultaneously in a parallel region and written into a respective score buffer, comprising:
[0073] S301: The preprocessed time sequence features are input into a machine training model in the parallel region; the FPGA chip sets different calculation models for different features through model training, and automatically selects an adaptive calculation model according to the features;
[0074] S302: The parallel region simultaneously calculates the preprocessed time sequence features to obtain feature scores according to the machine training model; the same sampling point may contain different features, such as different temperatures, humidities, and frequencies, each feature value obtains different feature scores (P1, P2, P3...Pn) according to the model, and the feature score of the sampling point is the weighted average of various feature scores, that is, P=aP1+bP2+cP3+...mPn; wherein a, b, c...m are weight coefficients obtained according to actual application and model training;
[0075] S303: The feature scores are written into respective score buffers.
[0076] The working principle of the technical solution is that the preprocessed time sequence features are input into a machine training model in the parallel region; the FPGA chip sets different calculation models for different features through model training, and automatically selects an adaptive calculation model according to the features to calculate the feature scores, the same sampling point may contain different features, the feature score of the sampling point is obtained by weighting according to the model and actual application, and the feature score is written into a respective score buffer.
[0077] The effect of the above technical solution is that the parallel regions simultaneously input features into a machine training model, calculate feature scores according to model training, make the calculation of feature scores more accurate and fast, and fit actual application, obtain more accurate feature scores through weighted average of different features of a point, write the feature scores into respective score buffer areas, temporarily store the features, prepare for subsequent processing, update the cache after processing, and reduce the storage space of the host.
[0078] In one embodiment of the present application, when the score buffer area is full, the feature scores are normalized to obtain feature vectors and the feature vectors are written into the host through a first-in-first-out queue, comprising:
[0079] S401: The system determines whether the score buffer area is full;
[0080] S402: If the buffer area is not full, the parallel regions simultaneously calculate the feature scores of each sampling data point and write the feature scores into respective score buffer areas;
[0081] S403: If the score buffer area is full, the network controller controls the network to pause data transmission, the FPGA normalizes the data feature scores in the buffer area to obtain feature vectors; the Z-Score standardization method is used to adjust the mean of the feature scores in the buffer area to 0 and the standard deviation to 1;
[0082] S404: The feature vectors are written into the host according to a first-in-first-out queue, and then the network controller controls the network to continue data transmission.
[0083] The working principle of the above technical solution is that first, it is determined whether the score buffer area is full, if not, the parallel regions simultaneously calculate the feature scores of each sampling data point and write the feature scores into respective score buffer areas; if the buffer area is full, the network controller controls the network to pause data transmission, normalizes the data feature scores in the buffer area to obtain feature vectors, and writes the feature vectors into the host according to a first-in-first-out queue, and then the network controller controls the network to continue data transmission.
[0084] The effect of the above technical solution is that whether the buffer is full is determined, so that the next action is performed, if the buffer is full, the network controller controls the network to suspend data transmission, and the feature score in the buffer is normalized to obtain a feature vector, which is beneficial to batch calculation of the feature vector and classification, otherwise, the normalization processing is performed, the buffer inputs new feature scores, which is easy to cause confusion and increase the calculation amount, after the normalization processing, the buffer is emptied, new features are input, and the cycle is continued, so that the calculation efficiency and accuracy are improved. The normalization processing can classify the feature vector, reduce database redundancy, better classify the feature vector, and prepare for subsequent data utilization and comparison. The feature vector is written into the host in the first-in first-out queue, so that the data is more clear and orderly, and is easy to query.
[0085] In one embodiment of the application, an FPGA-based accelerated streaming time series feature extraction system comprises:
[0086] A real-time acquisition module acquires sample data points by real-time data acquisition through an FPGA;
[0087] A feature transmission module extracts time series features of the sample data points through the FPGA to obtain the time series features and transmits the time series features of each data point to a parallel region through a first-in first-out queue;
[0088] A feature score writing module simultaneously calculates time series feature scores of each sample data point and writes the feature scores into respective score buffers;
[0089] A normalization processing module normalizes the feature scores through the FPGA to obtain feature vectors and writes the feature vectors into a host through a first-in first-out queue when the score buffers are full.
[0090] The working principle of the above technical solution is that the FPGA acquires sample data points by real-time data acquisition through a real-time acquisition module, then enters a feature transmission module to extract time series features of the sample data points to obtain the time series features and transmits the time series features of each data point to a parallel region through a first-in first-out queue, then enters a feature score writing module to simultaneously calculate time series feature scores of each sample data point and write the feature scores into respective score buffers; when the score buffers are full, finally enters a normalization processing module to normalize the feature scores to obtain feature vectors and write the feature vectors into a host through a first-in first-out queue.
[0091] The effect of the above technical scheme is that: the real-time access data generator is accessed by the real-time acquisition module to acquire data, and the data acquisition is more efficient; the feature transmission module extracts the time sequence feature of the sampling data point, so that the time sequence feature of the sampling data point is extracted in real time while the data is acquired; the feature score writing module FPGA transmits the time sequence feature of each data point to the parallel region through the first-in first-out queue, so as to ensure the stability, reliability and availability of the data; the parallel region calculates the feature score and writes it into the respective score buffer at the same time, the parallel region calculates at the same time, the speed is improved, and the data processing is more efficient; when the buffer is full, the feature score is normalized by the normalization processing module, the features are classified, and the feature vector is written into the host through the first-in first-out queue, so as to be better searched and used later, and the data redundancy is reduced.
[0092] In an embodiment of the present application, the real-time acquisition module comprises:
[0093] The real-time receiving module: the FPGA receives the data generated by the data generating device in real time;
[0094] The time sequence sampling module: the FPGA acquires the NLP time sequence of the data generated by the data generating device, and samples the NLP time sequence to obtain a sampling data point.
[0095] The working principle of the above technical scheme is that: the FPGA receives the data generated by the data generating device in real time in the real-time receiving module; the FPGA acquires the NLP time sequence of the data generated by the data generating device in the time sequence sampling module, and samples the NLP time sequence to obtain a sampling data point.
[0096] The effect of the above technical scheme is that: the FPGA receives the data generated by the data generating device in real time in the real-time receiving module; the FPGA acquires the NLP time sequence of the data generated by the data generating device in the time sequence sampling module, and samples the NLP time sequence to obtain a sampling data point; the data is acquired by accessing the data generator in real time, and the data acquisition is more efficient; the sampling data point is acquired according to the time sequence, and the sampling record of different time periods and time points can be acquired according to the demand, so that the acquired data is more suitable for actual application.
[0097] In an embodiment of the present application, the feature transmission module comprises:
[0098] The content type determination module: determines the content and data type contained in the data of the sampling data point;
[0099] The time sequence feature extraction module: the FPGA extracts the time sequence feature of the sampling data point according to the content and data type of the sampling data point to obtain the time sequence feature;
[0100] The preprocessing module: removing the obvious outliers of the time series features; filling the removed values by using linear interpolation analysis, and filling the missing features of the time series points by using linear interpolation analysis to obtain the preprocessed time series features;
[0101] The transmission module: transmitting the preprocessed time series features to the parallel region through a first-in first-out queue.
[0102] The working principle of the above technical solution is as follows: first, entering the content type determination module, determining the content and data type contained by the data of the sampling data points; entering the time series feature extraction module, setting different algorithms in the FPGA chip, automatically identifying different contents and data types, and performing feature extraction by using different feature extraction methods according to the contents and data types; entering the preprocessing module, the FPGA automatically identifies the obvious outliers and missing values on the time series, removes the outliers, and supplements the missing values by using difference analysis; finally, entering the transmission module: transmitting the preprocessed time series features to the parallel region through a first-in first-out queue.
[0103] The effect of the above technical solution is as follows: the content type determination module determines the content and data type contained by the data of the sampling data points, the time series feature extraction module, the FPGA chip sets different algorithms, automatically identifies different contents and data types, and performs feature extraction by using different feature extraction methods according to the contents and data types, the preprocessing module, the FPGA automatically identifies the obvious outliers and missing values on the time series, and pre-processes the extracted features, removes the outliers, and supplements the missing values by using difference analysis; the transmission module realizes the intelligentization and high efficiency of data sampling, reduces the missing and redundancy of data, and makes the extracted data more accurate and usable.
[0104] In an embodiment of the present application, the feature score writing module comprises:
[0105] The input machine training model module: the parallel region inputs the preprocessed time series features into a machine training model;
[0106] The feature score obtaining module: the parallel region obtains feature scores from the preprocessed time series features according to the machine training model;
[0107] The score buffer module: writing the feature scores into respective score buffers.
[0108] The working principle of the technical solution is that the input machine training model module is entered first, and the parallel region inputs the preprocessed time sequence features into the machine training model; the FPGA chip sets different calculation models for different features through model training, the feature score obtaining module automatically selects an adaptive calculation model according to the features to calculate the feature score, the same sampling point may contain different features, finally, the score buffer module is entered, the feature score of the sampling point is obtained by weighting according to the model and the actual application, and the feature score is written into the respective score buffer.
[0109] The effect of the technical solution is that the parallel region inputs the features into the machine training model through the input machine training model module, the feature score obtaining module calculates the feature score, the calculation of the feature score is accurate and fast, and is suitable for actual application, the feature score obtained by the weighted average of different features of a point is more accurate, the feature score is written into the respective score buffer through the score buffer module, the features are temporarily stored, and the subsequent processing is prepared, the cache is updated after processing, and the storage space of the host is reduced.
[0110] In an embodiment of the present application, the normalization processing module comprises:
[0111] The determination module determines whether the score buffer is full;
[0112] The buffer not full module calculates the feature score of each sampling data point and writes the feature score into the respective score buffer if the buffer is not full;
[0113] The buffer full module performs normalization processing on the data feature score in the buffer to obtain a feature vector if the score buffer is full, and the network controller controls the network to pause data transmission;
[0114] The feature vector writing module writes the feature vector into the host according to a first-in first-out queue, and then the network controller controls the network to continue data transmission.
[0115] The working principle of the technical solution is that the determination module is entered first, it is determined whether the score buffer is full, if not, the buffer not full module is entered, the parallel region calculates the feature score of each sampling data point and writes the feature score into the respective score buffer, if the buffer is full, the buffer full module is entered, the network controller controls the network to pause data transmission, and the feature vector is obtained by performing normalization processing on the data feature score in the buffer, the feature vector writing module writes the feature vector into the host according to a first-in first-out queue, and then the network controller controls the network to continue data transmission.
[0116] The effect of the technical scheme is that the determination module determines whether the buffer is full, so as to perform the next action, if the buffer is full, the buffer full module is entered, the network controller controls the network to suspend data transmission, and the feature score in the buffer is normalized to obtain a feature vector, which is beneficial to batch calculation of the feature vector and classification, otherwise, the normalization processing is performed, the buffer inputs new feature scores, which is easy to cause confusion and increase the calculation amount, after the normalization processing, the buffer is emptied, the buffer not full module is entered, new features are input, and the cycle is continued, so that the calculation efficiency and accuracy are improved. The normalization processing can classify the feature vector, reduce database redundancy, and better classify the feature vector, so as to prepare for subsequent data utilization and comparison. The feature vector writing module writes the feature vector into the host according to the first-in first-out queue, so that the data is more clear and orderly, and is easy to query.
[0117] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application belong to the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.
Claims
1. An FPGA-based accelerated streaming time series feature extraction method, characterized in that, The process comprises: S1: obtaining sample data points by FPGA real-time data acquisition; S2: FPGA extracts time sequence features of the sample data points to obtain time sequence features and transmits the time sequence features of each data point to the parallel region through the first-in-first-out queue; S3: the parallel region simultaneously calculates the time sequence feature scores of each sample data point and writes the feature scores into the respective score buffer; S4: when the score buffer is full, FPGA normalizes the feature scores to obtain a feature vector and writes the feature vector into the host through the first-in-first-out queue.
2. The FPGA-based accelerated streaming time series feature extraction method of claim 1, wherein, The sample data points obtained by FPGA real-time data acquisition comprise: S101: FPGA receives data generated by a data generation device in real time; S102: FPGA obtains the NLP time sequence of the data generated by the data generation device, and samples to obtain sample data points according to the NLP time sequence.
3. The FPGA-based accelerated streaming time series feature extraction method of claim 1, wherein, The FPGA extracts the time sequence features of the sample data points to obtain time sequence features and transmits the time sequence features of each data point to the parallel region through the first-in-first-out queue, comprising: S201: determining the content and data type contained in the sample data points; S202: FPGA extracts the time sequence features of the sample data points according to the content and data type of the sample data points to obtain time sequence features; S203: removing the obvious outliers of the time sequence features; using linear interpolation analysis to fill in the removed values, and using linear interpolation analysis to fill in the missing features of the time sequence points to obtain preprocessed time sequence features; S204: transmitting the preprocessed time sequence features to the parallel region through the first-in-first-out queue.
4. The FPGA-based accelerated streaming time series feature extraction method of claim 3, wherein The parallel region simultaneously calculates the time sequence feature scores of each sample data point and writes the feature scores into the respective score buffer, comprising: S301: the parallel region inputs the preprocessed time sequence features into a machine training model; S302: the parallel region simultaneously calculates the preprocessed time sequence features to obtain feature scores according to the machine training model; S303: write the feature scores into the respective score buffer.
5. The FPGA-based accelerated streaming time series feature extraction method of claim 1, wherein, When the score buffer is full, the feature scores are normalized to obtain a feature vector, and the feature vector is written into the host through the first-in-first-out queue, comprising: S401: the system determines whether the score buffer is full; S402: if the buffer is not full, the parallel region simultaneously calculates the feature scores of each sample data point and writes the feature scores into the respective score buffer; S403: if the score buffer is full, the network controller controls the network to pause data transmission, normalizes the data feature scores in the buffer to obtain a feature vector; S404: write the feature vector into the host according to the first-in-first-out queue, and then the network controller controls the network to continue data transmission.
6. An FPGA-based accelerated streaming time series feature extraction system, comprising: The system comprises: A real-time acquisition module for obtaining sample data points by FPGA real-time data acquisition; The feature transmission module: the FPGA extracts the time series feature of the sampling data point to obtain the time series feature and transmits the time series feature of each data point to the parallel region through a first-in-first-out queue; The feature score writing module: the parallel region simultaneously calculates the time series feature score of each sampling data point and writes the feature score into a respective score buffer; The normalization processing module: when the score buffer is full, the FPGA performs normalization processing on the feature score to obtain a feature vector and writes the feature vector into the host through a first-in-first-out queue.
7. The FPGA-based accelerated streaming time-series feature extraction system of claim 6, wherein, The real-time acquisition module comprises: The real-time receiving module: the FPGA receives data generated by a data generating device in real time; The time series sampling module: the FPGA acquires an NLP time series of the data generated by the data generating device and samples the NLP time series to obtain a sampling data point.
8. The FPGA-based accelerated streaming time-series feature extraction system of claim 6, wherein, The feature transmission module comprises: The content type determination module: determines the content and data type contained in the sampling data point; The time series feature extraction module: the FPGA extracts the time series feature of the sampling data point according to the content and data type of the sampling data point to obtain the time series feature; The preprocessing module: removes obvious outliers of the time series feature; uses a linear interpolation analysis method to fill in the removed values, and simultaneously uses the linear interpolation analysis method to fill in the missing features of the time series point to obtain preprocessed time series features; The transmission module: transmits the preprocessed time series features to the parallel region through a first-in-first-out queue.
9. The FPGA-based accelerated streaming time-series feature extraction system of claim 8, wherein, The feature score writing module comprises: The input machine training model module: the parallel region inputs the preprocessed time series features into a machine training model; The feature score obtaining module: the parallel region simultaneously calculates the preprocessed time series features to obtain feature scores according to the machine training model; The score buffer module: writes the feature scores into respective score buffers.
10. The FPGA-based accelerated streaming time-series feature extraction system of claim 6, wherein, The normalization processing module comprises: The determination module: the system determines whether the score buffer is full; The buffer not full module: if the buffer is not full, the parallel region simultaneously calculates the feature scores of each sampling data point and writes the feature scores into respective score buffers; The buffer full module: if the score buffer is full, the network controller controls the network to pause data transmission, performs normalization processing on the data feature scores in the buffer to obtain a feature vector; The feature vector writing module: writes the feature vector into the host according to a first-in-first-out queue, and then the network controller controls the network to continue data transmission.
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