Method and system for generating hypergraph, and simulation method of circuit

Abstract

The application discloses a supergraph generation method and system, and a circuit simulation method. The supergraph generation method comprises the following steps: constructing a corresponding hierarchical design tree based on a netlist design; generating a data flow graph of each module corresponding to each node of the hierarchical design tree; performing feature analysis on each module based on the data flow graph of each module, putting the nodes corresponding to the modules matching the features of the undesired split modules into a feature list, and putting the nodes corresponding to the other modules into a non-feature list; traversing the nodes in the feature list, deleting the child nodes of the parent nodes in the two lists if the parent nodes of the nodes currently traversed are also in the feature list; after the traversal is completed, judging whether the number of all nodes in the two lists meets a node number constraint, and if yes, generating a supergraph by taking the remaining nodes in the two lists as supergraph nodes. The application can quickly generate a supergraph with good split effect.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit simulation, and in particular to a supergraph generation method and system based on netlist feature extraction. BACKGROUND

[0002] The effect of splitting a chip design into multiple FPGAs in a hardware simulation accelerator will directly affect the running performance of the chip design in the hardware simulation accelerator, thereby affecting the efficiency of chip simulation.

[0003] In the current commonly used splitting method, the splitting problem of such a chip is often converted into a supergraph splitting problem. A supergraph is generated according to the nodes in the netlist and the interconnection relationship of the nodes, and then the netlist design of the chip is split according to the supergraph splitting related algorithm, and then converted into the netlist of each FPGA. Therefore, the quality of the generated supergraph directly affects the effect of the splitting algorithm. The quality of the supergraph here is mainly judged according to the number of nodes in the supergraph, the distribution of resources occupied by each node, and the like.

[0004] In addition, chip designs nowadays are mostly integrated with general-purpose IPs (Integrated Processors), especially AI chip designs, which mostly use NPU (neural processing unit), NFU (neural functional unit), TPU (tensor processing unit), and other modules to form an array structure with extremely high reuse rate for high-density and high-parallelism computation.

[0005] In the prior art, when splitting a chip, these high-density computation modules are not considered, and they are randomly split and placed in different FPGAs for simulation, which can cause problems such as a decrease in the main frequency.

[0006] Therefore, how to handle some modules that users do not expect to be split during the supergraph generation phase to avoid problems such as a decrease in the main frequency is a technical problem that needs to be solved urgently. SUMMARY

[0007] In order to solve the technical problem that the generation of a supergraph in the prior art does not consider modules such as high-density computation modules that users do not expect to be split, the present application proposes a supergraph generation method and system and a circuit simulation method.

[0008] The supergraph generation method proposed by the present application comprises:

[0009] Step 1: constructing a corresponding hierarchical design tree based on the netlist design;

[0010] Step 2, generating a data flow graph of each module corresponding to a node of the hierarchical design tree;

[0011] Step 3, performing feature analysis on each module based on the data flow graph of each module, putting a node corresponding to a module matching a feature of an undesired split module into a feature list, and putting a node corresponding to other modules into a non-feature list;

[0012] Step 4, traversing the nodes in the feature list, if a parent node of a currently traversed node is also in the feature list, deleting a child node of the parent node in the two lists;

[0013] Step 5, after the traversal, judging whether the number of all nodes in the two lists meets a node number constraint, if yes, generating a hypergraph by taking the remaining nodes in the two lists as hypergraph nodes.

[0014] Further, the step 1 comprises:

[0015] Obtaining all modules in the netlist design;

[0016] Parallel processing all modules to generate corresponding sub-trees;

[0017] According to the parent-child relationship of each module, splicing all sub-trees into the hierarchical design tree.

[0018] Further, the step 3 performs feature analysis on each module by pre-constructing a feature extraction comparator, and the construction of the feature extraction comparator comprises:

[0019] Taking a general integrated circuit module and / or a customized integrated circuit module as a training sample;

[0020] Generating a data flow graph of all training samples;

[0021] Training and learning the data flow graph using a convolutional neural network;

[0022] Until the similarity of the features extracted by the convolutional neural network and the expected features meets a preset condition.

[0023] Further, the features extracted by the convolutional neural network include at least one of the number of nodes of the training sample, the resource size occupied by the nodes, and the association relationship of node data.

[0024] Further, the general integrated circuit module includes at least one of an NPU, an NFU, and a TPU.

[0025] Further, the step 3 starts traversing each node from the bottom layer of the hierarchical design tree layer by layer, and performs feature analysis on the data flow graph of each module corresponding to each traversed node.

[0026] Further, in the step 3, the nodes in the two lists are stored in layers, and the nodes in each layer are arranged in order of the size of the occupied resources.

[0027] Further, in the step 4, the nodes in the feature list are traversed from bottom to top according to the layers.

[0028] Further, in the step 5, if the number of nodes in the two lists does not meet the node number constraint, the nodes in the bottom layer of the feature list that have not been merged are traversed in order from large to small, and for each traversed feature node, the bottom layer of the non-feature list is traversed in order from small to large, and for each traversed non-feature node, it is determined whether the current traversed non-feature node and the current traversed feature node have an upper layer association relationship, if yes, it is determined whether the resources occupied by the current traversed non-feature node and the current traversed feature node meet the resource constraint condition, if yes, the two nodes are merged and placed in the feature list, if not, the next non-feature node is traversed, after merging, it is determined whether the number of nodes in the current two lists meets the node number constraint, if not, the next feature node is traversed.

[0029] The supergraph generation system of the present application adopts the supergraph generation method of the above technical solution to generate a supergraph, comprising:

[0030] The netlist parser parses the netlist design of the circuit and constructs a corresponding hierarchical design tree based on the netlist design;

[0031] The data flow graph generator generates a data flow graph for each module corresponding to a node of the hierarchical design tree;

[0032] The feature extraction comparator performs feature analysis on each module based on the data flow graph of each module, and distinguishes between undesired partition modules and other modules;

[0033] The supergraph selection generator adjusts the nodes of the supergraph based on the undesired partition modules and other modules and the node number constraint until the node number constraint is met.

[0034] The circuit simulation method proposed in the present application comprises:

[0035] The netlist design of the circuit is generated into a supergraph using the supergraph generation method of the above technical solution;

[0036] The circuit is partitioned according to the generated supergraph;

[0037] The partitioned circuit parts are processed in parallel simulation.

[0038] The present application generates a hypergraph according to the characteristics of the netlist, so that some modules that are not expected to be partitioned can be as an independent node as much as possible to avoid being partitioned, and the present application can automatically constrain the number of nodes of the hypergraph, and in the process of node merging, make the resources occupied by each node as balanced as possible to optimize the iteration process. Finally, the present application can automatically perform node merging according to the node granularity. The present application enables the partitioning algorithm to quickly partition to obtain a hypergraph with good effect, and improves the efficiency and effect of netlist partitioning. BRIEF DESCRIPTION OF DRAWINGS

[0039] The present application will be described in detail below with reference to the embodiments and drawings, in which:

[0040] Figure 1 is the overall flowchart of an embodiment of the present application.

[0041] Figure 2 is a hierarchical design tree of an embodiment of the present application.

[0042] Figure 3 is a feature list and a featureless list of an embodiment of the present application.

[0043] Figure 4 is the formation flowchart of a feature extraction comparator of an embodiment of the present application.

[0044] Figure 5 is the system block diagram of an embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to make the technical problems to be solved by the present application, the technical solutions and the beneficial effects clearer and more apparent, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0046] Therefore, one feature indicated in the specification will be used to explain one feature of an embodiment of the present application, and it is not implied that each embodiment of the present application must have the explained feature. In addition, it should be noted that the specification describes many features. Although some features can be combined together to show possible system designs, these features can also be used in other combinations that are not explicitly described. Therefore, unless otherwise stated, the described combinations are not intended to be limiting.

[0047] As shown in Figure 1 The hypergraph generation method proposed by the present application mainly includes the following steps.

[0048] Step 1, constructing a corresponding hierarchical design tree based on the netlist design. In this step, the present application reads the post-synthesis gate-level netlist design file to generate a corresponding hierarchical netlist design tree, i.e., a hierarchical design tree, the bottom layer of which is a netlist module, an instance, or a basic logic unit, etc. The basic logic unit refers to units such as LUT, FF, etc.

[0049] Figure 2 One specific embodiment of the hierarchical design tree is shown. The hierarchical design tree has four layers in total, namely level0-level3. The node of level0 is top, corresponding to the top module. The nodes of the previous layer in Level1 can be divided into three sub-nodes a, b, c, and so on.

[0050] Step 2, then generating a data flow graph for each module corresponding to the node of the hierarchical design tree. The data flow graph refers to the data flow graph formed by traversing from the input end of each module to the output end. The output of each module may or may not correspond to connectivity, which is reflected in the data flow graph.

[0051] Step 3, performing feature analysis on each module based on the data flow graph (Data-flow-graph) of each module, and putting the nodes corresponding to the modules that match the characteristics of the undesired partitioning module into the feature list, and putting the nodes corresponding to the other modules into the non-feature list. Through this step, the present application tries to regard the modules that are not desired to be partitioned as an independent node, such as a module with high operation density or some customer-customized modules. These are screened by the data flow graph to form an independent node so as to be placed in the same FPGA for simulation.

[0052] Step 4, traversing the nodes in the feature list, if the parent node of the currently traversed node is also in the feature list, then deleting the child nodes of the parent node in the two lists.

[0053] In one embodiment, it is assumed that the traversal of the nodes is performed from bottom to top, which can easily lead to a large number of nodes. In addition, the parent node can contain non-feature nodes, so the largest parent node in the feature node is regarded as a hypergraph node. In this way, the number of hypergraph nodes can be reduced, and the node resource amount can be enlarged to an appropriate degree, i.e., the granularity is appropriate, avoiding the generation of resource-uniform nodes due to too small node resource amount.

[0054] Step 5, after the traversal is completed, it is judged whether the number of all nodes in the two lists satisfies the node number constraint, if yes, then the remaining nodes in the two lists are taken as hypergraph nodes to generate a hypergraph.

[0055] In one embodiment, the present application adopts the module base idea to obtain the hierarchical design tree through parallel processing, thereby improving the generation efficiency of the hierarchical design tree of the netlist design. In this embodiment, the step 1 comprises the following steps.

[0056] All modules in the netlist design are obtained;

[0057] All modules are then processed in parallel to generate corresponding sub-trees;

[0058] According to the parent-child relationship of each module, all sub-trees are spliced into a hierarchical design tree.

[0059] In one embodiment, the step 3 is performed by pre-constructing a feature extraction comparator to analyze the features of each module. For example, each module is traversed layer by layer from bottom to top in the hierarchical design tree, and each traversed module is input into the feature extraction comparator for feature extraction.

[0060] In one embodiment, the construction of the feature extraction comparator comprises the following steps.

[0061] The general integrated circuit module and / or the customized integrated circuit module are used as training samples;

[0062] A data flow graph of all training samples is generated;

[0063] The data flow graph is trained and learned using a convolutional neural network;

[0064] Until the similarity of the features extracted by the convolutional neural network and the expected features meets the preset condition.

[0065] The features extracted by the convolutional neural network include at least one of the number of nodes of the training sample, the resource size occupied by the node, and the association relationship of the node data. These features are used to identify custom (customized) modules or high operation density modules.

[0066] The general integrated circuit module includes at least one of NPU, NFU, and TPU.

[0067] In one embodiment, the nodes in the two lists in the step 3 are stored in layers, and the nodes in each layer are arranged in order of resource size.

[0068] Figure 3 A specific example of the feature list and the non-feature list is shown, Figure 3 The two lists are based on Figure 2 the hierarchical design tree. Figure 2Nodes in medium-dark gray represent nodes with features, while white nodes represent nodes without features. They are placed in two lists according to their level. Furthermore, nodes in each level can be sorted by resource usage. For example, nodes at level 3 in the feature list can be sorted from highest to lowest resource usage. Meanwhile, nodes at level 3 in the featureless list can be sorted from lowest to highest resource usage.

[0069] In one embodiment, in step 4 above, the nodes in the feature list are traversed in order from bottom to top. If the parent node of the selected module is still in the feature list, its parent node is retained and all child nodes of its parent node are deleted from both lists. Figure 2 For example, during the traversal of level 3, if node i's parent node d is in the feature list, nodes i and j are removed from both lists. Similarly, nodes k and l are removed. When reaching node m, if node h's resource meets the constraints but is in the featureless list, and m's sibling node o is also in the featureless list, node h is removed and nodes m, n, and o are placed in level 2. This loop traversal continues until the end of level 0.

[0070] Figure 4 This section illustrates a specific implementation process for the feature extraction and comparator of the present invention. This feature extraction and comparator is based on a convolutional neural network. The training sample is a netlist of a generic IP (or user-customized IP). A data flow graph generator generates a data flow graph. The convolutional neural network is then used for training. The output is compared with the expected result using cosine similarity (or other similarity comparison methods). The parameters of the convolutional neural network are adjusted to ensure that the feature extraction and comparator extracts netlist features as accurately as possible. The feature extraction and comparator, with the adjusted parameters, is then used in the hypergraph generation process.

[0071] In the above step 5, if the number of all nodes in the two lists does not meet the node number constraint, then traverse all the nodes that have not been merged from the bottom layer of the feature list in the order of resource occupancy from large to small. Every time a feature node is traversed, traverse from the bottom layer of the featureless list in the order of resource occupancy from small to large, find the featureless node that has an upper-level association relationship with the currently traversed feature node, and determine whether the sum of the resources occupied by the two nodes meets the resource constraint condition. If the resource constraint condition is met, merge the two nodes. If not, continue to traverse the next feature node.

[0072] After each merge, determine whether the number of all nodes in the two lists meets the node number constraint. If so, stop traversing the feature list; otherwise, continue traversing the feature list.

[0073] The present application arranges the nodes of each level of the two lists of the feature list and the non-feature list in order of resource occupation size, so that the merging algorithm is simpler when merging the nodes, and the present application only needs to traverse the corresponding feature nodes when the node quantity constraint is not met, and since the corresponding non-feature nodes are traversed in order of resource occupation from small to large, the non-feature nodes found at present which have an upper association relationship with the currently traversed feature nodes must be the non-feature nodes with the least current resource occupation which meet other conditions, and if the sum of the resources occupied by the two nodes cannot meet the resource constraint condition, then the traversal of the non-feature list can be directly ended, because the next traversed non-feature node, even if it has an upper association relationship with the currently traversed feature node, the sum of their resources must also not meet the resource constraint condition, so that the loop iteration process of the traversal of the non-feature list can be saved. In addition, the present application traverses the feature nodes in order of resource occupation from large to small, and traverses the non-feature nodes in order of resource occupation from small to large, which can also make the resource occupation of the merged nodes as balanced as possible with the resource occupation of the existing nodes, and will not cause the feature nodes with large resource occupation to be merged with the non-feature nodes with large resource occupation, resulting in unbalanced resource occupation among the nodes.

[0074] The supergraph generation system proposed by the present application is also generated by using the supergraph generation method of the present application.

[0075] Figure 5 A specific embodiment of the simulation system of the circuit of the present application is shown, in which the simulation system of the circuit comprises a netlist parser, a data flow graph generator, a feature extraction comparator, a supergraph selection generator, a supergraph partitioner, a netlist generator and a simulation tool. Among them, the netlist parser, the data flow graph generator, the feature extraction comparator and the supergraph selection generator belong to the constituent parts of the supergraph generation system of the present application.

[0076] The netlist parser is used to parse the netlist design of the circuit, and to construct the corresponding hierarchical design tree based on the netlist design;

[0077] The data flow graph generator generates the data flow graph of each module corresponding to each node of the hierarchical design tree;

[0078] The feature extraction comparator performs feature analysis on each module based on the data flow graph of each module, and distinguishes between the undesired partition modules and other modules;

[0079] The hypergraph selection generator adjusts nodes of the hypergraph based on the undesired partition module and other modules and a node number constraint until the node number constraint is satisfied.

[0080] Further, the hypergraph selection generator also needs to consider the resource constraint conditions of each hardware (FPGA) when adjusting the nodes of the hypergraph. The circuit simulation method of the present application also adopts the technical scheme of the above-mentioned hypergraph generation method. The circuit simulation method of the present application first generates a hypergraph for the netlist design of the circuit by using the hypergraph generation method of the above-mentioned technical scheme, then partitions the circuit according to the generated hypergraph, and finally performs parallel simulation processing on each partitioned circuit part.

[0081] The present application divides the complex logic of high-density high-parallel computation as an independent node in the design partition stage, so that the complex logic of high-density operation can be simulated at a high operation frequency in the hardware simulator.

[0082] The hypergraph generation, partition and simulation system of the present application is shown in Figure 5 The netlist parser is used to obtain the netlist and generate a design hierarchy tree. The data flow graph generator is used to generate a data flow graph of the module. The feature extraction comparator is used to extract the data flow graph features of the netlist and put the obtained module into a feature list and a non-feature list. The hypergraph selection generator is used to select hypergraph nodes based on the feature list and output a hypergraph file. The hypergraph partitioner is used to partition the obtained hypergraph. The netlist generator is used to generate a partitioned netlist based on the partitioning result of the hypergraph. The simulation tool is used to perform parallel simulation processing on the partitioned netlist.

[0083] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for generating a hypergraph, characterized in that: include: Step 1: Build a corresponding hierarchical design tree based on the netlist design; Step 2: generating a data flow graph for each module corresponding to each node of the hierarchical design tree; Step 3: Perform feature analysis on each module based on its data flow graph, put the nodes corresponding to the modules that match the features of the modules that are not expected to be split into a feature list, and put the nodes corresponding to other modules into a featureless list; Step 4: traverse the nodes in the feature list. If the parent node of the currently traversed node is also in the feature list, delete the child nodes of the parent node in both lists. Step 5: After the traversal is completed, determine whether the number of all nodes in the two lists meets the node number constraint. If so, use the remaining nodes in the two lists as hypergraph nodes to generate a hypergraph.

2. The method for generating a hypergraph according to claim 1, wherein: The step 1 comprises: Obtain all modules in the netlist design; Process all modules in parallel to generate corresponding subtrees; According to the parent-child relationship of each module, all subtrees are spliced ​​into the hierarchical design tree.

3. The method for generating a hypergraph according to claim 1, wherein: In step 3, feature analysis is performed on each module by pre-constructing a feature extraction and comparison device, and constructing the feature extraction and comparison device includes: Using a general integrated circuit module and / or a customized integrated circuit module as a training sample; Generate data flow graphs for all training samples; Use convolutional neural networks to train and learn data flow graphs; Until the similarity between the features extracted by the convolutional neural network and the expected features meets the preset conditions.

4. The method for generating a hypergraph according to claim 3, wherein: The features extracted by the convolutional neural network include at least one of the number of nodes in the training sample, the size of resources occupied by the nodes, and the association relationship of node data.

5. The method for generating a hypergraph according to claim 3, wherein: The universal integrated circuit module includes at least one of NPU, NFU, and TPU.

6. The method for generating a hypergraph according to claim 1, wherein: In step 3, each node is traversed layer by layer starting from the bottom layer of the hierarchical design tree, and the data flow graph of the module corresponding to each traversed node is subjected to feature analysis.

7. The method for generating a hypergraph according to claim 1, wherein: In step 3, the nodes in the two lists are stored hierarchically, and the nodes in each layer are arranged in order according to the size of the occupied resources.

8. The method for generating a hypergraph as claimed in claim 1, wherein: In step 4, the nodes in the feature list are traversed in order from bottom to top of the hierarchy.

9. The method for generating a hypergraph according to claim 7, wherein: In step 5, if the number of all nodes in the two lists does not meet the node number constraint, then all nodes that have not been merged in the bottom layer of the feature list are traversed in descending order, and each time a feature node is traversed, the bottom layer of the non-feature list is traversed in descending order, and each time a non-feature node is traversed, it is determined whether the currently traversed non-feature node has an upper-layer association relationship with the currently traversed feature node. If so, it is determined whether the resources occupied by the currently traversed non-feature node and the currently traversed feature node meet the resource constraint condition. If so, the two nodes are merged and placed in the feature list; If not, continue to traverse the next node without features; after merging, determine whether the number of nodes in the current two lists meets the node number constraint. If not, continue to traverse the next node with features.

10. A hypergraph generation system, characterized in that: Generating a hypergraph using the hypergraph generation method according to any one of claims 1 to 9, comprising: Netlist parser, which parses the circuit netlist design and builds a corresponding hierarchical design tree based on the netlist design; A data flow graph generator generates a data flow graph for each module corresponding to each node of the hierarchical design tree; Feature extraction and comparison, which performs feature analysis on each module based on its data flow graph to distinguish undesirable segmentation modules from other modules; The hypergraph selection generator adjusts the nodes of the hypergraph based on the undesired split modules and other modules as well as the node number constraint until the node number constraint is met.

11. A circuit simulation method, characterized in that: include: Generating a hypergraph by using the hypergraph generation method according to any one of claims 1 to 9 for the netlist design of the circuit; partitioning the circuit according to the generated hypergraph; The divided circuit parts are simulated in parallel.

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