A shader architecture that texture unit and cache multiplex

Abstract

The application discloses a shader architecture of texture unit and cache multiplexing. In the application, the data of the whole memory space is mapped to different single-port caches according to the low bits of the address, so that a plurality of read interfaces are provided, as shown in Fig. 3. The requests of the plurality of ports are combined by an address combining unit, and the request of each port is mapped to a certain single-port cache in the interior. After the data of all port requests are returned, the multi-port cache outputs the data. In the application, a unified shader architecture of texture unit and cache multiplexing is provided. The architecture has the following advantages: the vertex shader and the pixel shader have consistent architectures; no additional unit is needed to process different requests, so that the on-chip resources are saved; the design of the multi-port cache improves the request efficiency of the parallel multiple processing units.

Description

Technical Field

[0001] This invention belongs to the field of computer graphics technology, specifically a shader architecture that reuses texture units and cache. Background Technology

[0002] Shaders are used to implement image rendering, replacing editable programs with fixed rendering pipelines. Vertex shaders are primarily responsible for calculations such as vertex geometry and require access to vertex information; pixel shaders are primarily responsible for calculations such as source color and require access to texture information. Vertex data is typically managed using a cache, while texture information requires additional texture units to manage requests. In typical architectures, the cache and texture units are two separate modules.

[0003] US Patent Application US202217583151A discloses a graphics processing system including geometry processing logic, rasterization, and a texturer. The geometry processing logic uses a cache to cache vertex data, while the texture unit retrieves texture data directly from memory.

[0004] However, this approach provides a graphics processing system architecture, but only the pixel shader is programmable, the geometry stage uses a fixed pipeline, and the geometry stage cache is not shared with the pixel shader. Summary of the Invention

[0005] The purpose of this invention is to provide a shader architecture that reuses texture units and cache in order to solve the problems mentioned above.

[0006] The technical solution adopted in this invention is as follows: a shader architecture that reuses texture units and cache, the texture unit and cache reuse shader architecture includes: texture unit and shader architecture, the texture unit and shader architecture are connected by a private bus.

[0007] In a preferred embodiment, the operation flow of the texture unit and cache-reused shader architecture includes the following steps:

[0008] S1: During the vertex coloring phase, vertex data is requested via the vertex bus;

[0009] S2: During the pixel coloring stage, texture data is requested via the texture bus.

[0010] In a preferred embodiment, in step S1, during the vertex coloring stage, the colorist directly requests vertex data via the vertex private bus using the address request. After the vertex request is sent to the texture unit, it is directly passed through to the cache. The cache then directly returns the data to the colorist via the vertex private bus.

[0011] In a preferred embodiment, in step S2, during the pixel coloring stage, the colorist requests texture data using texture coordinates and texture ID via the pixel private bus. After the texture request is sent to the texture unit, it first retrieves texture information from the texture lookup table based on the texture ID; then, based on the texture information and texture coordinates, it converts the request into an address and retrieves the data from the cache; after retrieving the data, it decodes it based on the texture information and finally returns it to the colorist via the bus.

[0012] In a preferred embodiment, the multi-port cache internally maps data from the entire memory space to different single-port caches based on the low-order bits of the address, such as... Figure 3 As shown, this provides multiple read interfaces. Requests from multiple ports are merged through an address merging unit, mapping each port's request to a specific internal single-port cache. After all port request data has been returned, the multi-port cache outputs the data.

[0013] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0014] This invention proposes a unified shader architecture that reuses texture units and cache. The advantages of this architecture are: consistent vertex and pixel shader architectures; no need for additional units to handle different requests, saving on-chip resources; and improved request efficiency for multiple parallel processing units through a multi-port cache design. Attached Figure Description

[0015] Figure 1 This is a system framework diagram of the present invention;

[0016] Figure 2 This is a diagram of the multi-port cache architecture in this invention;

[0017] Figure 3 This is the cache memory mapping diagram in this invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0019] Reference Figure 1-3 ,

[0020] Example:

[0021] A shader architecture that reuses texture units and cache, comprising: texture units and shader architecture, wherein the texture units and shader architecture are connected by a private bus.

[0022] The operation flow of the shader architecture that reuses texture units and cache includes the following steps:

[0023] S1: During the vertex coloring phase, vertex data is requested via the vertex bus;

[0024] S2: During the pixel coloring stage, texture data is requested via the texture bus.

[0025] In step S1, during the vertex coloring stage, the colorist directly requests vertex data via the vertex private bus using the address request. After the vertex request is sent to the texture unit, it is directly passed through to the cache. The cache then directly returns the data to the colorist via the vertex private bus.

[0026] In step S2, during the pixel coloring stage, the colorizer requests texture data using texture coordinates and texture ID via the pixel private bus. After the texture request is sent to the texture unit, it first retrieves the texture information from the texture lookup table based on the texture ID; then, based on the texture information and texture coordinates, it converts the request into an address and retrieves the data from the cache; after retrieving the data, it decodes it based on the texture information and finally returns it to the colorizer via the bus.

[0027] The multi-port cache internally maps data from the entire memory space to different single-port caches based on the low-order bits of the address, such as... Figure 3 As shown, this provides multiple read interfaces. Requests from multiple ports are merged through an address merging unit, mapping each port's request to a specific internal single-port cache. After all port request data has been returned, the multi-port cache outputs the data.

[0028] This invention proposes a unified shader architecture that reuses texture units and cache. The advantages of this architecture are: consistent vertex and pixel shader architectures; no need for additional units to handle different requests, saving on-chip resources; and improved request efficiency for multiple parallel processing units through a multi-port cache design.

[0029] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0030] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A shader architecture that reuses texture units and cache, characterized in that: The texture unit and cache reuse shader architecture includes: texture unit and shader architecture; The texture unit and the shader architecture are connected via a private bus. The operation flow of the shader architecture that reuses texture units and cache includes the following steps: S1: During the vertex coloring phase, vertex data is requested via the vertex bus; S2: During the pixel coloring stage, texture data is requested via the texture bus; In step S1, during the vertex coloring stage, the colorist requests vertex data directly through the vertex private bus using the address; after the vertex request is sent to the texture unit, it is directly passed through to the cache; the cache directly returns the data to the colorist through the vertex private bus. In step S2, during the pixel coloring stage, the colorizer requests texture data using texture coordinates and texture ID via the pixel private bus. After the texture request is sent to the texture unit, it first retrieves the texture information from the texture lookup table based on the texture ID. Then, based on the texture information and texture coordinates, it converts the request into an address and retrieves the data from the cache. After retrieving the data, it decodes it based on the texture information and finally returns it to the colorizer via the bus. Internally, the cache provides multiple read interfaces by mapping the data of the entire memory space to different single-port caches according to the low-order bits of the address. Requests from multiple ports are merged through an address merging unit, which maps the request of each port to a specific single-port cache. After all port requests have returned data, the multi-port cache outputs the data.

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